CA1270064A - Ordinateur numerique a elements de memoire intercalaires - Google Patents

Ordinateur numerique a elements de memoire intercalaires

Info

Publication number: CA1270064A
Authority: CA; Canada
Prior art keywords: cache; memory; data; access; digital computer
Prior art date: 1985-07-22
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

CA000595112A

Other languages

English (en)

Inventor

Robert L. Fredieu

Richard T. Mcandrew

Craig J. Mundie

Ronald H. Gruner

James E. Veres

William K. Stewart

Mathew J. Myszewski

Michael L. Ziegler

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Alliant Computer Systems Corp

Original Assignee

Alliant Computer Systems Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1985-07-22

Filing date

1989-03-29

Publication date

1990-06-05

1985-07-22 Priority claimed from US06/757,853 external-priority patent/US4783736A/en

1986-06-18 Priority claimed from CA000511838A external-priority patent/CA1264493A1/fr

1989-03-29 Application filed by Alliant Computer Systems Corp filed Critical Alliant Computer Systems Corp

1989-03-29 Priority to CA000595112A priority Critical patent/CA1270064A/fr

1990-06-05 Application granted granted Critical

1990-06-05 Publication of CA1270064A publication Critical patent/CA1270064A/fr

2007-06-05 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

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Landscapes

Memory System Of A Hierarchy Structure (AREA)

CA000595112A 1985-07-22 1989-03-29 Ordinateur numerique a elements de memoire intercalaires Expired - Fee Related CA1270064A (fr)

Priority Applications (1)

Application Number	Priority Date	Filing Date	Title
CA000595112A CA1270064A (fr)	1985-07-22	1989-03-29	Ordinateur numerique a elements de memoire intercalaires

Applications Claiming Priority (8)

Application Number	Priority Date	Filing Date	Title
US75774585A	1985-07-22	1985-07-22
US75774985A	1985-07-22	1985-07-22
US757,853		1985-07-22
US06/757,853 US4783736A (en)	1985-07-22	1985-07-22	Digital computer with multisection cache
US757,749		1985-07-22
US757,745		1985-07-22
CA000511838A CA1264493A1 (fr)	1985-07-22	1986-06-18	Ordinateur numerique a processeurs paralleles
CA000595112A CA1270064A (fr)	1985-07-22	1989-03-29	Ordinateur numerique a elements de memoire intercalaires

Publications (1)

Publication Number	Publication Date
CA1270064A true CA1270064A (fr)	1990-06-05

Family

ID=27426435

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
CA000595112A Expired - Fee Related CA1270064A (fr)	1985-07-22	1989-03-29	Ordinateur numerique a elements de memoire intercalaires

Country Status (1)

Country	Link
CA (1)	CA1270064A (fr)

1989
- 1989-03-29 CA CA000595112A patent/CA1270064A/fr not_active Expired - Fee Related

Legal Events

Date	Code	Title	Description
1993-12-06	MKLA	Lapsed

Publication	Publication Date	Title
US4783736A (en)	1988-11-08	Digital computer with multisection cache
US4794521A (en)	1988-12-27	Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
EP0214718A2 (fr)	1987-03-18	Calculatrice numérique
US5043873A (en)	1991-08-27	Method of parallel processing for avoiding competition control problems and data up dating problems common in shared memory systems
KR100308677B1 (ko)	2001-10-19	복수l1캐쉬라인의파이프라인형스누핑
US4945479A (en)	1990-07-31	Tightly coupled scientific processing system
EP0325419B1 (fr)	1994-08-10	Méthode et dispositif pour mettre en antémémoire des variables interverrouillées dans une antémémoire intégrée
EP0352632B1 (fr)	1998-01-07	Procédé et appareil destiné à la prédiction de l'exécution correcte de traductions d'adresses virtuelles en adresses physiques
KR101123443B1 (ko)	2012-06-12	프로세서 시스템에서 명령어 레벨에서의 자원 할당 식별을 가능하게 하는 방법 및 장치
KR101626533B1 (ko)	2016-06-01	가비지 콜렉션을 위한 ｇｐｕ 서포트
US5734817A (en)	1998-03-31	Method for making a data base available to a user program during data base recovery
US5293500A (en)	1994-03-08	Parallel processing method and apparatus
KR100308682B1 (ko)	2001-10-19	다중방향연관외부마이크로프로세서캐쉬
EP0375950A2 (fr)	1990-07-04	Méthode et mise en oeuvre sous forme matérielle d'instructions de transfert de données complexes
JPH08278886A (ja)	1996-10-22	データ処理システムでの拡張システム管理操作のための方法およびシステム
US5339429A (en)	1994-08-16	Parallel processing system and compiling method used therefor
EP0325420A2 (fr)	1989-07-26	Organisation d'une unité cache intégrée pour l'utilisation flexible dans la conception de systèmes cache
EP0325421A2 (fr)	1989-07-26	Organisation d'un antémémoire intégrée à usage flexible pour supporter des opérations de multiprocesseurs
EP0374419A2 (fr)	1990-06-27	Méthode et dispositif pour générer des boucles d'itération par matériel et microcode
JPH06187241A (ja)	1994-07-08	変換索引バッファのコヒーレンス維持方法及びシステム
Schneck	2012	Supercomputer architecture
Liptay	1992	Design of the IBM Enterprise System/9000 high-end processor
US6012135A (en)	2000-01-04	Computer having multiple address ports, each having logical address translation with base and limit memory management
EP0325422B1 (fr)	1996-05-15	Unité d'antémémoire intégrée
US5434986A (en)	1995-07-18	Interdependency control of pipelined instruction processor using comparing result of two index registers of skip instruction and next sequential instruction