CA1283462C - Generation de signaux d'horloge biphases - Google Patents

Generation de signaux d'horloge biphases

Info

Publication number
CA1283462C
CA1283462C CA000580486A CA580486A CA1283462C CA 1283462 C CA1283462 C CA 1283462C CA 000580486 A CA000580486 A CA 000580486A CA 580486 A CA580486 A CA 580486A CA 1283462 C CA1283462 C CA 1283462C
Authority
CA
Canada
Prior art keywords
clock
input
output
latch
settable latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CA000580486A
Other languages
English (en)
Inventor
Nayan Mehta
Stephen Kenneth Sunter
Philip Stanley Wilcox
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Priority to CA000580486A priority Critical patent/CA1283462C/fr
Application granted granted Critical
Publication of CA1283462C publication Critical patent/CA1283462C/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
CA000580486A 1988-10-18 1988-10-18 Generation de signaux d'horloge biphases Expired - Lifetime CA1283462C (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA000580486A CA1283462C (fr) 1988-10-18 1988-10-18 Generation de signaux d'horloge biphases

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA000580486A CA1283462C (fr) 1988-10-18 1988-10-18 Generation de signaux d'horloge biphases

Publications (1)

Publication Number Publication Date
CA1283462C true CA1283462C (fr) 1991-04-23

Family

ID=4138935

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000580486A Expired - Lifetime CA1283462C (fr) 1988-10-18 1988-10-18 Generation de signaux d'horloge biphases

Country Status (1)

Country Link
CA (1) CA1283462C (fr)

Similar Documents

Publication Publication Date Title
US5259006A (en) Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
US5731715A (en) Glitch-free clock enable circuit
US4714924A (en) Electronic clock tuning system
US5087828A (en) Timing circuit for single line serial data
US6064247A (en) Multiple frequency clock generation and synchronization
US5406216A (en) Technique and method for asynchronous scan design
CA2201695A1 (fr) Detecteur de phase permettant d'extraire rapidement les signaux d'horloge incorpores a des signaux binaires aleatoires
EP0404127B1 (fr) Générateur de signal
US4912340A (en) Circuit for generating non-overlapping two-phase clocks
US6710637B1 (en) Non-overlap clock circuit
US6535048B1 (en) Secure asynchronous clock multiplexer
EP0401865B1 (fr) Circuit VLSI à verrous contrÔlés par un générateur d'horloge apparié et proche
US6255878B1 (en) Dual path asynchronous delay circuit
US5093565A (en) Apparatus for sequential optical systems where an independently controllable transmission gate is interposed between successive optoelectronic gates
US4317053A (en) High speed synchronization circuit
US5767718A (en) High speed conditional synchronous one shot circuit
US20050055614A1 (en) Multi-clock domain logic system and related method
US4949360A (en) Synchronizing circuit
US20190173458A1 (en) Shift register utilizing latches controlled by dual non-overlapping clocks
CA1283462C (fr) Generation de signaux d'horloge biphases
KR101629231B1 (ko) 데이터 홀드 기능을 갖는 도미노 로직 블록 및 그것을 구비한 도미노 로직
US4654599A (en) Four phase clock signal generator
JP4215919B2 (ja) Dllクロック発生器
Moyer et al. Precise delay generation using the Vernier technique
Hoyer et al. Locally-clocked dynamic logic

Legal Events

Date Code Title Description
MKLA Lapsed