CA1301369C - Boitier hermetique a reseau de broches matriciel - Google Patents

Boitier hermetique a reseau de broches matriciel

Info

Publication number
CA1301369C
CA1301369C CA000585310A CA585310A CA1301369C CA 1301369 C CA1301369 C CA 1301369C CA 000585310 A CA000585310 A CA 000585310A CA 585310 A CA585310 A CA 585310A CA 1301369 C CA1301369 C CA 1301369C
Authority
CA
Canada
Prior art keywords
base
pins
package
pin
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CA000585310A
Other languages
English (en)
Inventor
Kenneth A. Trevellyan
Kenneth L. Ii Jones
Tom R. O'connor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cabot Electronics Ceramics Inc
Original Assignee
Cabot Electronics Ceramics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cabot Electronics Ceramics Inc filed Critical Cabot Electronics Ceramics Inc
Application granted granted Critical
Publication of CA1301369C publication Critical patent/CA1301369C/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Connections Arranged To Contact A Plurality Of Conductors (AREA)
CA000585310A 1987-12-09 1988-12-08 Boitier hermetique a reseau de broches matriciel Expired - Lifetime CA1301369C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/130,469 US4861944A (en) 1987-12-09 1987-12-09 Low cost, hermetic pin grid array package
US130,469 1987-12-09

Publications (1)

Publication Number Publication Date
CA1301369C true CA1301369C (fr) 1992-05-19

Family

ID=22444836

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000585310A Expired - Lifetime CA1301369C (fr) 1987-12-09 1988-12-08 Boitier hermetique a reseau de broches matriciel

Country Status (6)

Country Link
US (1) US4861944A (fr)
EP (1) EP0345342A4 (fr)
JP (1) JPH02502502A (fr)
KR (1) KR900701144A (fr)
CA (1) CA1301369C (fr)
WO (1) WO1989005571A1 (fr)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0384599A1 (fr) * 1989-02-03 1990-08-29 General Electric Company Structure d'essai pour circuit intégré et méthode d'essai
US5006922A (en) * 1990-02-14 1991-04-09 Motorola, Inc. Packaged semiconductor device having a low cost ceramic PGA package
US5081327A (en) * 1990-03-28 1992-01-14 Cabot Corporation Sealing system for hermetic microchip packages
US5050296A (en) * 1990-06-07 1991-09-24 International Business Machines Corporation Affixing pluggable pins to a ceramic substrate
US5045639A (en) * 1990-08-21 1991-09-03 Tong Hsing Electronic Industries Ltd. Pin grid array package
US5233131A (en) * 1990-12-19 1993-08-03 Vlsi Technology, Inc. Integrated circuit die-to-leadframe interconnect assembly system
JP2772739B2 (ja) * 1991-06-20 1998-07-09 いわき電子株式会社 リードレスパッケージの外部電極構造及びその製造方法
US5361966A (en) * 1992-03-17 1994-11-08 Kabushiki Kaisha Tokai Rika Denki Seisakusho Solder-bonded structure
JP2988603B2 (ja) * 1992-08-20 1999-12-13 株式会社豊田自動織機製作所 半導体パッケージ
US5589669A (en) * 1995-12-28 1996-12-31 Emc Corporation Electrical contact for printed circuit boards
JPH10275966A (ja) * 1997-01-30 1998-10-13 Ibiden Co Ltd プリント配線板及びその製造方法
US5952716A (en) * 1997-04-16 1999-09-14 International Business Machines Corporation Pin attach structure for an electronic package
US6448106B1 (en) 1999-11-09 2002-09-10 Fujitsu Limited Modules with pins and methods for making modules with pins
US6639154B1 (en) * 2000-10-10 2003-10-28 Teradyne, Inc. Apparatus for forming a connection between a circuit board and a connector, having a signal launch
AU2003901146A0 (en) * 2003-03-12 2003-03-27 Cochlear Limited Feedthrough assembly
KR100757910B1 (ko) * 2006-07-06 2007-09-11 삼성전기주식회사 매립패턴기판 및 그 제조방법
JP2009164173A (ja) * 2007-12-28 2009-07-23 Fujitsu Ltd 基板ユニットおよびその製造方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3103547A (en) * 1963-09-10 ansley
US2450340A (en) * 1944-02-03 1948-09-28 Mallory & Co Inc P R Silver base alloy for metal evaporation
US2586854A (en) * 1947-04-19 1952-02-26 Farnsworth Res Corp Printed circuit construction
US3006069A (en) * 1957-05-23 1961-10-31 Rca Corp Method of sealing a metal member to a ceramic member
GB854593A (en) * 1957-09-11 1960-11-23 British Telecomm Res Ltd Improvements in electrical connecting arrangements
US3205297A (en) * 1962-08-03 1965-09-07 Thompson Ramo Wooldridge Inc Electrical connection utilizing tamped gold foil
US3254279A (en) * 1963-04-17 1966-05-31 Cohn James Composite alloy electric contact element
US3307246A (en) * 1963-12-23 1967-03-07 Ibm Method for providing multiple contact terminations on an insulator
US3257704A (en) * 1964-05-04 1966-06-28 Hafner Erich Method of mounting high frequency piezoelectric crystals
US3281923A (en) * 1964-08-27 1966-11-01 Corning Glass Works Method of attaching leads to thin films
US3385618A (en) * 1965-05-26 1968-05-28 American Lava Corp Ceramic-to-metal seal
GB1177831A (en) * 1967-01-23 1970-01-14 J & S Engineers Ltd Methods and Apparatus for Providing Connections Between Printed Circuits
US3489879A (en) * 1967-02-09 1970-01-13 Microtek Electronics Inc Thermoswaging method for fixing pins to ceramic wafers
US3568301A (en) * 1968-03-30 1971-03-09 Chugai Electric Ind Co Ltd Bonding of precious metal to a metal substrate and product therefor
US3545606A (en) * 1968-06-11 1970-12-08 Benny Morris Bennett Flexible tape terminal assembly
US3730969A (en) * 1972-03-06 1973-05-01 Rca Corp Electronic device package
US3981724A (en) * 1974-11-06 1976-09-21 Consolidated Refining Company, Inc. Electrically conductive alloy
US3941297A (en) * 1975-06-02 1976-03-02 Western Electric Company, Inc. Method and apparatus for simultaneously bonding a plurality of lead frames to a plurality of planar articles
DE2812768C3 (de) * 1978-03-23 1987-05-07 Stettner & Co, 8560 Lauf Elektrisches Bauelement mit Anschlußdrähten zum Einstecken in Bohrungen der Platte einer gedruckten Schaltung
US4631821A (en) * 1981-01-07 1986-12-30 International Business Machines Corporation Method for joining metal components to a substrate
EP0082216B1 (fr) * 1981-12-23 1985-10-09 Ibm Deutschland Gmbh Substrat céramique multicouche pour circuits intégrés à semiconducteurs à niveau de métallisation multiples
US4412642A (en) * 1982-03-15 1983-11-01 Western Electric Co., Inc. Cast solder leads for leadless semiconductor circuits
US4550493A (en) * 1984-02-08 1985-11-05 International Business Machines Corporation Apparatus for connecting contact pins to a substrate
GB2162167B (en) * 1984-06-01 1988-01-20 Narumi China Corp Ceramic substrate material
JPS62279695A (ja) * 1986-05-29 1987-12-04 株式会社住友金属セラミックス セラミツク多層配線基板

Also Published As

Publication number Publication date
US4861944A (en) 1989-08-29
KR900701144A (ko) 1990-08-17
JPH02502502A (ja) 1990-08-09
WO1989005571A1 (fr) 1989-06-15
EP0345342A4 (en) 1991-03-27
EP0345342A1 (fr) 1989-12-13

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