CA1306310C - Systeme informatique reparti - Google Patents

Systeme informatique reparti

Info

Publication number
CA1306310C
CA1306310C CA000551788A CA551788A CA1306310C CA 1306310 C CA1306310 C CA 1306310C CA 000551788 A CA000551788 A CA 000551788A CA 551788 A CA551788 A CA 551788A CA 1306310 C CA1306310 C CA 1306310C
Authority
CA
Canada
Prior art keywords
data
bus
memory
node
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CA000551788A
Other languages
English (en)
Inventor
Shreyaunsh R. Shah
Rona J. Newmark
Jeffrey F. Hatalsky
Rosemarie Alicandro
Eric H. Enberg
Leo C. Waible, Iii
Donald D. Burn
Paul W. Woodbury
Michael A. Pogue
Morgan J. Dempsey
David I. Epstein
Peter C. Bixby
Paul K. Marino
Mark D. Hummel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMC Corp
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Priority to CA000551788A priority Critical patent/CA1306310C/fr
Application granted granted Critical
Publication of CA1306310C publication Critical patent/CA1306310C/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
CA000551788A 1987-11-13 1987-11-13 Systeme informatique reparti Expired - Lifetime CA1306310C (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA000551788A CA1306310C (fr) 1987-11-13 1987-11-13 Systeme informatique reparti

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA000551788A CA1306310C (fr) 1987-11-13 1987-11-13 Systeme informatique reparti

Publications (1)

Publication Number Publication Date
CA1306310C true CA1306310C (fr) 1992-08-11

Family

ID=4136837

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000551788A Expired - Lifetime CA1306310C (fr) 1987-11-13 1987-11-13 Systeme informatique reparti

Country Status (1)

Country Link
CA (1) CA1306310C (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114980033A (zh) * 2021-02-26 2022-08-30 维沃移动通信有限公司 原生算力业务实现方法、装置、网络设备及终端
CN116386145A (zh) * 2023-04-17 2023-07-04 浙江金融职业学院 一种基于双摄像头的银行内人员异常行为识别方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114980033A (zh) * 2021-02-26 2022-08-30 维沃移动通信有限公司 原生算力业务实现方法、装置、网络设备及终端
CN116386145A (zh) * 2023-04-17 2023-07-04 浙江金融职业学院 一种基于双摄像头的银行内人员异常行为识别方法
CN116386145B (zh) * 2023-04-17 2023-11-03 浙江金融职业学院 一种基于双摄像头的银行内人员异常行为识别方法

Similar Documents

Publication Publication Date Title
US5287537A (en) Distributed processing system having plural computers each using identical retaining information to identify another computer for executing a received command
US5016162A (en) Contention revolution in a digital computer system
US4920483A (en) A computer memory for accessing any word-sized group of contiguous bits
US4674033A (en) Multiprocessor system having a shared memory for enhanced interprocessor communication
US5598580A (en) High performance channel adapter having a pass through function
US4847750A (en) Peripheral DMA controller for data acquisition system
US4945473A (en) Communications controller interface
USRE38134E1 (en) System for communications where first priority data transfer is not disturbed by second priority data transfer and where allocated bandwidth is removed when process terminates abnormally
US5088033A (en) Data processing system emulation in a window with a coprocessor and I/O emulation
CA1191266A (fr) Systeme de transfert de donnees avec acces direct a la memoire pour systeme a plusieurs processeurs
US5313638A (en) Method using semaphores for synchronizing communication between programs or processes resident in a computer system
EP0525860A2 (fr) Processeur d'entrée/sortie
US4462028A (en) Access control logic for video terminal display memory
US4636174A (en) Cluster computer based education delivery system
US4390964A (en) Input/output subsystem using card reader-peripheral controller
US4782462A (en) Raster scan video controller with programmable prioritized sharing of display memory between update and display processes and programmable memory access termination
US4418343A (en) CRT Refresh memory system
CN112131176A (zh) 一种基于pcie的fpga快速局部重构方法
US4709329A (en) Input/output device controller for a data processing system
US6567837B1 (en) Object oriented processor arrays
CA1321843C (fr) Methode de mise en paquets de donnees
JPH0217818B2 (fr)
US4811284A (en) Computer terminal system with memory shared between remote devices
US4407014A (en) Communications subsystem having a direct connect clock
US5524211A (en) System for employing select, pause, and identification registers to control communication among plural processors

Legal Events

Date Code Title Description
MKLA Lapsed