CA2006704A1 - Circuit pouvant calculer rapidement la somme de plus de deux nombres en virgule flottante - Google Patents

Circuit pouvant calculer rapidement la somme de plus de deux nombres en virgule flottante

Info

Publication number
CA2006704A1
CA2006704A1 CA2006704A CA2006704A CA2006704A1 CA 2006704 A1 CA2006704 A1 CA 2006704A1 CA 2006704 A CA2006704 A CA 2006704A CA 2006704 A CA2006704 A CA 2006704A CA 2006704 A1 CA2006704 A1 CA 2006704A1
Authority
CA
Canada
Prior art keywords
total sum
exponent
parts
fraction
input data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2006704A
Other languages
English (en)
Other versions
CA2006704C (fr
Inventor
Toshihiko Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2006704A1 publication Critical patent/CA2006704A1/fr
Application granted granted Critical
Publication of CA2006704C publication Critical patent/CA2006704C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/012—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising in floating-point computations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49936—Normalisation mentioned as feature only

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Complex Calculations (AREA)
  • Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
  • Error Detection And Correction (AREA)
CA002006704A 1988-12-28 1989-12-27 Circuit pouvant calculer rapidement la somme de plus de deux nombres en virgule flottante Expired - Fee Related CA2006704C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63334316A JP2693800B2 (ja) 1988-12-28 1988-12-28 浮動小数点データ総和演算回路
JP334316/1988 1988-12-28

Publications (2)

Publication Number Publication Date
CA2006704A1 true CA2006704A1 (fr) 1990-06-28
CA2006704C CA2006704C (fr) 1993-12-21

Family

ID=18275991

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002006704A Expired - Fee Related CA2006704C (fr) 1988-12-28 1989-12-27 Circuit pouvant calculer rapidement la somme de plus de deux nombres en virgule flottante

Country Status (6)

Country Link
US (1) US5021986A (fr)
EP (1) EP0376266B1 (fr)
JP (1) JP2693800B2 (fr)
AU (1) AU621788B2 (fr)
CA (1) CA2006704C (fr)
DE (1) DE68923606T2 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5166898A (en) * 1990-09-07 1992-11-24 Nec Corporation Shift amount floating-point calculating circuit with a small amount of hardware and rapidly operable
IE914102A1 (en) 1990-11-26 1992-06-03 Genetics Inst Expression of pace in host cells and methods of use thereof
US5247471A (en) * 1991-12-13 1993-09-21 International Business Machines Corporation Radix aligner for floating point addition and subtraction
EP0593073A1 (fr) * 1992-10-16 1994-04-20 Matsushita Electric Industrial Co., Ltd. Processeur comprenant des registres à décalage
GB2275355B (en) * 1993-02-19 1997-06-18 Motorola Inc Detection of exponent underflow and overflow in a floating point adder
JP2919386B2 (ja) * 1996-09-19 1999-07-12 甲府日本電気株式会社 浮動小数点数検出装置および浮動小数点数検出回路
GB2323189B (en) * 1997-03-14 2001-11-21 Nokia Mobile Phones Ltd Processing multi-bit signals representing floating-point numbers
JP4086459B2 (ja) * 2000-11-13 2008-05-14 Ｎｅｃエレクトロニクス株式会社 固定小数点データ生成方法及び固定小数点データ生成回路
US6751638B2 (en) * 2001-05-11 2004-06-15 Sun Microsystems, Inc. Min and max operations for multiplication and/or division under the simple interval system
US7543013B2 (en) * 2006-08-18 2009-06-02 Qualcomm Incorporated Multi-stage floating-point accumulator
US9274750B2 (en) * 2012-04-20 2016-03-01 Futurewei Technologies, Inc. System and method for signal processing in digital signal processors

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4335372A (en) * 1980-03-28 1982-06-15 Motorola Inc. Digital scaling apparatus
JPS59188740A (ja) * 1983-04-11 1984-10-26 Hitachi Ltd フロ−テイング加算器
US4562553A (en) * 1984-03-19 1985-12-31 Analogic Corporation Floating point arithmetic system and method with rounding anticipation
WO1986001017A1 (fr) * 1984-07-30 1986-02-13 Arya Keerthi Kumarasena Circuit additionneur rapide a entrees multiples
US4734876A (en) * 1985-12-18 1988-03-29 Motorola, Inc. Circuit for selecting one of a plurality of exponential values to a predetermined base to provide a maximum value
EP0265555B1 (fr) * 1986-10-31 1991-09-18 International Business Machines Corporation Procédé et dispositif d'addition de nombres à virgule flottante
AU606559B2 (en) * 1987-12-24 1991-02-07 Nec Corporation Circuit for comparing a plurality of binary inputs

Also Published As

Publication number Publication date
EP0376266A2 (fr) 1990-07-04
EP0376266B1 (fr) 1995-07-26
DE68923606D1 (de) 1995-08-31
EP0376266A3 (fr) 1992-03-04
DE68923606T2 (de) 1996-01-04
JP2693800B2 (ja) 1997-12-24
JPH02178769A (ja) 1990-07-11
AU621788B2 (en) 1992-03-19
CA2006704C (fr) 1993-12-21
US5021986A (en) 1991-06-04
AU4728289A (en) 1990-07-05

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed