CA2014285A1 - Procede de fabrication de structures fines; les structures ainsi obtenues - Google Patents

Procede de fabrication de structures fines; les structures ainsi obtenues

Info

Publication number
CA2014285A1
CA2014285A1 CA2014285A CA2014285A CA2014285A1 CA 2014285 A1 CA2014285 A1 CA 2014285A1 CA 2014285 A CA2014285 A CA 2014285A CA 2014285 A CA2014285 A CA 2014285A CA 2014285 A1 CA2014285 A1 CA 2014285A1
Authority
CA
Canada
Prior art keywords
fabrication
irradiation
removal
regions
inventive process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2014285A
Other languages
English (en)
Other versions
CA2014285C (fr
Inventor
Lloyd R. Harriott
Morton B. Panish
Henryk Temkin
Yuh-Lin Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Inc
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2014285A1 publication Critical patent/CA2014285A1/fr
Application granted granted Critical
Publication of CA2014285C publication Critical patent/CA2014285C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/22—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2907—Materials being Group IIIA-VA materials
    • H10P14/2909—Phosphides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2907—Materials being Group IIIA-VA materials
    • H10P14/2911—Arsenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3218—Phosphides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3221—Arsenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3251—Layer structure consisting of three or more layers
    • H10P14/3252—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3418—Phosphides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3421—Arsenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/246—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/111—Narrow masking

Landscapes

  • Drying Of Semiconductors (AREA)
CA002014285A 1989-04-10 1990-04-10 Procede de fabrication de structures fines; les structures ainsi obtenues Expired - Fee Related CA2014285C (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US33562689A 1989-04-10 1989-04-10
US335,626 1989-04-10
US07/444,579 US5106764A (en) 1989-04-10 1989-11-30 Device fabrication
US444,579 1989-11-30

Publications (2)

Publication Number Publication Date
CA2014285A1 true CA2014285A1 (fr) 1990-10-10
CA2014285C CA2014285C (fr) 1994-06-07

Family

ID=26989806

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002014285A Expired - Fee Related CA2014285C (fr) 1989-04-10 1990-04-10 Procede de fabrication de structures fines; les structures ainsi obtenues

Country Status (6)

Country Link
US (1) US5106764A (fr)
EP (1) EP0400791B9 (fr)
JP (1) JPH0722142B2 (fr)
KR (1) KR940007443B1 (fr)
CA (1) CA2014285C (fr)
DE (1) DE69033879T2 (fr)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0909989A1 (fr) * 1990-09-26 1999-04-21 Canon Kabushiki Kaisha Méthode de traitement et appareillage photolithographique
US5288657A (en) * 1990-11-01 1994-02-22 At&T Bell Laboratories Device fabrication
JPH0555545A (ja) * 1991-08-27 1993-03-05 Matsushita Electric Ind Co Ltd 量子素子の製造方法
JP2757642B2 (ja) * 1991-12-20 1998-05-25 日本電気株式会社 ドライエッチング方法
US5275687A (en) * 1992-11-20 1994-01-04 At&T Bell Laboratories Process for removing surface contaminants from III-V semiconductors
US5346581A (en) * 1993-04-01 1994-09-13 At&T Bell Laboratories Method of making a compound semiconductor device
US5403753A (en) * 1993-07-15 1995-04-04 Texas Instruments Incorporated Method of forming implant indicators for implant verification
US5580419A (en) * 1994-03-23 1996-12-03 Trw Inc. Process of making semiconductor device using focused ion beam for resistless in situ etching, deposition, and nucleation
US5427648A (en) * 1994-08-15 1995-06-27 The United States Of America As Represented By The Secretary Of The Army Method of forming porous silicon
JP4014676B2 (ja) * 1996-08-13 2007-11-28 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置およびその作製方法
SE511314C2 (sv) * 1997-02-07 1999-09-06 Ericsson Telefon Ab L M Framställning av heterobipolär transistor och laserdiod på samma substrat
US20060051508A1 (en) * 2000-12-28 2006-03-09 Ilan Gavish Focused ion beam deposition
US6492261B2 (en) * 2000-12-30 2002-12-10 Intel Corporation Focused ion beam metal deposition
US6638580B2 (en) * 2000-12-29 2003-10-28 Intel Corporation Apparatus and a method for forming an alloy layer over a substrate using an ion beam
US6528427B2 (en) 2001-03-30 2003-03-04 Lam Research Corporation Methods for reducing contamination of semiconductor substrates
DE10163346A1 (de) * 2001-12-21 2003-07-10 Infineon Technologies Ag Resistloses Lithographieverfahren zur Herstellung feiner Strukturen
EP2144117A1 (fr) 2008-07-11 2010-01-13 The Provost, Fellows and Scholars of the College of the Holy and Undivided Trinity of Queen Elizabeth near Dublin Procédé et système de fabrication de motifs sur une surface
US8547526B2 (en) * 2009-04-07 2013-10-01 Micron Technology, Inc. Photolithography systems and associated methods of selective die exposure
KR20130106770A (ko) * 2010-07-26 2013-09-30 하마마츠 포토닉스 가부시키가이샤 반도체 디바이스의 제조 방법
EP2880764B1 (fr) 2012-08-06 2019-10-23 Skorpios Technologies, Inc. Procédé et système d'intégration monolithique de circuits de surveillance et de commande de signaux rf
US9337933B2 (en) * 2012-10-19 2016-05-10 Skorpios Technologies, Inc. Integrated optical network unit

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5375854A (en) * 1976-12-17 1978-07-05 Nippon Telegr & Teleph Corp <Ntt> Production fo semiconductor device
JPS5567138A (en) * 1978-11-16 1980-05-21 Jeol Ltd Method of exposure to electron beam
US4377437A (en) * 1981-05-22 1983-03-22 Bell Telephone Laboratories, Incorporated Device lithography by selective ion implantation
US4405710A (en) * 1981-06-22 1983-09-20 Cornell Research Foundation, Inc. Ion beam exposure of (g-Gex -Se1-x) inorganic resists
JPS60128622A (ja) * 1983-12-16 1985-07-09 Hitachi Ltd エツチング法
JPS62281349A (ja) * 1986-05-29 1987-12-07 Seiko Instr & Electronics Ltd 金属パタ−ン膜の形成方法及びその装置
JPS62284939A (ja) * 1986-05-31 1987-12-10 Suzuki Motor Co Ltd 内燃機関の始動制御装置
JPS63116443A (ja) * 1986-11-05 1988-05-20 Seiko Instr & Electronics Ltd Ｆｉｂテスタ
US4853341A (en) * 1987-03-25 1989-08-01 Mitsubishi Denki Kabushiki Kaisha Process for forming electrodes for semiconductor devices using focused ion beams
JP2531690B2 (ja) * 1987-08-03 1996-09-04 株式会社日立製作所 配線薄膜パタ―ンの形成方法及びその装置
US4897361A (en) * 1987-12-14 1990-01-30 American Telephone & Telegraph Company, At&T Bell Laboratories Patterning method in the manufacture of miniaturized devices
GB8806800D0 (en) * 1988-03-22 1988-04-20 British Telecomm Etching methods

Also Published As

Publication number Publication date
CA2014285C (fr) 1994-06-07
JPH0722142B2 (ja) 1995-03-08
KR940007443B1 (ko) 1994-08-18
EP0400791B1 (fr) 2001-12-19
EP0400791A2 (fr) 1990-12-05
US5106764A (en) 1992-04-21
EP0400791B9 (fr) 2002-11-27
DE69033879T2 (de) 2002-08-22
KR900017111A (ko) 1990-11-15
EP0400791A3 (fr) 1991-01-02
DE69033879D1 (de) 2002-01-31
JPH02295115A (ja) 1990-12-06

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