CA2016407A1 - Circuit logique d'interface de poursuite - Google Patents

Circuit logique d'interface de poursuite

Info

Publication number
CA2016407A1
CA2016407A1 CA 2016407 CA2016407A CA2016407A1 CA 2016407 A1 CA2016407 A1 CA 2016407A1 CA 2016407 CA2016407 CA 2016407 CA 2016407 A CA2016407 A CA 2016407A CA 2016407 A1 CA2016407 A1 CA 2016407A1
Authority
CA
Canada
Prior art keywords
interface circuit
comparator
tracking interface
logic
logic tracking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA 2016407
Other languages
English (en)
Other versions
CA2016407C (fr
Inventor
John Anthony Wolczanski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Priority to CA 2016407 priority Critical patent/CA2016407C/fr
Publication of CA2016407A1 publication Critical patent/CA2016407A1/fr
Application granted granted Critical
Publication of CA2016407C publication Critical patent/CA2016407C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018535—Interface arrangements of Schottky barrier type [MESFET]
    • H03K19/018542—Interface arrangements of Schottky barrier type [MESFET] with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Logic Circuits (AREA)
CA 2016407 1990-05-09 1990-05-09 Circuit logique d'interface de poursuite Expired - Fee Related CA2016407C (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA 2016407 CA2016407C (fr) 1990-05-09 1990-05-09 Circuit logique d'interface de poursuite

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA 2016407 CA2016407C (fr) 1990-05-09 1990-05-09 Circuit logique d'interface de poursuite

Publications (2)

Publication Number Publication Date
CA2016407A1 true CA2016407A1 (fr) 1991-11-09
CA2016407C CA2016407C (fr) 1996-08-06

Family

ID=4144950

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2016407 Expired - Fee Related CA2016407C (fr) 1990-05-09 1990-05-09 Circuit logique d'interface de poursuite

Country Status (1)

Country Link
CA (1) CA2016407C (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116018756A (zh) * 2020-08-19 2023-04-25 索尼半导体解决方案公司 固态成像元件和成像装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116018756A (zh) * 2020-08-19 2023-04-25 索尼半导体解决方案公司 固态成像元件和成像装置

Also Published As

Publication number Publication date
CA2016407C (fr) 1996-08-06

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Legal Events

Date Code Title Description
EEER Examination request
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