CA2017394A1 - Methode et dispositif d'alignement de donnees - Google Patents

Methode et dispositif d'alignement de donnees

Info

Publication number
CA2017394A1
CA2017394A1 CA2017394A CA2017394A CA2017394A1 CA 2017394 A1 CA2017394 A1 CA 2017394A1 CA 2017394 A CA2017394 A CA 2017394A CA 2017394 A CA2017394 A CA 2017394A CA 2017394 A1 CA2017394 A1 CA 2017394A1
Authority
CA
Canada
Prior art keywords
frame pulse
data
sampling
clock
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2017394A
Other languages
English (en)
Other versions
CA2017394C (fr
Inventor
David Kazuo Okura
John Albert Gauthier
Trevor Robert Hill
Simon Andrew Mackenzie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2017394A1 publication Critical patent/CA2017394A1/fr
Application granted granted Critical
Publication of CA2017394C publication Critical patent/CA2017394C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
CA002017394A 1989-11-22 1990-05-23 Methode et dispositif d'alignement de donnees Expired - Fee Related CA2017394C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US440,157 1989-11-22
US07/440,157 US4965884A (en) 1989-11-22 1989-11-22 Data alignment method and apparatus

Publications (2)

Publication Number Publication Date
CA2017394A1 true CA2017394A1 (fr) 1991-05-22
CA2017394C CA2017394C (fr) 1996-04-09

Family

ID=23747681

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002017394A Expired - Fee Related CA2017394C (fr) 1989-11-22 1990-05-23 Methode et dispositif d'alignement de donnees

Country Status (2)

Country Link
US (1) US4965884A (fr)
CA (1) CA2017394C (fr)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0416330B1 (fr) * 1989-09-06 1995-02-08 Omron Corporation Dispositif de commande programmable
JP2600509B2 (ja) * 1990-09-05 1997-04-16 富士通株式会社 ディジタル無線伝送方式
JP2744690B2 (ja) * 1990-10-15 1998-04-28 三菱電機株式会社 フレーム同期回路
JPH0778774B2 (ja) * 1991-02-22 1995-08-23 インターナショナル・ビジネス・マシーンズ・コーポレイション 短待ち時間データ回復装置及びメッセージデータの同期化方法
US5491729A (en) * 1992-07-06 1996-02-13 3Com Corporation Digital phase-locked data recovery circuit
US5537418A (en) * 1993-03-11 1996-07-16 Unisys Corporation Data transmit resynchronization at a node
JPH07154381A (ja) * 1993-11-30 1995-06-16 Hitachi Ltd データ転送装置
US5513377A (en) * 1994-06-17 1996-04-30 International Business Machines Corporation Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus
EP0687986A3 (fr) * 1994-06-17 1996-02-14 Ibm Méthode et appareil pour la transmission de données digitales dans des systèmes massivement parallèles
US5522088A (en) * 1994-06-17 1996-05-28 International Business Machines Corporation Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus
JPH08111675A (ja) * 1994-10-07 1996-04-30 Mitsubishi Denki Eng Kk 同期回路
US5948116A (en) * 1996-02-23 1999-09-07 Texas Instruments Deutschland, Gmbh Bit error correction algorithm
US5862131A (en) * 1996-10-10 1999-01-19 Lucent Technologies Inc. Hybrid time-slot and sub-time-slot operation in a time-division multiplexed system
US5910742A (en) * 1997-06-16 1999-06-08 Cypress Semiconductor Corp. Circuit and method for data recovery
JPH1174878A (ja) * 1997-08-28 1999-03-16 Mitsubishi Electric Corp デジタルデータ伝送システム
US7346063B1 (en) * 1998-07-08 2008-03-18 Broadcom Corporation Memory management unit for a network switch
JP2000174736A (ja) * 1998-12-08 2000-06-23 Sharp Corp ビット同期回路
US6654897B1 (en) * 1999-03-05 2003-11-25 International Business Machines Corporation Dynamic wave-pipelined interface apparatus and methods therefor
US6629250B2 (en) * 1999-04-23 2003-09-30 Cray Inc. Adjustable data delay using programmable clock shift
US6401213B1 (en) * 1999-07-09 2002-06-04 Micron Technology, Inc. Timing circuit for high speed memory
JP2001168848A (ja) * 1999-12-07 2001-06-22 Mitsubishi Electric Corp デジタル同期回路
US6865241B1 (en) 1999-12-15 2005-03-08 Lexmark International, Inc. Method and apparatus for sampling digital data at a virtually constant rate, and transferring that data into a non-constant sampling rate device
US6553505B1 (en) * 2000-02-29 2003-04-22 Maxtor Corporation Method and apparatus for performing clock timing de-skew
WO2002030036A1 (fr) * 2000-10-06 2002-04-11 Flextronics Semiconductor Design, Inc. Interface coherente extensible haute vitesse
US7050512B1 (en) * 2001-01-08 2006-05-23 Pixelworks, Inc. Receiver architecture
GB2375274A (en) * 2001-03-27 2002-11-06 Acuid Corp Ltd Receiver with automatic skew compensation
US20020184412A1 (en) * 2001-06-02 2002-12-05 Stevens James Ray System and method for locating and aligning to framing bits
US7613237B1 (en) * 2005-01-13 2009-11-03 Advanced Micro Devices, Inc. Built-in test feature to facilitate system level stress testing of a high-speed serial link that uses a forwarding clock
CN101529790B (zh) * 2006-09-21 2015-05-20 美国亚德诺半导体公司 串行数字数据通信接口

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4672639A (en) * 1984-05-24 1987-06-09 Kabushiki Kaisha Toshiba Sampling clock pulse generator
GB8511585D0 (en) * 1985-05-08 1985-06-12 Hewlett Packard Ltd Jitter measurement method
US4756011A (en) * 1986-12-24 1988-07-05 Bell Communications Research, Inc. Digital phase aligner
US4805198A (en) * 1987-05-19 1989-02-14 Crystal Semiconductor Corporation Clock multiplier/jitter attenuator
US4791652A (en) * 1987-06-04 1988-12-13 Northern Telecom Limited Synchronization of asynchronous data signals

Also Published As

Publication number Publication date
US4965884A (en) 1990-10-23
CA2017394C (fr) 1996-04-09

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