CA2020607A1 - Circuit de conversion serie-parallele mot par mot - Google Patents
Circuit de conversion serie-parallele mot par motInfo
- Publication number
- CA2020607A1 CA2020607A1 CA 2020607 CA2020607A CA2020607A1 CA 2020607 A1 CA2020607 A1 CA 2020607A1 CA 2020607 CA2020607 CA 2020607 CA 2020607 A CA2020607 A CA 2020607A CA 2020607 A1 CA2020607 A1 CA 2020607A1
- Authority
- CA
- Canada
- Prior art keywords
- bit
- serial
- word
- parallel
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000006243 chemical reaction Methods 0.000 title description 2
- 238000005516 engineering process Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
- H04J3/0608—Detectors therefor, e.g. correlators, state machines
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19893922482 DE3922482A1 (de) | 1989-07-08 | 1989-07-08 | Schaltungsanordnung zur wortweisen seriell-parallel-wandlung |
| DEP3922482.1 | 1989-07-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2020607A1 true CA2020607A1 (fr) | 1991-01-09 |
Family
ID=6384553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2020607 Abandoned CA2020607A1 (fr) | 1989-07-08 | 1990-07-06 | Circuit de conversion serie-parallele mot par mot |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH03139020A (fr) |
| CA (1) | CA2020607A1 (fr) |
| DE (1) | DE3922482A1 (fr) |
| HU (1) | HUT57963A (fr) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE518865C2 (sv) | 1998-12-22 | 2002-12-03 | Switchcore Ab | Anordning och metod för omvandling av data i seriellt format till parallellt format och vice versa |
-
1989
- 1989-07-08 DE DE19893922482 patent/DE3922482A1/de not_active Withdrawn
-
1990
- 1990-07-05 HU HU409690A patent/HUT57963A/hu unknown
- 1990-07-06 JP JP17761990A patent/JPH03139020A/ja active Pending
- 1990-07-06 CA CA 2020607 patent/CA2020607A1/fr not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03139020A (ja) | 1991-06-13 |
| DE3922482A1 (de) | 1991-01-17 |
| HU904096D0 (en) | 1990-12-28 |
| HUT57963A (en) | 1991-12-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2747077B2 (ja) | フレーム同期回路 | |
| US4920535A (en) | Demultiplexer system | |
| GB1300029A (en) | Information buffer unit | |
| CA2068867A1 (fr) | Circuits de regeneration de signaux d'horloge degrades par effet de gigue | |
| EP0351779A3 (fr) | Circuit de mise en phase d'une horloge | |
| US4899339A (en) | Digital multiplexer | |
| US3575557A (en) | Time division multiplex system | |
| US4949339A (en) | Multiplexer apparatus adaptable for two kinds of transmission rates | |
| US4566099A (en) | Synchronous clock generator for digital signal multiplex devices | |
| US4348762A (en) | Circuit for correcting data reading clock pulses | |
| US4646328A (en) | Frame alignment loss and recovery device for a digital signal | |
| US4573172A (en) | Programmable circuit for series-parallel transformation of a digital signal | |
| US4034352A (en) | Phase control of clock and sync pulser | |
| US4058682A (en) | Expandable memory for PCM signal transmission | |
| US3678200A (en) | Frame synchronization system | |
| CA2020607A1 (fr) | Circuit de conversion serie-parallele mot par mot | |
| EP0548649B1 (fr) | Générateur de code DS3 AIS/Repos parallèle | |
| US5228065A (en) | Arrangement for producing a synchronizing pulse | |
| US4101739A (en) | Demultiplexer for originally synchronous digital signals internested word-wise | |
| US4045618A (en) | Device for synchronizing a binary data train in relation to a reference train | |
| EP0409168B1 (fr) | Circuit de mémoire élastique | |
| US5111462A (en) | Decoders for hamming encoded data | |
| US4063040A (en) | High speed multiplexer and demultiplexer for pulse code channels | |
| EP0012135A1 (fr) | Méthode et commutateur pour la commutation en série et bit par bit de données en forme de mots | |
| SU836805A1 (ru) | Устройство дл устранени "обратной работы |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Dead |