CA2025096A1 - Methode d'utilisation de circuits logiques prediffuses reconfigurables electroniquement et appareil comportant ces circuits - Google Patents

Methode d'utilisation de circuits logiques prediffuses reconfigurables electroniquement et appareil comportant ces circuits

Info

Publication number
CA2025096A1
CA2025096A1 CA2025096A CA2025096A CA2025096A1 CA 2025096 A1 CA2025096 A1 CA 2025096A1 CA 2025096 A CA2025096 A CA 2025096A CA 2025096 A CA2025096 A CA 2025096A CA 2025096 A1 CA2025096 A1 CA 2025096A1
Authority
CA
Canada
Prior art keywords
chips
reconfigurable
ercga
interconnect
interconnected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2025096A
Other languages
English (en)
Other versions
CA2025096C (fr
Inventor
Michael R. Butts
Jon A. Batcheller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quickturn Design Systems Inc
Original Assignee
Mentor Graphics Corp
Quickturn Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/417,196 external-priority patent/US5036473A/en
Application filed by Mentor Graphics Corp, Quickturn Design Systems Inc filed Critical Mentor Graphics Corp
Publication of CA2025096A1 publication Critical patent/CA2025096A1/fr
Application granted granted Critical
Publication of CA2025096C publication Critical patent/CA2025096C/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CA002025096A 1989-10-04 1990-09-11 Methode d'utilisation de circuits logiques prediffuses reconfigurables electroniquement et appareil comportant ces circuits Expired - Lifetime CA2025096C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/417,196 1989-10-04
US07/417,196 US5036473A (en) 1988-10-05 1989-10-04 Method of using electronically reconfigurable logic circuits

Publications (2)

Publication Number Publication Date
CA2025096A1 true CA2025096A1 (fr) 1991-04-05
CA2025096C CA2025096C (fr) 1999-01-19

Family

ID=23652972

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002025096A Expired - Lifetime CA2025096C (fr) 1989-10-04 1990-09-11 Methode d'utilisation de circuits logiques prediffuses reconfigurables electroniquement et appareil comportant ces circuits

Country Status (1)

Country Link
CA (1) CA2025096C (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111199128A (zh) * 2018-10-31 2020-05-26 财团法人工业技术研究院 仿真系统与方法
CN116822596A (zh) * 2023-05-31 2023-09-29 清华大学 计算装置及其操作方法、可重构数据通路的制备方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111199128A (zh) * 2018-10-31 2020-05-26 财团法人工业技术研究院 仿真系统与方法
CN111199128B (zh) * 2018-10-31 2023-10-13 财团法人工业技术研究院 仿真系统与方法
CN116822596A (zh) * 2023-05-31 2023-09-29 清华大学 计算装置及其操作方法、可重构数据通路的制备方法

Also Published As

Publication number Publication date
CA2025096C (fr) 1999-01-19

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