CA2026236A1 - Methode et dispositif pour antememoire a fenetre de lecture - Google Patents

Methode et dispositif pour antememoire a fenetre de lecture

Info

Publication number
CA2026236A1
CA2026236A1 CA2026236A CA2026236A CA2026236A1 CA 2026236 A1 CA2026236 A1 CA 2026236A1 CA 2026236 A CA2026236 A CA 2026236A CA 2026236 A CA2026236 A CA 2026236A CA 2026236 A1 CA2026236 A1 CA 2026236A1
Authority
CA
Canada
Prior art keywords
registers
addressable
lines
logically
addressed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2026236A
Other languages
English (en)
Other versions
CA2026236C (fr
Inventor
Eric Hartwig Jensen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of CA2026236A1 publication Critical patent/CA2026236A1/fr
Application granted granted Critical
Publication of CA2026236C publication Critical patent/CA2026236C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G06F9/30127—Register windows
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CA002026236A 1989-11-16 1990-09-26 Methode et dispositif pour antememoire a fenetre de lecture Expired - Fee Related CA2026236C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US437,978 1989-11-16
US07/437,978 US5179681A (en) 1989-11-16 1989-11-16 Method and apparatus for current window cache with switchable address and out cache registers

Publications (2)

Publication Number Publication Date
CA2026236A1 true CA2026236A1 (fr) 1991-05-17
CA2026236C CA2026236C (fr) 1993-10-12

Family

ID=23738728

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002026236A Expired - Fee Related CA2026236C (fr) 1989-11-16 1990-09-26 Methode et dispositif pour antememoire a fenetre de lecture

Country Status (4)

Country Link
US (1) US5179681A (fr)
CA (1) CA2026236C (fr)
GB (1) GB2238145B (fr)
HK (1) HK76294A (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293631A (en) * 1991-08-06 1994-03-08 Hewlett-Packard Company Analysis and optimization of array variables in compiler for instruction level parallel processor
JP2823767B2 (ja) * 1992-02-03 1998-11-11 松下電器産業株式会社 レジスタファイル
US5666556A (en) * 1993-12-30 1997-09-09 Intel Corporation Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit
JP3676411B2 (ja) * 1994-01-21 2005-07-27 サン・マイクロシステムズ・インコーポレイテッド レジスタファイル装置及びレジスタファイルアクセス方法
US6157981A (en) * 1998-05-27 2000-12-05 International Business Machines Corporation Real time invariant behavior cache
US7117342B2 (en) * 1998-12-03 2006-10-03 Sun Microsystems, Inc. Implicitly derived register specifiers in a processor
US7114056B2 (en) * 1998-12-03 2006-09-26 Sun Microsystems, Inc. Local and global register partitioning in a VLIW processor
US7013377B2 (en) * 2003-09-03 2006-03-14 Sun Microsystems, Inc. Method and apparatus for alleviating register window size constraints
US7284092B2 (en) * 2004-06-24 2007-10-16 International Business Machines Corporation Digital data processing apparatus having multi-level register file

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0644245B2 (ja) * 1983-12-29 1994-06-08 富士通株式会社 ストアバッファ装置
US4734852A (en) * 1985-08-30 1988-03-29 Advanced Micro Devices, Inc. Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor
JP2545789B2 (ja) * 1986-04-14 1996-10-23 株式会社日立製作所 情報処理装置
US4811208A (en) * 1986-05-16 1989-03-07 Intel Corporation Stack frame cache on a microprocessor chip
US4891753A (en) * 1986-11-26 1990-01-02 Intel Corporation Register scorboarding on a microprocessor chip
US4947366A (en) * 1987-10-02 1990-08-07 Advanced Micro Devices, Inc. Input/output controller incorporating address mapped input/output windows and read ahead/write behind capabilities
US5083263A (en) * 1988-07-28 1992-01-21 Sun Microsystems, Inc. BISC with interconnected register ring and selectively operating portion of the ring as a conventional computer

Also Published As

Publication number Publication date
GB2238145A (en) 1991-05-22
HK76294A (en) 1994-08-12
GB9013928D0 (en) 1990-08-15
GB2238145B (en) 1993-12-08
CA2026236C (fr) 1993-10-12
US5179681A (en) 1993-01-12

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