CA2036372C - Antememoire de l'entree-sortie pour l'antememorisation de donnees a acces de memoire (virtuelle) directe - Google Patents
Antememoire de l'entree-sortie pour l'antememorisation de donnees a acces de memoire (virtuelle) directe Download PDFInfo
- Publication number
- CA2036372C CA2036372C CA 2036372 CA2036372A CA2036372C CA 2036372 C CA2036372 C CA 2036372C CA 2036372 CA2036372 CA 2036372 CA 2036372 A CA2036372 A CA 2036372A CA 2036372 C CA2036372 C CA 2036372C
- Authority
- CA
- Canada
- Prior art keywords
- cache
- data
- dvma
- address
- devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000012546 transfer Methods 0.000 claims abstract description 20
- 230000006870 function Effects 0.000 claims description 11
- 238000012545 processing Methods 0.000 claims description 5
- 238000013519 translation Methods 0.000 claims description 5
- 230000003139 buffering effect Effects 0.000 abstract description 3
- 239000000872 buffer Substances 0.000 description 106
- 238000012360 testing method Methods 0.000 description 32
- 238000013507 mapping Methods 0.000 description 24
- 238000010586 diagram Methods 0.000 description 16
- 238000003491 array Methods 0.000 description 14
- 230000007246 mechanism Effects 0.000 description 13
- 230000004224 protection Effects 0.000 description 9
- 238000013461 design Methods 0.000 description 6
- 230000004044 response Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000006855 networking Effects 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 208000033748 Device issues Diseases 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 238000002405 diagnostic procedure Methods 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US50897990A | 1990-04-12 | 1990-04-12 | |
| US508,979 | 1990-04-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2036372A1 CA2036372A1 (fr) | 1991-10-13 |
| CA2036372C true CA2036372C (fr) | 2002-10-01 |
Family
ID=24024845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2036372 Expired - Fee Related CA2036372C (fr) | 1990-04-12 | 1991-02-08 | Antememoire de l'entree-sortie pour l'antememorisation de donnees a acces de memoire (virtuelle) directe |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2036372C (fr) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN120891990B (zh) * | 2025-09-30 | 2026-01-27 | 济南浪潮数据技术有限公司 | Io流限速控制方法及装置、电子设备和存储介质 |
-
1991
- 1991-02-08 CA CA 2036372 patent/CA2036372C/fr not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2036372A1 (fr) | 1991-10-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5263142A (en) | Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices | |
| US5247648A (en) | Maintaining data coherency between a central cache, an I/O cache and a memory | |
| US5604865A (en) | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU | |
| US5897656A (en) | System and method for maintaining memory coherency in a computer system having multiple system buses | |
| US6049847A (en) | System and method for maintaining memory coherency in a computer system having multiple system buses | |
| US5561779A (en) | Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system | |
| US5696937A (en) | Cache controller utilizing a state machine for controlling invalidations in a network with dual system busses | |
| US5659709A (en) | Write-back and snoop write-back buffer to prevent deadlock and to enhance performance in an in-order protocol multiprocessing bus | |
| EP0301354A2 (fr) | Protocole de cohérence d'antémémoire pour système multiprocesseur | |
| US6178481B1 (en) | Microprocessor circuits and systems with life spanned storage circuit for storing non-cacheable data | |
| US20020174305A1 (en) | Method and apparatus for controlling memory storage locks based on cache line ownership | |
| US20020199079A1 (en) | Method to prefetch data from system memory using a bus interface unit | |
| US5161162A (en) | Method and apparatus for system bus testability through loopback | |
| US5829027A (en) | Removable processor board having first, second and third level cache system for use in a multiprocessor computer system | |
| US6892283B2 (en) | High speed memory cloner with extended cache coherency protocols and responses | |
| US20040111576A1 (en) | High speed memory cloning facility via a source/destination switching mechanism | |
| US20040111575A1 (en) | Dynamic data routing mechanism for a high speed memory cloner | |
| JPH06318174A (ja) | キャッシュ・メモリ・システム及び主メモリに記憶されているデータのサブセットをキャッシュする方法 | |
| KR100322223B1 (ko) | 대기행렬및스누프테이블을갖는메모리제어기 | |
| EP0681241A1 (fr) | Carte processeur à système d'antémémoire de second niveau à postmémorisation et système d'antémémoire de troisième niveau à écriture en travers qui emmagasine des informations de cohérence de multiprocesseur | |
| US6898677B2 (en) | Dynamic software accessibility to a microprocessor system with a high speed memory cloner | |
| US7502917B2 (en) | High speed memory cloning facility via a lockless multiprocessor mechanism | |
| CA2036372C (fr) | Antememoire de l'entree-sortie pour l'antememorisation de donnees a acces de memoire (virtuelle) directe | |
| US20040111581A1 (en) | Imprecise cache line protection mechanism during a memory clone operation | |
| US5696938A (en) | Computer system permitting mulitple write buffer read-arounds and method therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |