CA2051606A1 - Tableau de connexions multicouches - Google Patents

Tableau de connexions multicouches

Info

Publication number
CA2051606A1
CA2051606A1 CA2051606A CA2051606A CA2051606A1 CA 2051606 A1 CA2051606 A1 CA 2051606A1 CA 2051606 A CA2051606 A CA 2051606A CA 2051606 A CA2051606 A CA 2051606A CA 2051606 A1 CA2051606 A1 CA 2051606A1
Authority
CA
Canada
Prior art keywords
glass
spheres
glass ceramic
wiring board
layer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2051606A
Other languages
English (en)
Other versions
CA2051606C (fr
Inventor
Kishio Yokouchi
Hiroshi Kamezaki
Masato Wakamura
Nobuo Kamehara
Koichi Niwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2051606A1 publication Critical patent/CA2051606A1/fr
Application granted granted Critical
Publication of CA2051606C publication Critical patent/CA2051606C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/25—Web or sheet containing structurally defined element or component and including a second component containing structurally defined particles
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/29—Coated or structually defined flake, particle, cell, strand, strand portion, rod, filament, macroscopic fiber or mass thereof
    • Y10T428/2982—Particulate matter [e.g., sphere, flake, etc.]
    • Y10T428/2991—Coated
    • Y10T428/2993—Silicic or refractory material containing [e.g., tungsten oxide, glass, cement, etc.]
    • Y10T428/2996—Glass particles or spheres

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Compositions Of Oxide Ceramics (AREA)
  • Porous Artificial Stone Or Porous Ceramic Products (AREA)
  • Laminated Bodies (AREA)
CA002051606A 1990-09-20 1991-09-17 Tableau de connexions multicouches Expired - Fee Related CA2051606C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2252500A JP2906282B2 (ja) 1990-09-20 1990-09-20 ガラスセラミック・グリーンシートと多層基板、及び、その製造方法
JP2-252500 1990-09-20

Publications (2)

Publication Number Publication Date
CA2051606A1 true CA2051606A1 (fr) 1992-03-21
CA2051606C CA2051606C (fr) 1996-08-27

Family

ID=17238239

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002051606A Expired - Fee Related CA2051606C (fr) 1990-09-20 1991-09-17 Tableau de connexions multicouches

Country Status (6)

Country Link
US (2) US5275889A (fr)
EP (1) EP0477004B1 (fr)
JP (1) JP2906282B2 (fr)
KR (1) KR950002963B1 (fr)
CA (1) CA2051606C (fr)
DE (1) DE69103999T2 (fr)

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JPH0645759A (ja) * 1992-07-22 1994-02-18 Fujitsu Ltd 多層セラミック回路基板の製造方法
JP2756075B2 (ja) * 1993-08-06 1998-05-25 三菱電機株式会社 金属ベース基板およびそれを用いた電子機器
US5470802A (en) * 1994-05-20 1995-11-28 Texas Instruments Incorporated Method of making a semiconductor device using a low dielectric constant material
US6147870A (en) * 1996-01-05 2000-11-14 Honeywell International Inc. Printed circuit assembly having locally enhanced wiring density
US5839188A (en) 1996-01-05 1998-11-24 Alliedsignal Inc. Method of manufacturing a printed circuit assembly
US6214746B1 (en) * 1999-05-07 2001-04-10 Honeywell International Inc. Nanoporous material fabricated using a dissolvable reagent
US6171687B1 (en) 1999-10-18 2001-01-09 Honeywell International Inc. Infiltrated nanoporous materials and methods of producing same
JP3414342B2 (ja) * 1999-11-25 2003-06-09 日本電気株式会社 集積回路チップの実装構造および実装方法
US6627669B2 (en) 2000-06-06 2003-09-30 Honeywell International Inc. Low dielectric materials and methods of producing same
US6444715B1 (en) 2000-06-06 2002-09-03 Honeywell International Inc. Low dielectric materials and methods of producing same
US20040176488A1 (en) * 2000-06-06 2004-09-09 Shyama Mukherjee Low dielectric materials and methods of producing same
US7056468B2 (en) * 2000-06-15 2006-06-06 Paratek Microwave, Inc. Method for producing low-loss tunable ceramic composites with improved breakdown strengths
WO2001099224A1 (fr) 2000-06-16 2001-12-27 Paratek Microwave, Inc. Couche épaisse composite diélectrique accordable électroniquement
US6423811B1 (en) 2000-07-19 2002-07-23 Honeywell International Inc. Low dielectric constant materials with polymeric networks
JP3785903B2 (ja) * 2000-07-21 2006-06-14 株式会社村田製作所 多層基板及びその製造方法
DE10042653A1 (de) * 2000-08-31 2002-03-28 Bosch Gmbh Robert Keramische Mehrlagenschaltung
US20040102584A1 (en) * 2001-12-03 2004-05-27 Lau Kreisler S. Low dielectric constant materials with polymeric networks
JP3847628B2 (ja) * 2002-01-09 2006-11-22 株式会社ワコム 低電圧駆動回路及び方法
JP4426805B2 (ja) * 2002-11-11 2010-03-03 日本特殊陶業株式会社 配線基板およびその製造方法
JP4554330B2 (ja) * 2004-10-21 2010-09-29 株式会社リコー 高耐久性を有する断熱スタンパ構造
US7432133B2 (en) * 2005-10-24 2008-10-07 Freescale Semiconductor, Inc. Plastic packaged device with die interface layer
US7435625B2 (en) * 2005-10-24 2008-10-14 Freescale Semiconductor, Inc. Semiconductor device with reduced package cross-talk and loss
US20070090545A1 (en) * 2005-10-24 2007-04-26 Condie Brian W Semiconductor device with improved encapsulation
US20090026924A1 (en) * 2007-07-23 2009-01-29 Leung Roger Y Methods of making low-refractive index and/or low-k organosilicate coatings
US7988412B2 (en) * 2007-08-24 2011-08-02 General Electric Company Structures for damping of turbine components
JP5105378B2 (ja) * 2007-12-26 2012-12-26 パナソニック株式会社 半導体装置および多層配線基板
US8076587B2 (en) * 2008-09-26 2011-12-13 Siemens Energy, Inc. Printed circuit board for harsh environments
JPWO2012011232A1 (ja) * 2010-07-22 2013-09-09 パナソニック株式会社 プラズマディスプレイパネル用ガラスペーストおよびプラズマディスプレイパネル
DE102012004708A1 (de) * 2012-03-07 2013-09-12 Manfred Jaeckel Verfahren zur Herstellung eines offenporigen keramischen Formkörpers
EP2669667B1 (fr) * 2012-03-30 2017-06-28 NGK Insulators, Ltd. Procédé d'analyse de microstructure, programme associé, et dispositif d'analyse de microstructure
US9258892B2 (en) * 2013-07-23 2016-02-09 Rogers Corporation Circuit materials, circuits laminates, and method of manufacture thereof
DE102016119031B4 (de) * 2016-10-07 2025-08-14 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Wärmeisoliertes Mikrosystem
CN114080375B (zh) * 2019-07-05 2023-06-06 日本电气硝子株式会社 陶瓷三维造型用膏体及立体造型物的制造方法
EP4405308A4 (fr) * 2021-09-20 2025-07-30 3M Innovative Properties Company Bulles de verre revêtues, composites obtenus à partir de celles-ci, et leurs procédés de fabrication
KR102716712B1 (ko) 2021-12-27 2024-10-11 한국세라믹기술원 초고주파 소자용 복합체 세라믹스 조성물과 그에 의한 세라믹 기판 및 이의 제조방법
CN118696409A (zh) * 2022-02-16 2024-09-24 Ａｇｃ株式会社 二氧化硅玻璃基板
US20230317592A1 (en) * 2022-04-01 2023-10-05 Intel Corporation Substrate with low-permittivity core and buildup layers
KR102840267B1 (ko) 2023-07-28 2025-07-29 한국세라믹기술원 고주파 소자용 유전체 세라믹스 조성물 및 이의 마이크로파 유전특성의 제어방법, 그리고 그에 의한 세라믹 기판 및 이의 제조방법
KR102700847B1 (ko) 2023-10-23 2024-08-29 한국세라믹기술원 High-Q 적층 세라믹 커패시터의 제조방법

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Also Published As

Publication number Publication date
KR950002963B1 (ko) 1995-03-28
US5593526A (en) 1997-01-14
KR920007158A (ko) 1992-04-28
EP0477004A3 (en) 1993-02-24
US5275889A (en) 1994-01-04
CA2051606C (fr) 1996-08-27
EP0477004B1 (fr) 1994-09-14
JP2906282B2 (ja) 1999-06-14
JPH04130072A (ja) 1992-05-01
DE69103999T2 (de) 1995-01-19
DE69103999D1 (de) 1994-10-20
EP0477004A2 (fr) 1992-03-25

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Effective date: 20080917