CA2139191A1 - Transmit reference oscillator of a vsat for satellite communications - Google Patents
Transmit reference oscillator of a vsat for satellite communicationsInfo
- Publication number
- CA2139191A1 CA2139191A1 CA002139191A CA2139191A CA2139191A1 CA 2139191 A1 CA2139191 A1 CA 2139191A1 CA 002139191 A CA002139191 A CA 002139191A CA 2139191 A CA2139191 A CA 2139191A CA 2139191 A1 CA2139191 A1 CA 2139191A1
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- controlled oscillator
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- 238000004891 communication Methods 0.000 title abstract description 10
- 230000010355 oscillation Effects 0.000 claims abstract description 8
- 238000001914 filtration Methods 0.000 claims abstract description 4
- 230000009977 dual effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 3
- 241000283986 Lepus Species 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/19—Earth-synchronous stations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
- H03D7/161—Multiple-frequency-changing all the frequency changers being connected in cascade
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Astronomy & Astrophysics (AREA)
- Aviation & Aerospace Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transmitters (AREA)
- Radio Relay Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present invention relates to a transmit reference oscillator for a remote station of a VSAT for satellite communications. comprises a by-fifteen divider for dividing input reference signals by 15: a Voltage Controlled Oscillator (VCO) for outputting oscillation signals; a by-four divider for dividing the oscillating signals outputted from said voltage controlled oscillator: a by-N divider for dividing by N the signals divided by said by-N divider; a phase detector for outputting phase difference signals, which are the signals of the phase differences obtained by comparing the output signals of said by-N divider and those of said by-fifteen divider; and a low pass filter for varying the oscillation signals of said voltage controlled oscillator by filtering the difference signals outputted from said phase detector and applying the filtered difference signals to said voltage controlled oscillator. Accordingly, the present invention not only can transmit data over the whole band of 500 MHz which is a bandwidth for satellite communication transponders, without modifying a remote station or a Radio Frequency (RF) part of a VSAT, but also is proof against phase noises and spurious, and can be simply implemented to reduce its size and lower its price.
Description
213~191 A TRANSMIT REFERENCE OSCILLATOR OF A VSAT FOR SATELLITE
COMMUNICATIONS
BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a Transmit Reference Oscillator (TRO) of a VSAT (Very Small Aperture Terminal) for satellite communications, especially to a transmit reference oscillator for generating a reference frequency by using a frequency synthesizer so that data can be transmitted over the whole band of 500 MHz which is a bandwidth for satellite communication transponders.
Description of the Prior Art Generally speaking, a conventional remote station of a VSAT has a problem that because it is fixed to use only a specific band out of a bandwid-th of 500 MHz which is that for satellite communication transponders,said remote station or a Radio Frequency (RF) part of a VSAT has to be inevitably ~1391gl modified to change the band to be used.
Summary of the Invention To provide a transmit reference oscillator for generating a reference frequency by using a frequency synthesizer so that data can be transmitted over the whole band of 500 MHz which is a bandwidth for satellite communication transponders, without modifying a remote station or a Radio Frequency (RF) part of a VSAT, the present invention comprises a by-fifteen divider for dividing input reference signals by 15; a Voltage Controlled Oscillator (VCO) for outputting oscillation signals; a by-four divider for dividing the oscillating signals outputted from said voltage controlled oscillator. a by-N divider for dividing by N the signals divided by said by-four divider; a phase detector for outputting phase difference signals, which are the signals of the phase differences obtained by comparing the output signals of said by-N divider and those of said by-fifteen divider; and a low pass filter for varying the oscillation signals of said voltage controlled oscillator by filtering the difference signals outputted from said p~hase detector and applying the filtered difference signals to said voltage controlled oscillator.
~139191 BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Fig. 1 is a diagram showing a process for converting the transmit frequencies of a remote station of a VSAT according to the present invention;
Fig. 2 is a block diagram for showing a configuration of a transmit reference oscillator according to the present invention;
Fig. 3 is a detailed circuit diagram of an embodiment of a transmit reference oscillator according to the present invention; and Fig. 4 is a detailed circuit diagram of the other embodiment of a transmit reference oscillator TRO according to the present invention.
Detailed description of the pre-ferred embodiments Fig. 1 shows a process for converting the transmit frequencies of a remote station of a VSAT according to the present invention. A Binary Phase Shift Keying (BPSK) modulator 11 modulates digital data (base band data), which are inputted to be transmitted, into an Intermediate Frequency (IF) between 1456 - 1584 MHz, where the modulatable bandwidth is 128 MHz. by using double frequency converters. A Transmit Block Unit (TBU) 12 converts the signals modulated by said BPSK
modulator 11 up to a frequency level of 14 GHz through a Frequency Division Multiplexing (FDM) technique by using the four reference frequencies inputted from a Transmit Reference Oscillator (TRO) 13.
TRO 13 generates a reference frequency for converting the signal modulated by said BPSK modulator 11 up to a frequency of 14.0 - 14.5 GHz so that data can be transmitted over the range of 500 MHz which is the bandwidth for communication satellites. The reference frequencies outputted from said TRO 13 are 130 2/3 MHz for converting the modulated signal having 1456 - 1584 MHz into a signal having 14.000 -14.128 GHz. 132.0 MHz for converting the modulated signal having 1456 - 1584 MHz into a signal having 14.128 - 14.256 GHz. 133 1/3 MHz for converting the modulated signal having 1456 - 1584 MHz into a signal having 14.256 - 14.384 GHz and 133 1/3 MHz for converting the modulated signal having 1456 -1584 MHz into a signal having 14.384 - 14.500 GHz.
The IF signals modulated at a remote station of a VSAT
as mentioned above are converted up to a Ku band of 14 GHz and amplified by a Solid State Power Amplifier (SSPA) to access communication satellites by the values calculated in a link budget. In the meantime. said frequency up-converter and SSPA
are incorporated into a TBU 12, since a remote station of a VSAT should characteristically be small and simple in it size.
Fig. 2 shows a configuration of a transmit reference oscillator according to the present invention. A signal having a frequency level of 130 MHz is set as a transmit reference frequency to minimize the influence of inter-modulation during the conversion of the frequency as mentioned in TBU 12. The dividing factors of a frequency synthesizer are set respectively to 15 and 4 in consideration of phase noises, a spurious, and its simple implementation. The values of N for a by-N divider are set to 98, 9'3, 100, and 101 respectively to obtain Transmit Reference Signals 130 2/3 MHz, 132 MHz, 133 1/3 MHz and 134 2/3 MHz. In the mean time, a reference input frequency of TRO uses a reference signal of 5 MHz locked by a reference frequency of a hub station, while an output frequency of TRO is locked the hub station and finally the RF signals of a remote station are locked by the hub station.
In other words, the transmit reference oscillator has a configuration of a by-fifteen divider 22 for dividing input reference signals by 15, a Voltage Controlled Oscillator (VCO) 25 for outputting oscillation signals, a by-four divider 26 for dividing the oscillating signals outputted from said voltage controlled oscillator 25, a by-N divider 27 for dividing by N
the signals divided by said by-four divider 26. a phase detector 23 for outputting phase difference signals. which are the signals of the phase differences obtained by comparing the output signals of said by-N divider 27 and those of said by-fifteen 22 divider, a low pass filter 24 for varying the oscillation signals of said voltage controlled oscillator 25 by filtering the difference signals outputted from said phase detector 23 and applying the filtered difference signals to said voltage controlled oscillator 25, and a TR0 alarm device for generating alarms when phase differences outputted from said 15 divider 27 and N divider are detected from said TR0 ALM
28.
The operation of the present invention having a configuration mentioned above will be described in the following;
A reference signal 21 of 5 MHz locked by a hub station is divided into 333 1/3 KHz by a by-fifteen divider 22. The signal oscillated by VC0 25 is divided into 32 2/3 MHz. 33.0 MHz, 33 1/3 MHz and 33 2/3 MHz respectively by a by-four divider 26. The signal divided by said by-four divider 26 are again divided into 98. 99, 100 and 101 respectively by a by-N
divider 27 to become a signal of 333 1/3 KHz. The dividing ratio of the by-N divider can be controlled by the data of a Central Processor (CP) or a switch.
The phases of the 333 1/3 KHz divided respectively by a 213~
by-fifteen divider and a by-N divider as mentioned above are compared and the component having the phase difference is detected by a phase detector 23. The signal of the phase difference detected is converted into a direct current control voltage through a low pass filter 24. Accordingly said VCO 25 oscillates a frequency corresponding to the direct current control voltage inputted, and the oscillated frequency becomes a stabilized frequency by forming a loop after being locked by a reference signal of S MHz, and is converted to a desired frequency by the dividing ratio of a by-N divider. A TRO
alarm device 2~ detects whether the output of TRO (a transmit reference frequency) is locked by the reference signal of S MHz and generates alarms. Such alarms are reported to the CP of a VSAT remote station and used for a network management system(NMS).
Fig. 3 is a detailed circuit diagram of an embodiment of a transmit reference oscillator according to the present invention. A reference frequency of S MHz is divided by 15 according to CP data of a VSAT remote station by using a phase locked loop (PLL) frequency synthesizer U1.
The oscillating output signal of VCO 25 are divided by 4 at a by-4 divider 26 and then divided by N at a by-N divider 27. At a by-N divider 27 according to CP data of a VSAT remote station by using a phase locked loop(PLL) frequency synthesizer U1 and a dual modulus prescaler U2. And one desired frequency 2 139 1 g 1 74092-3 selected out of the frequencies divided by N. At a by-15 divider 22 and a by-N divider 27, the CP data of VSAT remote station consist of 3-bit address, 4-bit data and 1-bit strobe signal. and CP of VSAT remote station transmits, continuously eight times the address, the data and the stro~e to store data values in the registers R,N, and A inside the PLL frequency synthesizer U1.
A TRO output frequency is set according to the data values of CP. Here, the value of a register R is always 15. A
transmit frequency of 130 2/3 MHz is outputted when the value of a register N is 9 and that of a register A is ~. A
transmit frequency of 132 MHz is outputted when the value of a register N is 9 and that of a register A is 9. A transmit frequency of 133 1/3 MHz is outputted when the value of a register N is 10 and that of a register A is 0. A transmit frequency of 134 2/3 MHz is outputted when the value of a register N is 10 and that of a register A is 1.
4-bit data, 3-bit address and 1-bit strobe signal, which are outputted from CP 29, are inputted respectively to the data input terminals (DO, D1, D2, D3), the address input terminals (AO. A1, A3) and the strobe input terminal (ST) of a PLL
frequency synthesizer U1. Additionally, a reference signal 21 of 5 MHz is inputted to a terminal (OSCI) of the PLL frequency synthesizer U2 and the output (MTLL) of a dual modulus prescaler U2 to a terminal (FI) of the PLL frequency 213`~
synthesizer. A terminal (VDD) of the PLL frequency synthesizer is connected to a power supply (VCC) and a terminal (VSS) of the PLL frequency synthesizer to the ground (GND).
The signals outputted through the terminals (FR, FV) of the PLL frequency synthesizer U1 are applied to a phase detector 23 which detects a phase difference of the two signals. The data outputted through the terminal (MOD) of the PLL frequency synthesizer U2 are inputted to a terminal (ES) of the dual modulus prescaler U2 and determines the dividing ratio of the signal inputted from a by-4 divider 26.
Additionally a terminal (LD) of the PLL frequency synthesizer U1 is connected to the negative terminal of the comparator (U3) inside a TRO alarm device 28 and detects the status of alarms of TRO. In other words, the TRO alarm device 28 detects the status of lock of the TRO output frequency by comparing the voltage outputted through the terminal (LD) of the PLL frequency synthesizer U1 to a reference voltage divided by the two resistors (R1, R2) by using a comparator (U3) and generates alarms according to the detected results.
In the meanwhile, a TRO signal divided by 4 at a by-four divider is inputted to a clock terminal (CLK) of a dual modulus prescaler U2 and the terminals (E1, E2, E3, E4) of the dual modulus prescaler U2 are grounded so that it can be used as a 10/11 dividing prescaler. A terminal ES of the dual modulus prescaler U2 is connected to a terminal MOD of the PLL
2 1 3 g 1 g 1 74092-3 frequency synthesizer U1 and selects the 10/11 dividing ratio according to the value of the data outputted through the terminal MOD.
Additionally, in the dual modulus prescaler U2, a terminal Q is connected to a terminal IN, a terminal QN to a terminal INN. terminals (VBB, VSS) to the groundt terminals (VCCO, VDD, MVCC) to a power supply (VCC) respectively.
And, the output of a phase detector 23 makes the phase difference component inputted to a low pass filter LPF 24 a direct current voltages, which is inputted to a voltage controlled oscillator VCO 25 to oscillate a frequency corresponding to the direct current control voltage.
The frequency outputted from a voltage controlled oscillator 25 is divided by 4 at a by-four divider 26 and stabilized by a PLL loop and this stabilized frequency is supplied to a TBU.
Fig. 4 is a detailed circuit diagram of the other embodiment of a transmit reference oscillator TRO according to the present invention, where a by-N divider and a by-fifteen divider are designed by using a presettabl.e counter U4, U5 which is controlled by a CP or a switch. The TRO outputs the transmit reference frequencies of 130 2/3 MHz, 132.0 MHz, 131 1/3 MHz and 134 2/3 MHz respectively according to the values of the data from a CP or a switch, namely, 1110, 1101, 1100 and 1011.
213919t 74092-3 To design by-98, 99, 100 and 101 dividers using a pre-settable counter, two 4-bit presettable counters are needed.
The by-98, 99, 100 and 101 dividers can be made by controlling the input values of the presettable counter to 10011110, 10011101, 10011100 and 10011011, respectively. Accordingly, the upper 4 bits are fixed to 1001 and only the lower 4 bits are controlled by a CP or a switch.
The 4-bit control signals outputted from a CP or a switch are inputted to the terminals (A, B, C, D) of the first presettable counter U4 according to said data value and the output terminal RCO of the second presettable counter U5 is connected to the input terminal LOAD of the first presettable counter. The output signal of a by-four divider 26 is inputted to the clock terminal CLK of the first presettable counter U4.
A power supply VCC is inputted to the terminals (ENP, ENT, CLR) of the counter U4. The output terminal RCO of the counter U4 is connected to an input terminal ENT of the second presettable counter U5.
In the meantime, to input data 1001 to the second presettable counter U5, terminals (A, D) are connected to a power supply and terminals (B, C) to the ground respectively.
Power is supplied to terminals (ENP, CLR) to operate the second presettable counter.
Additionally, the output terminal RCO of the first presettable counter U4 is connected to the input terminal ENT
of the second presettable counter U5. The output terminal RCO
of the second presettable counter U5 is connected to the terminal LOAD of both the first presettable counter U4 and the second presettable counter U5, a phase detector 23 and the clock terminal CLK of the second D-flip-flop U7 respectively.
A reference fre~uency 21 of 5 MHz is inputted to a by-fifteen divider 22, which is implemented by a presettable counter, and divided by 15 and its output is inputted to a phase detector 23.
In the meantime, a TRO alarm device 28 is constructed by two D-flip-flops, an Exclusive OR gate and a multi-vibrator.
In other words, the output signal divided by a by-fifteen divider 22 is inputted to the clock terminal of the first D-flip-flop U6, the inverted output terminal Q of the first D-flip-flop is fed back to its input terminal D and its output is inputted to one input terminal of an Exclusive OR gate.
Additionally, the inverted output terminal Q of the second D-flip-flop U7 is fed back to its input terminal D and its output is inputted to the other input terminal of an Exclusive OR gate. The output of the Exclusive OR gate is inputted to the terminal B of a multi-vibrator U9.
Power VCC is supplied to the input terminals (CLR, RXET/CEXT, CEXT) of the multi-vibrator U9 and its terminal A
is grounded. Accordingly, the multi-vibrator outputs an alarm signal TRO ALM through its terminal Q.
213gl91 Through a configuration mentioned above, the present invention not only can transmit data over the whole bands of 500 MHz, which is the bandwidth of satellite communication transponders, but also has the following specific advantages;
Firstly, it is proof against phase noises and spurious, and can be simply implemented to reduce its size and lower its prlce.
Secondly, a system can be simplified through the fact that it can be installed inside a TBU, which is used indoors and if necessary, outdoors. and has less limitation in the design of its product.
Thirdly, a transmit reference frequency of a TRO, which is a remote station , can be automatically controlled by the control of a network management system (NMS) or manually controlled by manipulating a switch.
Although the preferred embodiments of the present invention have been disclosed for illustrative purpose, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanylng clalms.
COMMUNICATIONS
BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a Transmit Reference Oscillator (TRO) of a VSAT (Very Small Aperture Terminal) for satellite communications, especially to a transmit reference oscillator for generating a reference frequency by using a frequency synthesizer so that data can be transmitted over the whole band of 500 MHz which is a bandwidth for satellite communication transponders.
Description of the Prior Art Generally speaking, a conventional remote station of a VSAT has a problem that because it is fixed to use only a specific band out of a bandwid-th of 500 MHz which is that for satellite communication transponders,said remote station or a Radio Frequency (RF) part of a VSAT has to be inevitably ~1391gl modified to change the band to be used.
Summary of the Invention To provide a transmit reference oscillator for generating a reference frequency by using a frequency synthesizer so that data can be transmitted over the whole band of 500 MHz which is a bandwidth for satellite communication transponders, without modifying a remote station or a Radio Frequency (RF) part of a VSAT, the present invention comprises a by-fifteen divider for dividing input reference signals by 15; a Voltage Controlled Oscillator (VCO) for outputting oscillation signals; a by-four divider for dividing the oscillating signals outputted from said voltage controlled oscillator. a by-N divider for dividing by N the signals divided by said by-four divider; a phase detector for outputting phase difference signals, which are the signals of the phase differences obtained by comparing the output signals of said by-N divider and those of said by-fifteen divider; and a low pass filter for varying the oscillation signals of said voltage controlled oscillator by filtering the difference signals outputted from said p~hase detector and applying the filtered difference signals to said voltage controlled oscillator.
~139191 BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Fig. 1 is a diagram showing a process for converting the transmit frequencies of a remote station of a VSAT according to the present invention;
Fig. 2 is a block diagram for showing a configuration of a transmit reference oscillator according to the present invention;
Fig. 3 is a detailed circuit diagram of an embodiment of a transmit reference oscillator according to the present invention; and Fig. 4 is a detailed circuit diagram of the other embodiment of a transmit reference oscillator TRO according to the present invention.
Detailed description of the pre-ferred embodiments Fig. 1 shows a process for converting the transmit frequencies of a remote station of a VSAT according to the present invention. A Binary Phase Shift Keying (BPSK) modulator 11 modulates digital data (base band data), which are inputted to be transmitted, into an Intermediate Frequency (IF) between 1456 - 1584 MHz, where the modulatable bandwidth is 128 MHz. by using double frequency converters. A Transmit Block Unit (TBU) 12 converts the signals modulated by said BPSK
modulator 11 up to a frequency level of 14 GHz through a Frequency Division Multiplexing (FDM) technique by using the four reference frequencies inputted from a Transmit Reference Oscillator (TRO) 13.
TRO 13 generates a reference frequency for converting the signal modulated by said BPSK modulator 11 up to a frequency of 14.0 - 14.5 GHz so that data can be transmitted over the range of 500 MHz which is the bandwidth for communication satellites. The reference frequencies outputted from said TRO 13 are 130 2/3 MHz for converting the modulated signal having 1456 - 1584 MHz into a signal having 14.000 -14.128 GHz. 132.0 MHz for converting the modulated signal having 1456 - 1584 MHz into a signal having 14.128 - 14.256 GHz. 133 1/3 MHz for converting the modulated signal having 1456 - 1584 MHz into a signal having 14.256 - 14.384 GHz and 133 1/3 MHz for converting the modulated signal having 1456 -1584 MHz into a signal having 14.384 - 14.500 GHz.
The IF signals modulated at a remote station of a VSAT
as mentioned above are converted up to a Ku band of 14 GHz and amplified by a Solid State Power Amplifier (SSPA) to access communication satellites by the values calculated in a link budget. In the meantime. said frequency up-converter and SSPA
are incorporated into a TBU 12, since a remote station of a VSAT should characteristically be small and simple in it size.
Fig. 2 shows a configuration of a transmit reference oscillator according to the present invention. A signal having a frequency level of 130 MHz is set as a transmit reference frequency to minimize the influence of inter-modulation during the conversion of the frequency as mentioned in TBU 12. The dividing factors of a frequency synthesizer are set respectively to 15 and 4 in consideration of phase noises, a spurious, and its simple implementation. The values of N for a by-N divider are set to 98, 9'3, 100, and 101 respectively to obtain Transmit Reference Signals 130 2/3 MHz, 132 MHz, 133 1/3 MHz and 134 2/3 MHz. In the mean time, a reference input frequency of TRO uses a reference signal of 5 MHz locked by a reference frequency of a hub station, while an output frequency of TRO is locked the hub station and finally the RF signals of a remote station are locked by the hub station.
In other words, the transmit reference oscillator has a configuration of a by-fifteen divider 22 for dividing input reference signals by 15, a Voltage Controlled Oscillator (VCO) 25 for outputting oscillation signals, a by-four divider 26 for dividing the oscillating signals outputted from said voltage controlled oscillator 25, a by-N divider 27 for dividing by N
the signals divided by said by-four divider 26. a phase detector 23 for outputting phase difference signals. which are the signals of the phase differences obtained by comparing the output signals of said by-N divider 27 and those of said by-fifteen 22 divider, a low pass filter 24 for varying the oscillation signals of said voltage controlled oscillator 25 by filtering the difference signals outputted from said phase detector 23 and applying the filtered difference signals to said voltage controlled oscillator 25, and a TR0 alarm device for generating alarms when phase differences outputted from said 15 divider 27 and N divider are detected from said TR0 ALM
28.
The operation of the present invention having a configuration mentioned above will be described in the following;
A reference signal 21 of 5 MHz locked by a hub station is divided into 333 1/3 KHz by a by-fifteen divider 22. The signal oscillated by VC0 25 is divided into 32 2/3 MHz. 33.0 MHz, 33 1/3 MHz and 33 2/3 MHz respectively by a by-four divider 26. The signal divided by said by-four divider 26 are again divided into 98. 99, 100 and 101 respectively by a by-N
divider 27 to become a signal of 333 1/3 KHz. The dividing ratio of the by-N divider can be controlled by the data of a Central Processor (CP) or a switch.
The phases of the 333 1/3 KHz divided respectively by a 213~
by-fifteen divider and a by-N divider as mentioned above are compared and the component having the phase difference is detected by a phase detector 23. The signal of the phase difference detected is converted into a direct current control voltage through a low pass filter 24. Accordingly said VCO 25 oscillates a frequency corresponding to the direct current control voltage inputted, and the oscillated frequency becomes a stabilized frequency by forming a loop after being locked by a reference signal of S MHz, and is converted to a desired frequency by the dividing ratio of a by-N divider. A TRO
alarm device 2~ detects whether the output of TRO (a transmit reference frequency) is locked by the reference signal of S MHz and generates alarms. Such alarms are reported to the CP of a VSAT remote station and used for a network management system(NMS).
Fig. 3 is a detailed circuit diagram of an embodiment of a transmit reference oscillator according to the present invention. A reference frequency of S MHz is divided by 15 according to CP data of a VSAT remote station by using a phase locked loop (PLL) frequency synthesizer U1.
The oscillating output signal of VCO 25 are divided by 4 at a by-4 divider 26 and then divided by N at a by-N divider 27. At a by-N divider 27 according to CP data of a VSAT remote station by using a phase locked loop(PLL) frequency synthesizer U1 and a dual modulus prescaler U2. And one desired frequency 2 139 1 g 1 74092-3 selected out of the frequencies divided by N. At a by-15 divider 22 and a by-N divider 27, the CP data of VSAT remote station consist of 3-bit address, 4-bit data and 1-bit strobe signal. and CP of VSAT remote station transmits, continuously eight times the address, the data and the stro~e to store data values in the registers R,N, and A inside the PLL frequency synthesizer U1.
A TRO output frequency is set according to the data values of CP. Here, the value of a register R is always 15. A
transmit frequency of 130 2/3 MHz is outputted when the value of a register N is 9 and that of a register A is ~. A
transmit frequency of 132 MHz is outputted when the value of a register N is 9 and that of a register A is 9. A transmit frequency of 133 1/3 MHz is outputted when the value of a register N is 10 and that of a register A is 0. A transmit frequency of 134 2/3 MHz is outputted when the value of a register N is 10 and that of a register A is 1.
4-bit data, 3-bit address and 1-bit strobe signal, which are outputted from CP 29, are inputted respectively to the data input terminals (DO, D1, D2, D3), the address input terminals (AO. A1, A3) and the strobe input terminal (ST) of a PLL
frequency synthesizer U1. Additionally, a reference signal 21 of 5 MHz is inputted to a terminal (OSCI) of the PLL frequency synthesizer U2 and the output (MTLL) of a dual modulus prescaler U2 to a terminal (FI) of the PLL frequency 213`~
synthesizer. A terminal (VDD) of the PLL frequency synthesizer is connected to a power supply (VCC) and a terminal (VSS) of the PLL frequency synthesizer to the ground (GND).
The signals outputted through the terminals (FR, FV) of the PLL frequency synthesizer U1 are applied to a phase detector 23 which detects a phase difference of the two signals. The data outputted through the terminal (MOD) of the PLL frequency synthesizer U2 are inputted to a terminal (ES) of the dual modulus prescaler U2 and determines the dividing ratio of the signal inputted from a by-4 divider 26.
Additionally a terminal (LD) of the PLL frequency synthesizer U1 is connected to the negative terminal of the comparator (U3) inside a TRO alarm device 28 and detects the status of alarms of TRO. In other words, the TRO alarm device 28 detects the status of lock of the TRO output frequency by comparing the voltage outputted through the terminal (LD) of the PLL frequency synthesizer U1 to a reference voltage divided by the two resistors (R1, R2) by using a comparator (U3) and generates alarms according to the detected results.
In the meanwhile, a TRO signal divided by 4 at a by-four divider is inputted to a clock terminal (CLK) of a dual modulus prescaler U2 and the terminals (E1, E2, E3, E4) of the dual modulus prescaler U2 are grounded so that it can be used as a 10/11 dividing prescaler. A terminal ES of the dual modulus prescaler U2 is connected to a terminal MOD of the PLL
2 1 3 g 1 g 1 74092-3 frequency synthesizer U1 and selects the 10/11 dividing ratio according to the value of the data outputted through the terminal MOD.
Additionally, in the dual modulus prescaler U2, a terminal Q is connected to a terminal IN, a terminal QN to a terminal INN. terminals (VBB, VSS) to the groundt terminals (VCCO, VDD, MVCC) to a power supply (VCC) respectively.
And, the output of a phase detector 23 makes the phase difference component inputted to a low pass filter LPF 24 a direct current voltages, which is inputted to a voltage controlled oscillator VCO 25 to oscillate a frequency corresponding to the direct current control voltage.
The frequency outputted from a voltage controlled oscillator 25 is divided by 4 at a by-four divider 26 and stabilized by a PLL loop and this stabilized frequency is supplied to a TBU.
Fig. 4 is a detailed circuit diagram of the other embodiment of a transmit reference oscillator TRO according to the present invention, where a by-N divider and a by-fifteen divider are designed by using a presettabl.e counter U4, U5 which is controlled by a CP or a switch. The TRO outputs the transmit reference frequencies of 130 2/3 MHz, 132.0 MHz, 131 1/3 MHz and 134 2/3 MHz respectively according to the values of the data from a CP or a switch, namely, 1110, 1101, 1100 and 1011.
213919t 74092-3 To design by-98, 99, 100 and 101 dividers using a pre-settable counter, two 4-bit presettable counters are needed.
The by-98, 99, 100 and 101 dividers can be made by controlling the input values of the presettable counter to 10011110, 10011101, 10011100 and 10011011, respectively. Accordingly, the upper 4 bits are fixed to 1001 and only the lower 4 bits are controlled by a CP or a switch.
The 4-bit control signals outputted from a CP or a switch are inputted to the terminals (A, B, C, D) of the first presettable counter U4 according to said data value and the output terminal RCO of the second presettable counter U5 is connected to the input terminal LOAD of the first presettable counter. The output signal of a by-four divider 26 is inputted to the clock terminal CLK of the first presettable counter U4.
A power supply VCC is inputted to the terminals (ENP, ENT, CLR) of the counter U4. The output terminal RCO of the counter U4 is connected to an input terminal ENT of the second presettable counter U5.
In the meantime, to input data 1001 to the second presettable counter U5, terminals (A, D) are connected to a power supply and terminals (B, C) to the ground respectively.
Power is supplied to terminals (ENP, CLR) to operate the second presettable counter.
Additionally, the output terminal RCO of the first presettable counter U4 is connected to the input terminal ENT
of the second presettable counter U5. The output terminal RCO
of the second presettable counter U5 is connected to the terminal LOAD of both the first presettable counter U4 and the second presettable counter U5, a phase detector 23 and the clock terminal CLK of the second D-flip-flop U7 respectively.
A reference fre~uency 21 of 5 MHz is inputted to a by-fifteen divider 22, which is implemented by a presettable counter, and divided by 15 and its output is inputted to a phase detector 23.
In the meantime, a TRO alarm device 28 is constructed by two D-flip-flops, an Exclusive OR gate and a multi-vibrator.
In other words, the output signal divided by a by-fifteen divider 22 is inputted to the clock terminal of the first D-flip-flop U6, the inverted output terminal Q of the first D-flip-flop is fed back to its input terminal D and its output is inputted to one input terminal of an Exclusive OR gate.
Additionally, the inverted output terminal Q of the second D-flip-flop U7 is fed back to its input terminal D and its output is inputted to the other input terminal of an Exclusive OR gate. The output of the Exclusive OR gate is inputted to the terminal B of a multi-vibrator U9.
Power VCC is supplied to the input terminals (CLR, RXET/CEXT, CEXT) of the multi-vibrator U9 and its terminal A
is grounded. Accordingly, the multi-vibrator outputs an alarm signal TRO ALM through its terminal Q.
213gl91 Through a configuration mentioned above, the present invention not only can transmit data over the whole bands of 500 MHz, which is the bandwidth of satellite communication transponders, but also has the following specific advantages;
Firstly, it is proof against phase noises and spurious, and can be simply implemented to reduce its size and lower its prlce.
Secondly, a system can be simplified through the fact that it can be installed inside a TBU, which is used indoors and if necessary, outdoors. and has less limitation in the design of its product.
Thirdly, a transmit reference frequency of a TRO, which is a remote station , can be automatically controlled by the control of a network management system (NMS) or manually controlled by manipulating a switch.
Although the preferred embodiments of the present invention have been disclosed for illustrative purpose, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanylng clalms.
Claims (5)
1. A transmit reference oscillator, comprising;
by-fifteen divider for dividing input reference signals by 15;
voltage controlled oscillator for outputting oscillation signals;
by-four divider for dividing the oscillating signals outputted from said voltage controlled oscillator;
by-N divider for dividing by N the signals divided by said by-four divider;
a phase detector for outputting phase difference signals, which are the signals of the phase differences obtained by comparing the output signals of said by-N divider and those of said by-fifteen divider; and a low pass filter for varying the oscillation signals of said voltage controlled oscillator by filtering the difference signals outputted from said phase detector and applying the filtered difference signals to said voltage controlled oscillator.
by-fifteen divider for dividing input reference signals by 15;
voltage controlled oscillator for outputting oscillation signals;
by-four divider for dividing the oscillating signals outputted from said voltage controlled oscillator;
by-N divider for dividing by N the signals divided by said by-four divider;
a phase detector for outputting phase difference signals, which are the signals of the phase differences obtained by comparing the output signals of said by-N divider and those of said by-fifteen divider; and a low pass filter for varying the oscillation signals of said voltage controlled oscillator by filtering the difference signals outputted from said phase detector and applying the filtered difference signals to said voltage controlled oscillator.
2. A transmit reference oscillator in accordance with claim 1, further comprising a TRO alarm device for generating alarms when a phase difference is detected at said phase detector.
3. A transmit reference oscillator in accordance with claim 1, wherein the oscillating signal outputted from said voltage controlled oscillator is divided by said by-four divider into one of the four signals of 32 2/3 MHz, 33.0 MHz, 33 1/2 MHz and 33 2/3 MHz.
4. A transmit reference oscillator in accordance with claim 3, wherein the signal, which has been already divided by said by-four divider into one of the four signals of 32 2/3 MHz, 33.0 MHz, 33 1/2 MHz and 33 2/3 MHz, is again divided by N
at said by-N divider to output a signal of 333 1/3 KHz.
at said by-N divider to output a signal of 333 1/3 KHz.
5. A transmit reference oscillator in accordance with claim 1, wherein the reference signal inputted from a reference frequency of 5 MHz is divided by 15 at said a by-fifteen divider and the divided signal is 333 1/3 KHz.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1993-30901 | 1993-12-29 | ||
| KR1019930030901A KR960014676B1 (en) | 1993-12-29 | 1993-12-29 | Satellite telecommunication |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2139191A1 true CA2139191A1 (en) | 1995-06-30 |
Family
ID=19373890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002139191A Abandoned CA2139191A1 (en) | 1993-12-29 | 1994-12-28 | Transmit reference oscillator of a vsat for satellite communications |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH07273644A (en) |
| KR (1) | KR960014676B1 (en) |
| CA (1) | CA2139191A1 (en) |
| DE (1) | DE4447142A1 (en) |
| GB (1) | GB2285353A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7796024B2 (en) | 2007-02-07 | 2010-09-14 | Db Systems, Llc | Automated multi-purpose alert system with sensory interrupts |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3932821A (en) * | 1974-11-08 | 1976-01-13 | Narco Scientific Industries, Inc. | Out of lock detector for phase lock loop synthesizer |
| US4182994A (en) * | 1977-08-22 | 1980-01-08 | Rca Corporation | Phase locked loop tuning system including stabilized time interval control circuit |
| JPS58107715A (en) * | 1981-12-22 | 1983-06-27 | Sony Corp | Channel selecting device |
| JPS60107920A (en) * | 1983-11-16 | 1985-06-13 | Toshiba Corp | Communication equipment using phase synchronizing circuit |
| JPS61157028A (en) * | 1984-12-28 | 1986-07-16 | Fujitsu Ltd | Frequency synthesizer |
| JPH01256224A (en) * | 1988-04-05 | 1989-10-12 | Fujitsu Ltd | Synthesizer channel detecting circuit |
| JPH0529932A (en) * | 1991-07-24 | 1993-02-05 | Matsushita Electric Ind Co Ltd | Clock switching device |
-
1993
- 1993-12-29 KR KR1019930030901A patent/KR960014676B1/en not_active Expired - Fee Related
-
1994
- 1994-12-20 GB GB9425738A patent/GB2285353A/en not_active Withdrawn
- 1994-12-27 JP JP6324280A patent/JPH07273644A/en active Pending
- 1994-12-28 CA CA002139191A patent/CA2139191A1/en not_active Abandoned
- 1994-12-29 DE DE4447142A patent/DE4447142A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| GB2285353A (en) | 1995-07-05 |
| GB9425738D0 (en) | 1995-02-22 |
| JPH07273644A (en) | 1995-10-20 |
| KR960014676B1 (en) | 1996-10-19 |
| DE4447142A1 (en) | 1995-07-06 |
| KR950022254A (en) | 1995-07-28 |
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