CA2184804C - High frequency differential filter with cmos control - Google Patents

Abstract

A programmable high frequency active filter comprises a plurality of basic building blocks connected in parallel. A basic building block includes a transistor pair connected in a differential amplifier configuration, an impedance connected between the emitters of the transistors and a switching block for applying the necessary bias current to the transistors. The transfer function of the filter is programmed with a digital word, the length of which determines the number of basic building blocks included in the configuration. In this way, the equivalent high frequency impedance of the filter is controlled by selecting the configuration and the value of the impedance of each building block.

Description

21 ~4804 -, .
A HIGH FREQUENCY DIFPERENTIAL FILTER WlTH CMOS CONTROL
BACKGROUND OF THE INVENTION

Field of the invention This invention relates to a high frequency differential filter and more particularly to a circuit for filtering of signals up to very high frequencies in such a way that the filter flmction is ~.ugld-l-llLable.
Back~round Art Modern telephone ronnmlmir~hr,n lines not only carry voice and supervisory signals which lie within a low-frequency range less than 3 kHz, but also serve to convey data signals in a high-frequency 15 range which may be as high as several GHz. Because ordinary telephone lines have a poor amplitude response in the high frequency range, it is present practice to interpose an Pql1~li7in~ module in the line at the receiver side to afford a sllhst~nh:~lly uniform signal gain over a broad frequency spechrum including the majority of the power of 20 the signal, generally from DC to half the symbol rate applied to the cable.
A telephone line equalizer is a device adapted to correct or compensate for some specified characteristic of the line which is regarded as undesirable. By the use of an equalizer, one can imprbve 25 particular lime characteristics and thereby enhance the quality or grade of the received signal. ~LS the losses of a telephone line are such that its ~mplitll-lP response falls off as the frequency of the signal carried over the line increases, the equalizer generally is designed to provide a rising gain with an increase in frequency. Proper ~1jllchmPnt of the equalizer 30 is attained when the equalizer ~Ulll ~ d~L'S for the line losses over the entire band of useful frPTlPnriPc.
In general, the equalizer is a filter whose s~hruchure is described with integrators and amplifiers connected in feedback and feed forward topologies, which are difficult to realize in practical circuits at high 35 frPqllPnriP~. Currently, designers are forced to use simpler lossy ey~Ld~l:~ and dirrL l~LlLidiul:~ for high speed (>50 MHZ) applir~hrnc Universal programmable active filters generally employ operational _, . , _ _ _ _ .. . .. . . .. . . ... . . .. . . . . .

~3

2 2 1 84804 ~mrlifirr~c with some form of resistive feedback loop from the output to the negative input, to allow the flow of current from the inverting input to the output of the operational amplifier. ~hen the signal spech um exceeds 20 MHz, bipolar processes of 10 GHz and higher are eurrently used. The resistor is switched into and out of the feedback path using MOS switches. However, resistors are diffieult to integrate on a single silicon chip so as to be switehed into and out, due to distortions and inaccuracy of resulting resistance value, which is difficult to eonhrol. To ~ Vt!llt this problem, prior art filters use external resistors rather than on-chip resistors.
Other prior art filters use capacitors in the feedback path.~
'~r~ritnrc are easier to fabricate in a small area of the ehip, and they can also be accurately switched with MOS switches. However, a capacitor does not permit DC current to flow, which prevent. the inverting input node from periodically being brought back to the DC offset voltage of the operational amplifier as required, so that resistors must be also rnnn~rhod in parallel for the necessary DC path. Tntl~gr~hnn of such circuitc into a single ehip requires ci~nifir~nf silicon area. In addition, due to the lengthl of feedback paths obtained in this way, delays and parasitic impedances are ~rrllmlllAtPcl and therefore the ability to synthesize high frequencies is limited~
For example, United States Patent No. 5,225,790 (Noguchi et al., issued July 6, 1993 to Digital Equipment Corporation) discloses a wideband, programmable first and second order filter network which provides eonstant gain and nnrm~li7P~l frequeney response as the resonant frequency is varied. The filter comprises a differential pair of hr:mci~nrc with the emitters coupled through a capacitor. A positive feedbaek eircuit feeds the differential pair through a resistive eireuit and a eonhrol circuit is coupled to the amplifier to provide ;~fljl-cfAhl~
frequency conhrol by varying the respective emitter currents and the ,e~liv~ collector loads. Besides the di~a~vd~ ges discussed above in rnnnrrhnn with the feedback, the control eircuit diselosed in this patent is a multiplier circuit of a complicated structure. At high fr~q~ nri~c this eircuit becomes difficult to realize in practice.
In addition, at high frf~ql1~n~ c, the relative tolerance of all elements is larger due to the generally smaller values and sizes used for r:~r~ritnrS resistors and active elements and the finite tolerance on _ . . _ _ _ _ . . . . .. .. . . . ..

3 21 8~80~
component ~limPn~ n~i. Compensation for these factors is made easier by the use of programmable elements, if p~ is not compromised.
In this description, "very high frequency" is a relative term in~ Afin~ that the required frequency of operation is such that the trAn~ron~llcfAncP of available active elements is reduced to the point where the device power gain is approaching unity.
SI~MMARY OF THE INVENIION
It is an object of this invention to reduce or eliminate the drawbacks of the prior art high frequency filters.
It is another object of this invention to provide a filter structure which adds gain at high frequencies while not modifying low frequencies of the input signal.
Still another object of this invention is to provide a u~ allllllable filter for very high frequencies which is essentially nAffPrfP~l by the electronics of the controlling signal. The filter disclosed herein is controlled by a CMOS signal, and is capable of using various differential signal formats in the signal path.
Another object of the invention is to create a filter element which can be combined with other such elements to create a o~ldllllllable filter of increased complexity.
Accordingly, this invention provides a programmable high frequency active filter for receiving a differential input signal and providing a differential output signal, the filter comprising a differential amplifier rompricing a first and second transistor, the first transistor having a first load and bemg biased with a first bias current source, the second transistor having a second load and being biased with a second bias current source; an impedance connected between the emitters of the pair of ~Idn~i~Lul~ for providing a frequency dependent dirr~ ial voltage gain for the amplifier; and a switching block for l-~nnPrfin~ and ~licfonnPcfin~ the first and second bias current sources to the first and second llal~is~ul~ liv~:ly, according to a digital control signal.
The invention also provides a ~Iu~;lallllllable high frequency active filter for receiving a differential input signal and providing a differential output signal, the filter comprising â plurality (N) of

4 2~ ~4804 differential amplifiers connected in parallel, each differential amplifier AMPi, where i is an integer and i-~[l,N], rr,mrricin~ a first and a second transistor having a first load and being biased with a first bias current source, the second transistor having a second load and being biased

5 with a second bias current source; a like plurality (N) of impedance units, each impèdance unit being associated with a dirrt ~ ial amplifier, an impedance unit Zi being connected between the emitters of the dirr~l~l.Lial amplifier AMPi for providing a frequency dependent di~ llLial voltage gain for the dirr~l~llLial amplifier AMPi; and a like 10 plurality (N) of switching blocks, each switching block being :Iccr~ri:~tr~1 with a dirr~l~llLidl amplifier, a switching block SWi for rr~nn~rtin~ and disconnecting the first and second bias current source of the differential amplifier AMPi to the first and second transistor, respectively, according to a digital control signal.
The invention further provides a programmabie high frequency active filter for receiving a differential input signal and providing a differential output signal, the filter ~:O~ ibillg a differential amplifier comprising a first and second transistor, the first transistor having a first load resistor and being biased with a first bias current source, the 20 second transistor having a second load resistor and being biased with a second bias current source; a capacitive network connected between the emitters of the first and second Llc~ iblul~ for providing a frequency dependent differential voltage gain for the amplifier; a first MOS device rrlnnf.r~d with the drain and source between the emitter of the first 25 transistor and the first current source; a second MOS device rrlnnpc~
with the drain and source between the emitter of the second transistor and the second current source; a third MOS device connected with the source and drain between the collector of the first transistor and the first current source; and a fourth MOS device connected with the 30 source and drain between the collector of the first transistor and the second current source; and wherein the gates of all the MOS devices are crlnn~r~l'r~ to receive the digital control signal.
A ci~nifir~n~ feature of this invention over the e~dsting systems is that it makes it possible to program the gain for the high frequency 35 band.
The high rl~4u~ll.y differential filter with CMOS control of this invention may be used.for a completely integrated Ll~lls.~iv~ s~lution for 155 Mb/s L,.l~".; on over Category 5 1~nqhiPl~lP~l twisted pair cabling (UPT-V). The design of this invention may be used as well in many other applications where a ~lu~ able high frequency filter is needed. The technology disclosed herein is viewed as a key technology 5 for introduction of ATM transport to the desktop. A major challenge for achieving this goal is the large scale intP~r~t~on of analog and digital circuitry at 155 MHz and above.
BEIEE ~ESCRIPTION OE THE DRAWINGS
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular~
description of the preferred embodi~ l.ls, as illustrated in the appended drawings, where:
Figurb IA is a block diagram of an equalizer using programmable filters according to this invention;
Figure lB illustrates the equivalent impedance for the high frequency building block filter;
Figure lC shows the equivalent impedance for the low and band pass building blocks;
Figure 2A illustrates a simulated frequency response for a three stage equalizer;
Figure 2B is an eye diagram showing the data signal without the equalizer;
Figure 2C is an eye diagram showing the equalizer effect on the data signal;
Figure 2D shows the measured frequency response of the equalizer of Figure IA for one particular setting;
Figure 2E shows the combined cable and equalizer response;
Figure 3 is a block diagram of a basic buildingblock filter for high frequency zeroes of the frequency response;
Figure 4 is an electric schematic of the basic building block of the of the high frequency differential ,u.u~lal..l..able filter;
Figure 5A illustrates the electric schematic,of a complex L,lu~,lall~lllable high frequency filter; and Figure 5B illustrates the equivalent circuit for a multitude of building blocks connected in parallel.

6 2184804 DESCRIE~IION OF THE ~ ~L~ IJ EMBODIMENT
Figure lA illustrates the overall structure of an equalizer used for extracting a bandwidth of interest from a received signal.
The pole/zero r~ tionchirs for the equalizer are chosen to 5 invert the expected loss at high frequencies in signals l~ d over twisted pair cabling. For lossy lines, for example, it is desirable to provide means to echo loss versus frequency char~tPri~tl-~c Thus, the transfer function of the equalizer may be chosen:
(--+1) (-- ) ( +1) h(s) = kz2~0 k;~36~0 (kpl~)o (kp2~)0 ) where kz2~ k~3, kpl, kp2, are the ratios of pole/zero frl~q -~n~ c and p(s) is the parasitic pole response.
Pole and zero tracking accuracy for an equalizer should be very accurate and dependent upon the conforming impedance only. The minimum parasitic pole frequency a)p must be out of band to ensure a minimllm preset eqll~li7~tinn Two different circuit topologies are used for the equalizer stages.
(I) According to this invention, the zeros at high frequency, as is the zero at kj~3~0, are formed with parallel selectable capacitor-degenerated differential pairs generally referenced as numeral 10 in Figure IA. The equivalent impedance of these blocks at high frequencies is shown in Figures IB and IC The differential gain of the high frequency building block 10 is controlled with a digital CMOS
signal 16, so that the high frequency zeroes may be provided with accuracy and the losses in input signal lla~ d over the telephone pair are compensated. Digital control is used to reduce signal coupling.
This block is designed to filter signals up to very high freqll~n~ c while adding gain at these high frf~qll~n~ i~c (2) The two poles at kpl a)0, kp2 ~o and two lower frequencies zeroes at kz2 ~v0 and kz3 lo0 may be formed with differential pair amplifiers degenerated with ~lv~ lllable R-C networks, referenced as numeral 15 in Figure IA. The equivalent impedance of these blocks at the frequency of interest is shown in Figure lC The differential gain , . , .. . . . . . : . . . . _ . _ _ . .

7 2184~04 is controlled with control signals 11 to 14 which set the impedance of the block for a particular resulting response. The two types of building blocks are cascaded, the equalizer receives-a differential input signal inl-in2 on the input terminals 4 and 5 and provides a differential output signal out1'-out2' on output terminals 8~ 9.
Figure 2A illustrates a simulated frequency response (V/F) for a three stage equalizer. Curves a to h show the progr~mm~hility of the equalizer using the circuit of this invention. The control word ramp is 0:255 and the value of the word is 255,128, 64, 32,16, 8, 4, 2,1, and 0, l~a~e~Lively.
The low frequency response from 10 kHz to I MHz is corfigured using two filter sections 15 as illllctr~t~(l in Figures IA and IC.
Figure 2B is an eye diagram illustrating the data signal without the equalizer, while Figure 2C is an eye diagram showing the equalizer effect on the data signal Figure 2D is a graph obtained with a network analyzer showing the measured frequency response of the equalizer of Figure lA for one particular setting and Figure 2E shows the combined response of cable and equalizer using a one stage filter according to this invention.
The frequency response is adapted to comply with several conflitinnc of external components, as well as rnn~1itio~c of an integrated circuit, as it may be fabricated.
Nominal constant values for obtaining the frequency response illustrated in Figure 2E were ~r~/~rminl~l to be: kz2 = 10, k~3 = 50, kpl =
1.44 and kp2 = 14.4. Pole and zero tracking with this structure of equalizer is better than 1% and the minimum parasitic pole frequency is ~p = 200 MHz. A minimum of 35 dB equalization was obtained expPriml~n~lly.
Figure 3 illustrates the general schematic for the high frequency building block 10 in block diagram form. A building block 10 comprises a dir~ l,Lial amplifier 1, an impedance block 2, a switching unit 3 and a current source 20. Differential amplifier 1 comprises two matched transistors Q1 and Q2 whose bases are connected to respective differential input terminals 4 and 5. Although each collector is cnnn~rh~<l to the positive supply voltage Vdd through a resistances R1 and R2, this rnnn~rtir~n is not essential to the operation of the t~ f~

8 21 84~4 onm~ tl~(1 to other lldllsis~ul~ rather than to resistive loads. It is essential though, that the collector circuits be such that Q1 and Q2 never enter saturation and that the l~dllsisLul, Q1 and Q2 and loads R1 and R2 are matched to each other.
The load resistors Rl and R2 serve to convert the output current to a voltage. Q1 and Q2 receive a high frequency input signal inl and in2, l~e~liv~ly, on their bases. The important response of the circuit is the differential gain measured from vin (vin=inl-in2) to Vout (VoUt=outl-out2)-The impedance block 2 is connected between the emitters of the active devices Ql and Q2, for reshaping the frequency response of the dirr~ dl amplifier 1. Transistors Q1 and Q2 are biased by a bias current source 20 comprising twû separate constant sources. Current source 21 provides the bias current Il to transistor Ql and current source 22 provides the bias current I2 to transistor Q2.
The response of the circuit is modified by adjusting the current input by sources 21 and 22 into the emitters of Ql and Q2. This is obtained using a switching unit 3 made of switches 25 and 26, which shift currents Il and I2 between the emitter and collector circuits of the l~ Liv~ transistor. Switches 25 and 26 are controlled by raising or lowering the potential of signal 16 (signal "PROG") to activate or deactivate the differential pair.
When the switching block is in a first state, current source 21 is rnnn(~rtPd to the emitter of Ql and current source 22 is ~-~nm~rtPd to the emitter of Q2. A path is ~ nmrl~tPd for the bias current I1 through contacts S1-A1, and for bias current I2 through contacts S2-A2. In this case, active devices Ql and Q2 are biased in their normal operating range with bias current Il and I2, l~ue~ ly. The differential gain of the circuit will be ~IPrPnl1Pnt upon the tr~n~rr~n~ t~n~p of Ql and Q2, and the impedance Z placed between the emitters. If impedance Z is reactive, then the dirr~l~lllial output Vout is frequency dependent.
When the switching block is in a second state, a path for currents Il and I2 is ~Ct~hlichl~d through contacts S1-B1 and S2-B2, le~e-liv~ly.
Now the bias currents I1 and I2 traveling through the active devices Q1 and Q2 are reduced and hence the tr~n~on~ rt~nfp~ of Q1 and Q2 are reduced to essentially zero. This has the effect of reducing the differential gain from vin to Vout to essentially zero. The common-

9 21 84804 mode voltage of output signals outl and out2 is llnrhAn~Prl, since the bias current is mAintAinP~I through load resistors Rl and R2.
Figure 4 illustrates the circuit diagram of the high frequency basic building block 10, showing a preferred Pmho~impnt for the switching 5 circuit 3. The switching block 3 is embodied by a current steering switch of the type disclosed in U.S. Patent No. 5,429,529 (Guay et al., issued May 30,1995 to Northern Telecom Limited).
The first switch 25 is made by a pair of ~r,mrlPmPntAry MOS
devices M1 and M3, and the second switch 26 comprises a pair of

10 r~mrlPmPntAry MOS devices M2 and M4. The first device M1 is rrlnnPrtpd between the current sources 21 and the emitter of transistor Q1, while the third device M3 is connected between source 21 and the collector of Q1. Similarly, the second device M2 is connected between the current source 22 and the emitter of transistor Q2, while fourth device M4 is rnnnPrtP~1 between source 22 and the collector of Q2.
M1 and M2 are NMOS devices and M3 and M4 are PMOS devices in the embodiment illustrated in Figure 4. The substrate rnnnPrtirlnc for the devices M1 to M4 are not shown, but are assumed to be d~lv~--a~e for the fabrication technology. Typically, the PMOS
substrates will be connected to Vdd and NMOS substrates will be connected to Vss Devices M1 to M4 are turned "on" or "ofP' by raising or lowering the potential of the signal "PROG" applied on their gates.
When the signal PROG is at, or near the positive supply rail Vdd, devices M1 and M2 are "on" while devices M3 and M4 are "off".
Active devices Ql and Q2 are biased in their normal operating range with bias currents I1 and I2, respectively.
If the signal PROG is near, or at the negative supply rail Vss, devices M1 and M2 are turned "off", reducing the bias current and hence the transrr,n~llrtAnrP of Q1 and Q2 to zero.
The selection of switches M1 to M4 must be made using criteria - such that the circuit elements creating the current sources 21 and 22 are not affected by the impedance of the switches, namely, must always operate as current sources. This, in practice, requires that the "on"
drain to source voltage usually not be less than 200~300mV.
The degeneration networks are ~~ t~1y balanced with respect to parasitics so that any noise injection, including that from noise lO 21 84804 signals, has a common mode component only. This reduces the effective switch resistance from (1/gm+RMos) to l/gm), removing the parasitic poles from the pass-band.
Impedance Z is ~ ably a capacitor, but can be any realizable 5 network of passive or active components.
Several (N) independently controlled basic building blocks 10 can be paralleled to provide a filter with high frequency gain, with a pl~grdllullable "corner frequency". Such a filter is illustrated in Figure 5A. Figure 5A shows "i" basic building blocks 10 having, le~e~liv~ly, ranges 0,1 and i, where i is an integer and i~[0,N]. Each block 10 comprises an impedance block 2. All blocks 10 are ronn~-t~l ir~
parallel with the bases of the respective transistor pairs Qli, Q2i cnnn~rt~d to differential input terminals 4, 5, and with the collectors of transistor pairs Q1i and Q2i connected to differential output terminals 15 6, 7. Resistors R1 and R2 are provided between the output lines and the supply voltage Vdd-Each basic block 10 receives a digital signal Pi, all digital signals Piforming the control word PROG. A basic unit is added or subtracted from the filter in accordance with the rnndllr~n~ or non-ron~ rting 20 state of the active devices Q1 and Q2. The control word PROG
~1~t~rrninl~c which block contributed to the transfer characteristic of the filter. In this way, the impedance of the resulting filter may be set by varying the number of basic units introduced in parallel.
Figure 5B illustrates an equivalent circuit for the filter of Figure 25 lA. Here, each building block is ~ s~ ed as an impedance Zi ronn~ t~-l in series with a switch SWi. A number (N) of such building blocks is vnn~rtPrl in parallel between the input and the output. An impedance block Zi is added or subtracted from the filter in accordance with the status of the switching circuits SWi. Control of ~0 is via 30 digital CMOS signal PROG applied on terminal 16. Signal PROG
tf~ninl~s which impedance block Zi contributes to the frequency response.
The transfer function of the high frequency programmable filter of Figures 5A and 5B is:5 v =(Rl +R2). ~,Pi z f3 ~3

11 27848~4 where Pi = {1 } is the ith control signal and Zi = s is the domain expresslon of the ith stage. In the case of one resistor (Rz) and several capacitive impedances Ci, the expression would be:
Vi ( I R2) [RZ+(SC1-PI)+(SC2 P2)+(SC3~P3)+~]
If the value of the ~ Ar~-i~n~ c are selected to satisfy the following conditions:
C2 = 2CI
C3 = 2C2 ' CN = 2cN-l~
15 the dirr~ ial gain becomes:
-( IR 2) [l+sRC'], . where C' = ~ piCi which is the transfer function of a single variable zero with a (~ ~) 20 scaling factor and a zero at f = 2 RC
The programmable filter disclosed herein may be employed in applications using very high frequency differential signals of various formats. The position of the high frequency zero on the transfer 25 characteristic of the filter may be varied as necessary for a particular application, by simply using a digital signal, with digits Po to PN
selected as needed. The filter may be used, for example, to compensate for a lossy element such as a twisted telephone pair or other inherently differential medium, including complementary striplines, ribbon 30 cables, etc. This filter is equally applicable for digital or analog signaling formats.

12 2 1 84804 While the invention has been described with reference to particular example embodiments, further mflflifi~ ~ions and ,.v\~ lents which will occur to those skilled in the art, may be made within the purview of the appended claims, without departing 5 from the scope of the invention in its broader aspect.

Claims (20)

WHAT IS CLAIMED IS:

1. A programmable high frequency active filter for receiving a differential input signal and providing a differential output signal, said filter comprising:
a differential amplifier comprising a first and a second transistor, said first transistor having a first load and being biased with a first bias current source, said second transistor having a second load and being biased with a second bias current source;
an impedance connected between the emitters of said transistors for providing a frequency dependent differential voltage gain for said differential amplifier; and a switching block for connecting and disconnecting said first and said second bias current source to said first and said second transistor Lively, according to a digital control signal.

2. A filter as claimed in claim 1, wherein said impedance is a reactance.

3. A filter as claimed in claim 1, wherein said impedance is a capacitive network.

4. A filter as claimed in claim 1, wherein said first and said second transistors have substantially similar parameters.

5. A filter as claimed in claim 1, wherein said switching circuit comprises:
a first switch for switching the bias current produced by said first current source between the emitter and the collector of said first transistor; and a second switch for switching the bias current produced by said second current source between the emitter and the collector of said second transistor.

6. A filter as claimed in claim 5, wherein said first switch comprises a CMOS pair of a first and a third MOS device and said second switch comprises a CMOS pair of a second and a fourth MOS
device.

7. A filter as claimed in claim 6, wherein said first and said second MOS devices are PMOS transistors, and said third and fourth MOS devices are NMOS transistors.

8. A filter as claimed in claim 6, wherein said first MOS device is connected with the drain and source between the emitter of said first transistor and said first current source, and said third MOS device is connected with the source and drain between the collector of said first transistor and said first current source.

9. A filter as claimed in claim 6, wherein said second MOS
device is connected with the drain and source between the emitter of said second transistor and said second current source, and said fourth MOS device is connected with the source and drain between the collector of said second transistor and said second current source.

10. A filter as claimed in claim 6, wherein the gates of all said MOS devices are connected to receive said digital control signal.

11. A programmable high frequency active filter for receiving a differential input signal and providing a differential output signal, said filter comprising:
a plurality (N) of differential amplifiers connected in parallel, each differential amplifier AMPi comprising a first and a second transistor, said first transistor having a first load and being biased with a first bias current source, said second transistor having a second load and being biased with a second bias current source;
a like plurality (N) of impedance units, each impedance unit being associated with a differential amplifier, an impedance unit Zi being connecting between the emitters of said differential amplifier AMPi for providing a frequency dependent differential voltage gain for said differential amplifier AMPi; and a like plurality (N) of switching blocks, each switching block being associated with a differential amplifier, a switching block SWi for connecting and disconnecting said first and said second bias current source to said first and said second transistor of said amplifier AMPi, respectively, according to a digital control signal;
where i is an integer and i?[1,N]

12. A programmable filter as claimed in claim 11, wherein said impedance unit Zi is a capacitance.

13. A filter as claimed in claim 11, wherein said switching circuit SWi comprises:
a first switch for commuting the bias current produced by said first current source between the emitter and the collector of said first transistor; and a second switch for commuting the bias current produced by said second current source between the emitter and the collector of said second transistor.

14. A filter as claimed in claim 13, wherein said first switch comprises a first CMOS pair of a first and a third MOS device, and said second switch comprises a second pair of a second and a fourth MOS
device.

15. A filter as claimed in claim 14, wherein said first and said second MOS devices are PMOS transistors, and said third and fourth MOS devices are NMOS transistors.

16. A programmable high frequency active filter for receiving a differential input signal and providing a differential output signal, said filter comprising:
a differential amplifier comprising a first and second transistor, said first transistor having a first load resistor and being biased with a first bias current source, said second transistor having a second load resistor and being biased with a second bias current source;
a capacitive network connected between the emitters of said first and second transistors for providing a frequency dependent differential voltage gain for said amplifier;

a first MOS device connected with the drain and source between the emitter of said first transistor and said first current source;
a second MOS device connected with the drain and source between the emitter of said second transistor and said second current source;
a third MOS device connected with the source and drain between the collector of said first transistor and said first current source; and a fourth MOS device connected with the source and drain between the collector of said second transistor and said second current source;
wherein the gates of all said MOS devices are connected to receive a digital control signal.

17 A filter as claimed in claim 1, wherein said differential input signal has a format compatible with transmission over a differential medium.

18. A filter as claimed in claim 17, wherein said differential medium is any of a twisted telephone pair, a pair of complimentary striplines, and a ribbon cable.

19. A filter as claimed in claim 1, wherein said differential input signal is a digital signal.

20. A filter as claimed in claim 1, wherein said differential input signal is an analog signal.