CA2267870A1 - Memoire de surface lineaire convertie en algorithme ou en mecanisme de juxtaposition spatiale - Google Patents

Memoire de surface lineaire convertie en algorithme ou en mecanisme de juxtaposition spatiale Download PDF

Info

Publication number
CA2267870A1
CA2267870A1 CA002267870A CA2267870A CA2267870A1 CA 2267870 A1 CA2267870 A1 CA 2267870A1 CA 002267870 A CA002267870 A CA 002267870A CA 2267870 A CA2267870 A CA 2267870A CA 2267870 A1 CA2267870 A1 CA 2267870A1
Authority
CA
Canada
Prior art keywords
memory
pixel
data
pixels
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002267870A
Other languages
English (en)
Inventor
Scott Hartog
Michael Mantor
John Austin Carey
Thomas A. Piazza
Ralph Clayton Taylor
Matthew Radecki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2267870A1 publication Critical patent/CA2267870A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C2029/1806—Address conversion or mapping, i.e. logical to physical address

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Generation (AREA)
  • Image Input (AREA)
  • Memory System (AREA)
CA002267870A 1998-04-01 1999-03-31 Memoire de surface lineaire convertie en algorithme ou en mecanisme de juxtaposition spatiale Abandoned CA2267870A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US8027098P 1998-04-01 1998-04-01
US60/080,270 1998-04-01

Publications (1)

Publication Number Publication Date
CA2267870A1 true CA2267870A1 (fr) 1999-10-01

Family

ID=22156301

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002267870A Abandoned CA2267870A1 (fr) 1998-04-01 1999-03-31 Memoire de surface lineaire convertie en algorithme ou en mecanisme de juxtaposition spatiale

Country Status (4)

Country Link
JP (1) JP2000090280A (fr)
CA (1) CA2267870A1 (fr)
GB (1) GB2336086B (fr)
TW (1) TW513676B (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6417848B1 (en) * 1997-08-25 2002-07-09 Ati International Srl Pixel clustering for improved graphics throughput
AU731863B2 (en) * 1999-04-29 2001-04-05 Canon Kabushiki Kaisha Image processing operation in hierarchical memory systems
EP1287494B1 (fr) 2000-06-08 2007-03-14 Imagination Technologies Limited Mosaique et compression pour rendre des images 3d
EP2587454B1 (fr) 2010-06-24 2017-12-13 Fujitsu Limited Dispositif de dessin et procédé de dessin
US9232156B1 (en) 2014-09-22 2016-01-05 Freescale Semiconductor, Inc. Video processing device and method
CN113375568B (zh) * 2021-05-12 2023-03-31 苏州阿普奇物联网科技有限公司 一种基于激光扫描的金属拉丝抛光不良检测方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5131080A (en) * 1987-08-18 1992-07-14 Hewlett-Packard Company Graphics frame buffer with RGB pixel cache
US5251293A (en) * 1987-09-02 1993-10-05 Ascii Corporation Character display apparatus
US5056044A (en) * 1989-12-21 1991-10-08 Hewlett-Packard Company Graphics frame buffer with programmable tile size
US5517609A (en) * 1990-08-06 1996-05-14 Texas Instruments Incorporated Graphics display system using tiles of data
TW245871B (en) * 1994-08-15 1995-04-21 Gen Instrument Corp Method and apparatus for efficient addressing of dram in a video decompression processor

Also Published As

Publication number Publication date
GB2336086A (en) 1999-10-06
TW513676B (en) 2002-12-11
JP2000090280A (ja) 2000-03-31
GB9907701D0 (en) 1999-05-26
GB2336086B (en) 2002-12-11

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Legal Events

Date Code Title Description
EEER Examination request
FZDE Discontinued
FZDE Discontinued

Effective date: 20080331