CA2303895A1 - Communication device for transmitting message signals - Google Patents
Communication device for transmitting message signals Download PDFInfo
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- CA2303895A1 CA2303895A1 CA002303895A CA2303895A CA2303895A1 CA 2303895 A1 CA2303895 A1 CA 2303895A1 CA 002303895 A CA002303895 A CA 002303895A CA 2303895 A CA2303895 A CA 2303895A CA 2303895 A1 CA2303895 A1 CA 2303895A1
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- 238000004891 communication Methods 0.000 title claims abstract description 14
- 230000000712 assembly Effects 0.000 claims abstract description 25
- 238000000429 assembly Methods 0.000 claims abstract description 25
- 230000008878 coupling Effects 0.000 claims abstract description 23
- 238000010168 coupling process Methods 0.000 claims abstract description 23
- 238000005859 coupling reaction Methods 0.000 claims abstract description 23
- 230000005540 biological transmission Effects 0.000 claims abstract description 13
- 238000012986 modification Methods 0.000 abstract description 2
- 230000004048 modification Effects 0.000 abstract description 2
- 238000011144 upstream manufacturing Methods 0.000 abstract description 2
- 238000012546 transfer Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 241000426682 Salinispora Species 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- YFONKFDEZLYQDH-OPQQBVKSSA-N N-[(1R,2S)-2,6-dimethyindan-1-yl]-6-[(1R)-1-fluoroethyl]-1,3,5-triazine-2,4-diamine Chemical compound C[C@@H](F)C1=NC(N)=NC(N[C@H]2C3=CC(C)=CC=C3C[C@@H]2C)=N1 YFONKFDEZLYQDH-OPQQBVKSSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 235000002020 sage Nutrition 0.000 description 1
- 230000003612 virological effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
- H04L49/254—Centralised controller, i.e. arbitration or scheduling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/256—Routing or path finding in ATM switching fabrics
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/552—Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5625—Operations, administration and maintenance [OAM]
- H04L2012/5627—Fault tolerance and recovery
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention relates to a communication device (KE) to transmit message cells respectively provided with routing information. The inventive device comprises a coupling device (ASN) and line assemblies (LIC AO, ..., LIC A15) allocated thereto, whereby a switching logic circuit (LPS) is located in the outgoing direction of transmission inside the coupling device (ASN) upstream from said line assemblies. The message cells can be forwarded to any specific number of line assemblies without modification of their routing information.
Description
MAR-1,T-00 08:56 CA 02303895 2000-03-17 P.03 R-417 Job-854 MAR. -17' 00(FRI) 09:99 HILL STEADMAN P. 003 COMMUNICATION DEVICE, r~UR TRANSMITTING MFSSAGIS1UNALS
The invention relates to a communication device according to the preamble of patent claim 1.
Depending on the fault tolerance required of a cummLtnicatiun device. di fferent redundancy structures can bee [sic] provided for the peripheral line assemblies belonging thereto. Examples of this are the "1+1", "1:1", and "1:N" types of line assembly redundancy, as is described in "IEEE .Tournal on Selected Areas in Communications" (Vol. 15, N. 5, Juna 1997, pp. 795-B06). In a "1+1" redundancy structuxe, two line assemblies are operated in parallel, in order to transmit message signal currents over them redundantly. But only one of these redundant message signal currents is considered for further processing.
In a "1-r-1 " line assembly redundancy, only 'one of two line assemblies is used as the active line assembly, while a changeover onto the ether line assembly, which serves as a back-up assembly, occurs only in case of a failure of the active line assembly.
Finally, in a "1:N" line assembly redundancy, in ~iclditiori to a plurality N
of line 2 o assemblies, a single backup line assembly is provided. When a failure occurs on one of the N line assemblies, the backup line assembly is then used instead.
In a "1:N" line assembly redundancy, a selector arrangement is typically connected between the Tina assemblies and external transmission lines, which arrangement can 2 5 distribute individual transmission lines to the N lines assemblies and tn the backup line assemhly_ Hut it must be nosed that, when a selector arrangement such as this fails, or respectively, in a resulting replacement of this selector arrangement, all the transmission tines that are connected to it are interrupted, along, with the caruieetions running via these lines.
MAR-1T-00 OA:56 CA 02303895 2000-03-17 P.16 R-417 Job-654 MAR. -17' OOfFRl1 09:52 HILL S'fEADMAN P. 016 l3eyorid this, it is mentioned in the cited document that a transfer logic arrangement (LPS: Line Protection Switch) is connected on the output side of the communication device between the coupling field and the line assemblies, in order to be able to selectively realize the abovementioned redundancy structures. But more detailed information about the mode of functioning and the reali~alion of this transfer logic arrangement is not given.
The US patent US 5,331,631 teaches a device with redundancy structure far trnasmitting message cells, The US patent 5,473,598 likewise teaches a redundancy structure for telecommunication systems. In both refercncca, modifications are made to the routing informaliori In case of a backup changeover.
It is the object of the itlvention to demonstrate how to construct the transfer logic an-angement that belongs to a communication device according to tl~ preamble of patent claim 1 such that arbitrary redundancy structures can be realized with a low outlay in terms of control technology and circuitry.
This object is inventively achieved in a communication device according to the patent claim 1 by the wiring features cited in this claim.
The invention imparts the advantage th..~t redundancy structures can be universally realized on the basis of the development of the transfer logic anastgement, wi lhout having to access redundancy-specific elements.
2 5 Advantageous developments of the invention derive from the subclclims.
'1 he present invention is detailed below with the aid of drawings. These drawings illustrate only those elements which are necessary in order to gain an understanding y the present invention.
MAR-1~-00 OB:56 CA 02303895 2000-03-l7PVt R-417 Job-B54 MAR. -17' OOfFRI) 09:53 HILL STEADMAN P. 017- -_-2a Figure 1 sectional diagram of the schematic: structure c~f a communication device according to the invention, Figure 2 sectional diabram of the schematic sri-ucture of a cou~lirtg element that is detailed balow, and LIAR-1P-00 09:56 CA 02303895 2000-03-17 P.05 R-417 Job-854 MAR. -17' 00 (FR I ) 09 : 50 H 1 LL STEADMAN P. 005 Figure 3 the schematic structure of a control device that is provided in the coupling element illustrated in Figure 2.
The conununication device KE illustrated in Figure 1 is a matter of ATM
communications equipment that functions in accordance with asynchronous transfer mode, enabling the transmission of message signals in the form of message ells in the course of virtual connections. Since the ATM principle and the general structure of message cells have long been known, these are not detailed here. It is merely noted here that the messrlge cells appertaixling to a virtual connection have an information part ("user purl") and a cell header ("header") at their disposal, respectively. Among other things, a cell header like this contains what is known as a virtual channel nta.mber VCI, which references the respective viral al c:c~nncction, and potentially what is knovm as a virtual path number VP1, a routing address that applies to the reslaecaive virtual connection, and what is known as housekeeping inlorrnation, as well.
The communication device ICE cortlprises a central coupling field ASN, which has at its disposal a central coupling arrangement ASN-C (ASN Core) with an appertaining coupling awangemerit control ASN-CC, and at least one ATM multiplexes AMX that is connected to the coupling arrangement. This ATM multiplexes comprises a 2 0 separate control, referenced AMX-C.
The communication device KE can be a matter of what is known as a crow connect for settills up virtual permanent connections, or a switching node for setting up virtual dial connections. In either case, the set-up of the connections is accomplished with 2 5 the aid of said coupling atTangament control ASN-CC and of the control AMX-C.
However, since this process of settin6 up virtual connections is not subject mater of the present invention, it 1s not discussed in greater detail hers.
IyIAR-1'7-00 OA:56 CA 02303895 2000-03-17 P.06 R-417 Job-854 MAR. -17' 00(FRI~ 09:50 HILL S'fEADMAN P. 006 In the present exemplifying embodimwt, a plurality of line assemblies are connected to the central coupling arrangement ASN via the ATM multihlexer AMX, via bidirectional electrical connections, for example. As illustrated im Figure 1.
the ATM
multiplexes can be designed for connecting 16 line assemblies, which arc referenced L1C AO to LIC A15. These line assemblies are provided far connecting at least one peripheral transmission line, respectively. The transmission lines, which may be designed for a bidirectional transmission of message sign..~ls, are referenced A1 to A15, according to their allocation to the line assemblies.
1 D Incidentally, it should be noted that a plurality of ATM multiPlexers AMX
can also be connected to the central coupling arrangement ASN-C, depending un the required size of the coxmnunication device KE.
The ATM multiplexes AMX illustrated in rigure 1 comprises at Icast one scpa.race coupling element Sir for each direction of the transmission, which elements have a structure 16116 in the present exentpli Eying embodiment; that is, they have 16 inputs and 16 outputs at their disposal. These coupling elements are controlled by the control AMX-C of the ATM multiplexes AMX. An gong other things, the control consists in the specifying of a particular connection path via the respective coupling 2 0 element i» the course of the sat-up of virtual connections. As previously mentioned, for such an established connection path, a Specific routing address is contained in the toll header of the individual messa6e culls, in order to make it possible to route the respective message cell vin the relevant coupling element S); on the correct connection according to the speciFcation5 of this routing address.
As is described in detail below, control means are provided at least in the respective coupling element that is provided in the outgoing direction of transmission (that is, from the ATM multiplexes AMX to the line assemblies LIC AU to LIC A15), so that, whzn one of the line assemblies fails, a backup path via the respective coupling MAR-17-00 09:56 CA 02303895 2000-03-17 P.07 R-417 Job-954 MAR. -17' QO (FRI l 09:50 HILL STEADMAN P. 007 s element is selected according tp a specific redundancy structure, without it being necessary to change the routing address that is contained in the message cells that are to be transmitted via the backup path.
Figure 2 is a sectional illustration tit the schematic Structure of a coupling element SE
for the outgoing direction of transmission, The backup switching principle just described is detailed with the aid of this 1~igure and rigure 3.
According to rigure ?, the illusWated coupling element SE, and every other coupling l0 element, comprises a central cell memory ZP, in which the message cells that are to be routed via the line assemblies 1.IC AO to LIC A15 arc temporarily stored.
Beyond this, the line assemblies LIC AO to LIC A15 are each assi6ned an individual logical queue, these being referenced QO to Q15 according to their allocation to the individual line assemblies. These logical queues can be controlled individually accordin6 to the routing addresses contained in the me;;sage cells, and they serve for the temporary storage of address pointers, by means of which it is respectively indicated wheue irt the cell memory ZF the message cells that are to be routed via the allocated line assembly are respectively stored. These address pnint~rs are made available by the cell buffer ZP.
The logical queues QO to Q l 5 are processed - for W stance, by a scanner (which i s not illustrated) -. cyclically in succession in a definite order, whereby one address pointer is extracted from each of the queues per cycle. Within the respective queue, the entered address poipters are read out in accordance with the FIFO principle.
The 2 5 address pointers that are loaded by the cell memory ZP are entered into the queues in question with the aid of a queue control QC. For this purpose, with ei~ch arrival of a message cell, this control is supplied art least with the part of the appertainins cell header in which the abovementioned routing address RIB (Figure 2) is contained_ MAR-17-00 09:56 CA 02303895 2000-03-17 P.OB R-41T Job-854 MAR. -17' 00(FRI) 09:51 HILL STEADMAN P. 008 s With the aid of this header, the queue into which the address pointer just loaded is to be entered is determined.
The above described controlling of the logical queues by the queue control QC:
is discussed below in detail with the aid of Figure 3.
The central part of the queue control QC is formed by a transfer logic arrangement LPS, by paeans of which one ar mare arbitrary queues o f the queues QO to Q
15, and thus one or more line assemblies LTC: AO to LIC A15, can be randomly allocated to l0 each routing address RA. For this purpose, a register is kept in the transfer logic arrangement LPS For every routing address possibly contained in the message cells.
In each of these registers, a separate bit position is reserved for each of the queues t)0 to Q15; that is, in the given example, there are 16 bit posifiona provided per regicter_ The queue into which the address pointer that has been detected for a message cell is 7.5 to be entered during the storing ofthis cell is indicated by a specifizd logic level, 'for instance "1 ", in one or more bit positions of a register. By contrast, a logic level "U"
signifies that the allocated queue is blocked.
The individual registers can be individually controlled at lzast according to the 2 0 abovementioned routing addresses RA. which are contained in the respective message cells. The controlling is accomplished with the aid of a control logic arrangement (which is referenced QA in Figure 3), to which the routing address that is contained in the appertaining cell header is delivered with each arrival of a message cell.
2 5 Furthermore. the register contents of the transfer logic arrangement LPS
arc preloaded jointly by the control unit AMX-C iliustratea in Figure 1 (which process is not illustrated) when the communication device ICE is initialized (Figure 1), or they arc modified individually if necessary; that is, in a backup switching process as described above, for example.
MAR-'.T-DO 09:56 CA 02303895 2000-03-17 P.09 R-41T Job-B54 MAR. -17' DO (FRI ) 09: 51 HI LL STEADMAN P. 009 It is illustrated again in rigure 3 that the individual queues QO to Q15 can bz controlled individually by tLie transfer logic arrangement LPS in accordance with said register contents, in order to pick up the aforesaid address pointers for message cells that are stored in the cell buffar ZP (Figure 2).
The basic method of functioning of the devices illustrated in the Figures 1 to ~ having been hereby described, it is now explained hnw the abovementioned various redundancy structures can be realised with the aid of the cited register contents of the conversion arrangement LPS.
In a system without assembly redundancy, a system with a "1:1" assemhly redundancy, or a system with a "1:N" assembly redundancy, the queue (QO In Q15) that is to be used for picking up an address pointer currently being made available, and thus ultimately the Iine assembly LIC AO to LIC; A15 via which the message call 25 that is allocated to the relevant address pointer is tc~ be routed, is respectively indicated in the registers of the changeover logic an-angr:ment LPS by a logical " 1 " at one of the bit positions only. The other bit positions of the individual registers are set to the logic level "0"
2 o When it is necessary to perform a backup changeover of a faulty line assembly (LIC
t10 to LIC A15), which assembly is identified by a specific routing address, it is merely necessary to provide the previously marked bit position in the register, which is allocated to this muting address, of the ch~rtgeover arrangement LPS with a logic level "0", and to mark a bit position that pertains to the backup switching process whiz 25 a logic level "1" instead.
When a "1+1" assembly redundancy is required, two - for instance, adjacent J
bit positions in the registers of the changeover logic at-rangement LPS are set to the logic level "1", respectively, in order to thereby mark the queues that are allocated to these MAR-1?-00 09:56 CA 02303895 2000-03-17 P.10 R-417 Job-B54 MAR. -17' 00 iFR I ) 09 : S 1 H I LL STEADMAN P. 010 a two bit positions as activated. This means that, with said storing of a message cell in the cell memory ZP (Figure 3), the address pointer that is allocated to the message cell being stored is simultaneously entered into both of the clueues that are designated active.
In addition to the realization just described of diflerern redundancy structures with the aid of specific register contents of the changeover logic arrangement LPS, a broadcasting can also be realized in that a logic level "1" are [sic] entered into all bit positions of the register, respectively. The result of this is that all of the message cells 1o that are delivered by the coupling arrangement ASN are routed to all line assemblies (LIC AO to L1C A15).
As mentioned above, besides a muting address, the cell headers of the message cells respectively contain what is known as housekeeping information, among other things.
s5 Acnong other things, this housekeeping infontiation indicates the type of the respective message cell; that is, whether the respentivc message cell is a matter of a normal payload cell, or respectively, a connection-speci fic control cell, or it is a matter of a system-specific control cell. In this exemplifying ernboditnent, in order to be able to detect these cell types when a message cell occurs, a czll filter FIL 1s 2 o provided in the control logic arrangement LPS or is connected to the control logic atTarlgement LPS upstream. This cell filter is passed by the housekeeping information of received message cells, and the detected cell type is indicated. In accordance with the respectively detected cell type, only tiortrtal payload cells, or respectively, connection-specific control cells, arc routed according to the specifications of the 25 register contents ofthc control logic arrangement LPS. 13y contrast, system-specific control cells are forwarded without modifiication o!' ihc respective original connection path as characterized by a particular routing address. This can be accomplished in that, for example, the information (address pointer) that is required for the routing of such a control cell is entered directly into the required queue.
The invention relates to a communication device according to the preamble of patent claim 1.
Depending on the fault tolerance required of a cummLtnicatiun device. di fferent redundancy structures can bee [sic] provided for the peripheral line assemblies belonging thereto. Examples of this are the "1+1", "1:1", and "1:N" types of line assembly redundancy, as is described in "IEEE .Tournal on Selected Areas in Communications" (Vol. 15, N. 5, Juna 1997, pp. 795-B06). In a "1+1" redundancy structuxe, two line assemblies are operated in parallel, in order to transmit message signal currents over them redundantly. But only one of these redundant message signal currents is considered for further processing.
In a "1-r-1 " line assembly redundancy, only 'one of two line assemblies is used as the active line assembly, while a changeover onto the ether line assembly, which serves as a back-up assembly, occurs only in case of a failure of the active line assembly.
Finally, in a "1:N" line assembly redundancy, in ~iclditiori to a plurality N
of line 2 o assemblies, a single backup line assembly is provided. When a failure occurs on one of the N line assemblies, the backup line assembly is then used instead.
In a "1:N" line assembly redundancy, a selector arrangement is typically connected between the Tina assemblies and external transmission lines, which arrangement can 2 5 distribute individual transmission lines to the N lines assemblies and tn the backup line assemhly_ Hut it must be nosed that, when a selector arrangement such as this fails, or respectively, in a resulting replacement of this selector arrangement, all the transmission tines that are connected to it are interrupted, along, with the caruieetions running via these lines.
MAR-1T-00 OA:56 CA 02303895 2000-03-17 P.16 R-417 Job-654 MAR. -17' OOfFRl1 09:52 HILL S'fEADMAN P. 016 l3eyorid this, it is mentioned in the cited document that a transfer logic arrangement (LPS: Line Protection Switch) is connected on the output side of the communication device between the coupling field and the line assemblies, in order to be able to selectively realize the abovementioned redundancy structures. But more detailed information about the mode of functioning and the reali~alion of this transfer logic arrangement is not given.
The US patent US 5,331,631 teaches a device with redundancy structure far trnasmitting message cells, The US patent 5,473,598 likewise teaches a redundancy structure for telecommunication systems. In both refercncca, modifications are made to the routing informaliori In case of a backup changeover.
It is the object of the itlvention to demonstrate how to construct the transfer logic an-angement that belongs to a communication device according to tl~ preamble of patent claim 1 such that arbitrary redundancy structures can be realized with a low outlay in terms of control technology and circuitry.
This object is inventively achieved in a communication device according to the patent claim 1 by the wiring features cited in this claim.
The invention imparts the advantage th..~t redundancy structures can be universally realized on the basis of the development of the transfer logic anastgement, wi lhout having to access redundancy-specific elements.
2 5 Advantageous developments of the invention derive from the subclclims.
'1 he present invention is detailed below with the aid of drawings. These drawings illustrate only those elements which are necessary in order to gain an understanding y the present invention.
MAR-1~-00 OB:56 CA 02303895 2000-03-l7PVt R-417 Job-B54 MAR. -17' OOfFRI) 09:53 HILL STEADMAN P. 017- -_-2a Figure 1 sectional diagram of the schematic: structure c~f a communication device according to the invention, Figure 2 sectional diabram of the schematic sri-ucture of a cou~lirtg element that is detailed balow, and LIAR-1P-00 09:56 CA 02303895 2000-03-17 P.05 R-417 Job-854 MAR. -17' 00 (FR I ) 09 : 50 H 1 LL STEADMAN P. 005 Figure 3 the schematic structure of a control device that is provided in the coupling element illustrated in Figure 2.
The conununication device KE illustrated in Figure 1 is a matter of ATM
communications equipment that functions in accordance with asynchronous transfer mode, enabling the transmission of message signals in the form of message ells in the course of virtual connections. Since the ATM principle and the general structure of message cells have long been known, these are not detailed here. It is merely noted here that the messrlge cells appertaixling to a virtual connection have an information part ("user purl") and a cell header ("header") at their disposal, respectively. Among other things, a cell header like this contains what is known as a virtual channel nta.mber VCI, which references the respective viral al c:c~nncction, and potentially what is knovm as a virtual path number VP1, a routing address that applies to the reslaecaive virtual connection, and what is known as housekeeping inlorrnation, as well.
The communication device ICE cortlprises a central coupling field ASN, which has at its disposal a central coupling arrangement ASN-C (ASN Core) with an appertaining coupling awangemerit control ASN-CC, and at least one ATM multiplexes AMX that is connected to the coupling arrangement. This ATM multiplexes comprises a 2 0 separate control, referenced AMX-C.
The communication device KE can be a matter of what is known as a crow connect for settills up virtual permanent connections, or a switching node for setting up virtual dial connections. In either case, the set-up of the connections is accomplished with 2 5 the aid of said coupling atTangament control ASN-CC and of the control AMX-C.
However, since this process of settin6 up virtual connections is not subject mater of the present invention, it 1s not discussed in greater detail hers.
IyIAR-1'7-00 OA:56 CA 02303895 2000-03-17 P.06 R-417 Job-854 MAR. -17' 00(FRI~ 09:50 HILL S'fEADMAN P. 006 In the present exemplifying embodimwt, a plurality of line assemblies are connected to the central coupling arrangement ASN via the ATM multihlexer AMX, via bidirectional electrical connections, for example. As illustrated im Figure 1.
the ATM
multiplexes can be designed for connecting 16 line assemblies, which arc referenced L1C AO to LIC A15. These line assemblies are provided far connecting at least one peripheral transmission line, respectively. The transmission lines, which may be designed for a bidirectional transmission of message sign..~ls, are referenced A1 to A15, according to their allocation to the line assemblies.
1 D Incidentally, it should be noted that a plurality of ATM multiPlexers AMX
can also be connected to the central coupling arrangement ASN-C, depending un the required size of the coxmnunication device KE.
The ATM multiplexes AMX illustrated in rigure 1 comprises at Icast one scpa.race coupling element Sir for each direction of the transmission, which elements have a structure 16116 in the present exentpli Eying embodiment; that is, they have 16 inputs and 16 outputs at their disposal. These coupling elements are controlled by the control AMX-C of the ATM multiplexes AMX. An gong other things, the control consists in the specifying of a particular connection path via the respective coupling 2 0 element i» the course of the sat-up of virtual connections. As previously mentioned, for such an established connection path, a Specific routing address is contained in the toll header of the individual messa6e culls, in order to make it possible to route the respective message cell vin the relevant coupling element S); on the correct connection according to the speciFcation5 of this routing address.
As is described in detail below, control means are provided at least in the respective coupling element that is provided in the outgoing direction of transmission (that is, from the ATM multiplexes AMX to the line assemblies LIC AU to LIC A15), so that, whzn one of the line assemblies fails, a backup path via the respective coupling MAR-17-00 09:56 CA 02303895 2000-03-17 P.07 R-417 Job-954 MAR. -17' QO (FRI l 09:50 HILL STEADMAN P. 007 s element is selected according tp a specific redundancy structure, without it being necessary to change the routing address that is contained in the message cells that are to be transmitted via the backup path.
Figure 2 is a sectional illustration tit the schematic Structure of a coupling element SE
for the outgoing direction of transmission, The backup switching principle just described is detailed with the aid of this 1~igure and rigure 3.
According to rigure ?, the illusWated coupling element SE, and every other coupling l0 element, comprises a central cell memory ZP, in which the message cells that are to be routed via the line assemblies 1.IC AO to LIC A15 arc temporarily stored.
Beyond this, the line assemblies LIC AO to LIC A15 are each assi6ned an individual logical queue, these being referenced QO to Q15 according to their allocation to the individual line assemblies. These logical queues can be controlled individually accordin6 to the routing addresses contained in the me;;sage cells, and they serve for the temporary storage of address pointers, by means of which it is respectively indicated wheue irt the cell memory ZF the message cells that are to be routed via the allocated line assembly are respectively stored. These address pnint~rs are made available by the cell buffer ZP.
The logical queues QO to Q l 5 are processed - for W stance, by a scanner (which i s not illustrated) -. cyclically in succession in a definite order, whereby one address pointer is extracted from each of the queues per cycle. Within the respective queue, the entered address poipters are read out in accordance with the FIFO principle.
The 2 5 address pointers that are loaded by the cell memory ZP are entered into the queues in question with the aid of a queue control QC. For this purpose, with ei~ch arrival of a message cell, this control is supplied art least with the part of the appertainins cell header in which the abovementioned routing address RIB (Figure 2) is contained_ MAR-17-00 09:56 CA 02303895 2000-03-17 P.OB R-41T Job-854 MAR. -17' 00(FRI) 09:51 HILL STEADMAN P. 008 s With the aid of this header, the queue into which the address pointer just loaded is to be entered is determined.
The above described controlling of the logical queues by the queue control QC:
is discussed below in detail with the aid of Figure 3.
The central part of the queue control QC is formed by a transfer logic arrangement LPS, by paeans of which one ar mare arbitrary queues o f the queues QO to Q
15, and thus one or more line assemblies LTC: AO to LIC A15, can be randomly allocated to l0 each routing address RA. For this purpose, a register is kept in the transfer logic arrangement LPS For every routing address possibly contained in the message cells.
In each of these registers, a separate bit position is reserved for each of the queues t)0 to Q15; that is, in the given example, there are 16 bit posifiona provided per regicter_ The queue into which the address pointer that has been detected for a message cell is 7.5 to be entered during the storing ofthis cell is indicated by a specifizd logic level, 'for instance "1 ", in one or more bit positions of a register. By contrast, a logic level "U"
signifies that the allocated queue is blocked.
The individual registers can be individually controlled at lzast according to the 2 0 abovementioned routing addresses RA. which are contained in the respective message cells. The controlling is accomplished with the aid of a control logic arrangement (which is referenced QA in Figure 3), to which the routing address that is contained in the appertaining cell header is delivered with each arrival of a message cell.
2 5 Furthermore. the register contents of the transfer logic arrangement LPS
arc preloaded jointly by the control unit AMX-C iliustratea in Figure 1 (which process is not illustrated) when the communication device ICE is initialized (Figure 1), or they arc modified individually if necessary; that is, in a backup switching process as described above, for example.
MAR-'.T-DO 09:56 CA 02303895 2000-03-17 P.09 R-41T Job-B54 MAR. -17' DO (FRI ) 09: 51 HI LL STEADMAN P. 009 It is illustrated again in rigure 3 that the individual queues QO to Q15 can bz controlled individually by tLie transfer logic arrangement LPS in accordance with said register contents, in order to pick up the aforesaid address pointers for message cells that are stored in the cell buffar ZP (Figure 2).
The basic method of functioning of the devices illustrated in the Figures 1 to ~ having been hereby described, it is now explained hnw the abovementioned various redundancy structures can be realised with the aid of the cited register contents of the conversion arrangement LPS.
In a system without assembly redundancy, a system with a "1:1" assemhly redundancy, or a system with a "1:N" assembly redundancy, the queue (QO In Q15) that is to be used for picking up an address pointer currently being made available, and thus ultimately the Iine assembly LIC AO to LIC; A15 via which the message call 25 that is allocated to the relevant address pointer is tc~ be routed, is respectively indicated in the registers of the changeover logic an-angr:ment LPS by a logical " 1 " at one of the bit positions only. The other bit positions of the individual registers are set to the logic level "0"
2 o When it is necessary to perform a backup changeover of a faulty line assembly (LIC
t10 to LIC A15), which assembly is identified by a specific routing address, it is merely necessary to provide the previously marked bit position in the register, which is allocated to this muting address, of the ch~rtgeover arrangement LPS with a logic level "0", and to mark a bit position that pertains to the backup switching process whiz 25 a logic level "1" instead.
When a "1+1" assembly redundancy is required, two - for instance, adjacent J
bit positions in the registers of the changeover logic at-rangement LPS are set to the logic level "1", respectively, in order to thereby mark the queues that are allocated to these MAR-1?-00 09:56 CA 02303895 2000-03-17 P.10 R-417 Job-B54 MAR. -17' 00 iFR I ) 09 : S 1 H I LL STEADMAN P. 010 a two bit positions as activated. This means that, with said storing of a message cell in the cell memory ZP (Figure 3), the address pointer that is allocated to the message cell being stored is simultaneously entered into both of the clueues that are designated active.
In addition to the realization just described of diflerern redundancy structures with the aid of specific register contents of the changeover logic arrangement LPS, a broadcasting can also be realized in that a logic level "1" are [sic] entered into all bit positions of the register, respectively. The result of this is that all of the message cells 1o that are delivered by the coupling arrangement ASN are routed to all line assemblies (LIC AO to L1C A15).
As mentioned above, besides a muting address, the cell headers of the message cells respectively contain what is known as housekeeping information, among other things.
s5 Acnong other things, this housekeeping infontiation indicates the type of the respective message cell; that is, whether the respentivc message cell is a matter of a normal payload cell, or respectively, a connection-speci fic control cell, or it is a matter of a system-specific control cell. In this exemplifying ernboditnent, in order to be able to detect these cell types when a message cell occurs, a czll filter FIL 1s 2 o provided in the control logic arrangement LPS or is connected to the control logic atTarlgement LPS upstream. This cell filter is passed by the housekeeping information of received message cells, and the detected cell type is indicated. In accordance with the respectively detected cell type, only tiortrtal payload cells, or respectively, connection-specific control cells, arc routed according to the specifications of the 25 register contents ofthc control logic arrangement LPS. 13y contrast, system-specific control cells are forwarded without modifiication o!' ihc respective original connection path as characterized by a particular routing address. This can be accomplished in that, for example, the information (address pointer) that is required for the routing of such a control cell is entered directly into the required queue.
Claims
1. Communication device (KE) for transmitting message cells, each of which has routing information at its disposal, having a coupling arrangement (ASN) and having line assemblies (LIC A0...LIC A15) that are allocated thereto, which are respectively connected to at least one transmission line (A0 to A15); whereby, at least in the outgoing direction of transmission, a changeover arrangement (LPS) is provided in the coupling arrangement (ASN) and is connected in series to the line assemblies, characterized in that the changeover logic arrangement (LPS) has storage means at its disposal, which have a number of register cells corresponding to the number of possible different items routing information, and which can be individually controlled, on the basis of the individual items of routing information, for the purpose of delivering selection information that is respectively stored in the register cells;
that the rousing of message cells to the line assemblies is controlled in accordance with the selection information made available by the register cells, instead of the routing information;
and that the selection information stored in the register cells can be individually modified.
that the rousing of message cells to the line assemblies is controlled in accordance with the selection information made available by the register cells, instead of the routing information;
and that the selection information stored in the register cells can be individually modified.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19741431.1 | 1997-09-19 | ||
| DE19741431A DE19741431A1 (en) | 1997-09-19 | 1997-09-19 | Communication device for transmission of routing information in ATM system |
| PCT/DE1998/002778 WO1999016216A1 (en) | 1997-09-19 | 1998-09-18 | Communication device to transmit message signals |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2303895A1 true CA2303895A1 (en) | 1999-04-01 |
Family
ID=7842977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002303895A Abandoned CA2303895A1 (en) | 1997-09-19 | 1998-09-18 | Communication device for transmitting message signals |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1016249A1 (en) |
| CA (1) | CA2303895A1 (en) |
| DE (1) | DE19741431A1 (en) |
| WO (1) | WO1999016216A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10140044A1 (en) * | 2001-08-16 | 2003-03-06 | Siemens Ag | Bus connection priority system for automatic control assigns priorities to all possible links |
| US7215664B2 (en) | 2001-11-01 | 2007-05-08 | Telefonaktiebolaget Lm Ericsson (Publ) | Arrangement and method for protection switching |
| EP1309136A1 (en) * | 2001-11-01 | 2003-05-07 | TELEFONAKTIEBOLAGET LM ERICSSON (publ) | Arrangement and method for protection switching |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3107216B2 (en) * | 1990-08-17 | 2000-11-06 | 株式会社日立製作所 | Routing method and non-stop table change method |
| US5229990A (en) * | 1990-10-03 | 1993-07-20 | At&T Bell Laboratories | N+K sparing in a telecommunications switching environment |
| US5327552A (en) * | 1992-06-22 | 1994-07-05 | Bell Communications Research, Inc. | Method and system for correcting routing errors due to packet deflections |
| JP3095314B2 (en) * | 1993-08-31 | 2000-10-03 | 株式会社日立製作所 | Path switching method |
-
1997
- 1997-09-19 DE DE19741431A patent/DE19741431A1/en not_active Withdrawn
-
1998
- 1998-09-18 WO PCT/DE1998/002778 patent/WO1999016216A1/en not_active Ceased
- 1998-09-18 CA CA002303895A patent/CA2303895A1/en not_active Abandoned
- 1998-09-18 EP EP98956780A patent/EP1016249A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| DE19741431A1 (en) | 1999-03-25 |
| EP1016249A1 (en) | 2000-07-05 |
| WO1999016216A1 (en) | 1999-04-01 |
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