CA2774482C - Circuit d'echantillonnage de donnees et procede de recuperation d'horloge et de donnees - Google Patents

Circuit d'echantillonnage de donnees et procede de recuperation d'horloge et de donnees Download PDF

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Publication number
CA2774482C
CA2774482C CA2774482A CA2774482A CA2774482C CA 2774482 C CA2774482 C CA 2774482C CA 2774482 A CA2774482 A CA 2774482A CA 2774482 A CA2774482 A CA 2774482A CA 2774482 C CA2774482 C CA 2774482C
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CA
Canada
Prior art keywords
signal
circuit
delay
data
preselected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CA2774482A
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English (en)
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CA2774482A1 (fr
Inventor
Wilhelm C. Fischer
David A. Inglis
Yusuke Ota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZENKO TECHNOLOGIES Inc
Original Assignee
ZENKO TECHNOLOGIES Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by ZENKO TECHNOLOGIES Inc filed Critical ZENKO TECHNOLOGIES Inc
Publication of CA2774482A1 publication Critical patent/CA2774482A1/fr
Application granted granted Critical
Publication of CA2774482C publication Critical patent/CA2774482C/fr
Active legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Linvention concerne un circuit et un procédé de récupération d'horloge et de données qui sont utilisés dans un système de communications de données numériques. Le circuit et le procédé sont employés de manière efficace pour une transmission haut débit, en mode rafale, et permettent une récupération rapide des signaux d'horloge et de données sans nécessiter un en-tête étendu, et indépendamment de la présence d'une instabilité de temporisation substantielle. Le procédé choisit de manière adaptative parmi trois temps de retard pour l'extraction de données par lidentification d'un motif d'entrée à récurrence fréquente dans les données entrantes. Le temps de retard est sélectionné d'une manière qui assure que le même motif est présent dans les données de sortie reconstruites, re-synchronisées.
CA2774482A 2008-10-02 2008-10-02 Circuit d'echantillonnage de donnees et procede de recuperation d'horloge et de donnees Active CA2774482C (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2008/011416 WO2010039108A1 (fr) 2008-10-02 2008-10-02 Circuit d'échantillonnage de données et procédé de récupération d'horloge et de données

Publications (2)

Publication Number Publication Date
CA2774482A1 CA2774482A1 (fr) 2010-04-08
CA2774482C true CA2774482C (fr) 2015-12-01

Family

ID=42073727

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2774482A Active CA2774482C (fr) 2008-10-02 2008-10-02 Circuit d'echantillonnage de donnees et procede de recuperation d'horloge et de donnees

Country Status (3)

Country Link
EP (1) EP2335374A4 (fr)
CA (1) CA2774482C (fr)
WO (1) WO2010039108A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8724764B2 (en) * 2012-05-30 2014-05-13 Xilinx, Inc. Distortion tolerant clock and data recovery
US9274545B2 (en) 2013-10-24 2016-03-01 Globalfoundries Inc. Apparatus and method to recover a data signal
CN113886315B (zh) * 2021-09-23 2024-05-03 珠海一微半导体股份有限公司 一种时钟数据恢复系统、芯片及时钟数据恢复方法
CN117917873B (zh) * 2023-12-25 2025-07-11 深圳市聚亿芯电子有限公司 光时钟恢复系统及方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4486739A (en) 1982-06-30 1984-12-04 International Business Machines Corporation Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code
EP1061691A3 (fr) * 1999-06-15 2005-05-25 Matsushita Electric Industrial Co., Ltd. Circuit PLL digital pour données en mode rafale et circuit de réception optique utilisant ce dernier
US20020085656A1 (en) * 2000-08-30 2002-07-04 Lee Sang-Hyun Data recovery using data eye tracking
US7642566B2 (en) * 2006-06-12 2010-01-05 Dsm Solutions, Inc. Scalable process and structure of JFET for small and decreasing line widths
WO2006011830A2 (fr) * 2004-07-20 2006-02-02 Igor Anatolievich Abrosimov Circuit resynchroniseur de recuperation de donnees a recuperation rapide a partir d'un mode faible puissance
US7873132B2 (en) * 2005-09-21 2011-01-18 Hewlett-Packard Development Company, L.P. Clock recovery
US7983368B2 (en) * 2006-12-11 2011-07-19 International Business Machines Corporation Systems and arrangements for clock and data recovery in communications
TW200835178A (en) * 2007-02-02 2008-08-16 Smedia Technology Corp Multi-sampling data recovery circuit and method applicable to receiver

Also Published As

Publication number Publication date
EP2335374A1 (fr) 2011-06-22
EP2335374A4 (fr) 2012-03-28
CA2774482A1 (fr) 2010-04-08
WO2010039108A1 (fr) 2010-04-08

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