CA2807739C - Methode de test de memoire otp non programmee - Google Patents

Methode de test de memoire otp non programmee Download PDF

Info

Publication number
CA2807739C
CA2807739C CA2807739A CA2807739A CA2807739C CA 2807739 C CA2807739 C CA 2807739C CA 2807739 A CA2807739 A CA 2807739A CA 2807739 A CA2807739 A CA 2807739A CA 2807739 C CA2807739 C CA 2807739C
Authority
CA
Canada
Prior art keywords
bitline
voltage
fuse
memory cell
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CA2807739A
Other languages
English (en)
Other versions
CA2807739A1 (fr
Inventor
Wlodek Kurjanowicz
Steven Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Synopsys Inc
Original Assignee
Sidense Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/412,500 external-priority patent/US8767433B2/en
Application filed by Sidense Corp filed Critical Sidense Corp
Publication of CA2807739A1 publication Critical patent/CA2807739A1/fr
Application granted granted Critical
Publication of CA2807739C publication Critical patent/CA2807739C/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM

Landscapes

  • Semiconductor Memories (AREA)

Abstract

Des procédés d'essai de cellules de mémoire anti-fusibles à un seul transistor et à deux transistors non programmées qui consistent à tester les connexions des cellules à une ligne de bit en comparant une caractéristique de tension d'une ligne de bit connectée à la cellule sous essai à celle d'une ligne de bit de référence ayant une caractéristique de tension prédéterminée. Certains procédés peuvent utiliser des cellules d'essai comprenant un transistor d'accès configuré d'une manière identique au transistor d'accès d'une cellule de mémoire normale, mais omettant le dispositif anti-fusible présent dans la cellule de mémoire normale, pour tester la présence d'une connexion de la cellule de mémoire normale à la ligne de bit. Une telle cellule d'essai peut être utilisée dans un essai supplémentaire pour déterminer le niveau de couplage capacitif de la tension de ligne de mot aux lignes de bit par rapport à celui d'une cellule de mémoire normale sous essai.
CA2807739A 2012-03-05 2013-03-01 Methode de test de memoire otp non programmee Active CA2807739C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/412,500 US8767433B2 (en) 2004-05-06 2012-03-05 Methods for testing unprogrammed OTP memory
US13/412,500 2012-03-05

Publications (2)

Publication Number Publication Date
CA2807739A1 CA2807739A1 (fr) 2013-05-08
CA2807739C true CA2807739C (fr) 2014-01-21

Family

ID=48239884

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2807739A Active CA2807739C (fr) 2012-03-05 2013-03-01 Methode de test de memoire otp non programmee

Country Status (2)

Country Link
CA (1) CA2807739C (fr)
WO (1) WO2013131185A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017058111A1 (fr) * 2015-09-28 2017-04-06 Agency For Science, Technology And Research Procédé de détection d'erreur dans un dispositif de mémoire vive magnétique à champ électrique oscillant (tef-ram), et dispositif tef-ram
US9959912B2 (en) 2016-02-02 2018-05-01 Qualcomm Incorporated Timed sense amplifier circuits and methods in a semiconductor memory
KR102384161B1 (ko) * 2017-08-24 2022-04-08 삼성전자주식회사 비트 라인 누설 전류에 의한 읽기 페일을 방지하도록 구성되는 메모리 장치 및 그 동작 방법
US11177010B1 (en) * 2020-07-13 2021-11-16 Qualcomm Incorporated Bitcell for data redundancy
JP7406467B2 (ja) * 2020-07-30 2023-12-27 ルネサスエレクトロニクス株式会社 半導体装置
CN112798940A (zh) * 2021-03-19 2021-05-14 普冉半导体(上海)股份有限公司 一种芯片测试筛选方法
KR20250105295A (ko) * 2023-12-29 2025-07-08 씨엑스엠티 코포레이션 메모리 및 그 제어 방법, 전자 기기

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7511982B2 (en) * 2004-05-06 2009-03-31 Sidense Corp. High speed OTP sensing scheme
US8059479B2 (en) * 2008-04-03 2011-11-15 Sidense Corp. Test circuit for an unprogrammed OTP memory array

Also Published As

Publication number Publication date
WO2013131185A1 (fr) 2013-09-12
CA2807739A1 (fr) 2013-05-08

Similar Documents

Publication Publication Date Title
CA2578837C (fr) Detection du procede de chiffrement vernam a haute vitesse
US8767433B2 (en) Methods for testing unprogrammed OTP memory
CA2520140C (fr) Architecture de reseau anti-fusion a canal dedouble
EP2165369B1 (fr) Cellule de mémoire anti-fusible
US9123572B2 (en) Anti-fuse memory cell
CA2887223C (fr) Cellule memoire anti-fusion
CA2807739C (fr) Methode de test de memoire otp non programmee

Legal Events

Date Code Title Description
MPN Maintenance fee for patent paid

Free format text: FEE DESCRIPTION TEXT: MF (PATENT, 12TH ANNIV.) - STANDARD

Year of fee payment: 12

U00 Fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U00-U101 (AS PROVIDED BY THE NATIONAL OFFICE); EVENT TEXT: MAINTENANCE REQUEST RECEIVED

Effective date: 20250220

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-U102 (AS PROVIDED BY THE NATIONAL OFFICE); EVENT TEXT: MAINTENANCE FEE PAYMENT DETERMINED COMPLIANT

Effective date: 20250220

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-U102 (AS PROVIDED BY THE NATIONAL OFFICE); EVENT TEXT: MAINTENANCE FEE PAYMENT PAID IN FULL

Effective date: 20250220

MPN Maintenance fee for patent paid

Free format text: FEE DESCRIPTION TEXT: MF (PATENT, 13TH ANNIV.) - STANDARD

Year of fee payment: 13

U00 Fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U00-U101 (AS PROVIDED BY THE NATIONAL OFFICE); EVENT TEXT: MAINTENANCE REQUEST RECEIVED

Effective date: 20260219

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-U102 (AS PROVIDED BY THE NATIONAL OFFICE); EVENT TEXT: MAINTENANCE FEE PAYMENT PAID IN FULL

Effective date: 20260219