CA2949488C - Codeur de verification de parite a faible densite ayant une longueur de 64 800 bits et un taux de code de 4/15 et procede de codage de verification de parite a faible densite employant ledit codeur - Google Patents

Codeur de verification de parite a faible densite ayant une longueur de 64 800 bits et un taux de code de 4/15 et procede de codage de verification de parite a faible densite employant ledit codeur Download PDF

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Publication number
CA2949488C
CA2949488C CA2949488A CA2949488A CA2949488C CA 2949488 C CA2949488 C CA 2949488C CA 2949488 A CA2949488 A CA 2949488A CA 2949488 A CA2949488 A CA 2949488A CA 2949488 C CA2949488 C CA 2949488C
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Prior art keywords
row
lambda
ldpc
length
sequence
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CA2949488A
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English (en)
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CA2949488A1 (fr
Inventor
Sung-Ik Park
Heung-Mook Kim
Sun-Hyoung Kwon
Nam-Ho Hur
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Electronics and Telecommunications Research Institute ETRI
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Electronics and Telecommunications Research Institute ETRI
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Priority claimed from CA2864630A external-priority patent/CA2864630C/fr
Publication of CA2949488A1 publication Critical patent/CA2949488A1/fr
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Error Detection And Correction (AREA)

Abstract

Un codeur de vérification de parité à faible densité (LDPC), un décodeur LDPC et une méthode de codage LDPC sont divulgués. Le codeur LDPC comprend une première mémoire, une deuxième mémoire et un processeur. La première mémoire stocke un mot de code LDPC ayant une longueur de 64 800 et un taux de code de 4/15. La deuxième mémoire est initialisée à 0. Le processeur génère le mot de code LDPC correspondant aux bits dinformation en exécutant une accumulation par rapport à la deuxième mémoire en utilisant une séquence correspondant à une matrice de vérification de parité (PCM).
CA2949488A 2014-08-14 2014-09-25 Codeur de verification de parite a faible densite ayant une longueur de 64 800 bits et un taux de code de 4/15 et procede de codage de verification de parite a faible densite employant ledit codeur Active CA2949488C (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
KR10-2014-0106180 2014-08-14
KR20140106180 2014-08-14
KR1020140120014A KR102184832B1 (ko) 2014-08-14 2014-09-11 길이가 64800이며, 부호율이 4/15인 ldpc 부호화기 및 이를 이용한 ldpc 부호화 방법
KR10-2014-0120014 2014-09-11
CA2864630A CA2864630C (fr) 2014-08-14 2014-09-25 Codeur de verification de parite a faible densite ayant une longueur de 64 800 bits et un taux de code de 4/15 et procede de codage de verification de parite a faible densite employant ledit codeur

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CA2864630A Division CA2864630C (fr) 2014-08-14 2014-09-25 Codeur de verification de parite a faible densite ayant une longueur de 64 800 bits et un taux de code de 4/15 et procede de codage de verification de parite a faible densite employant ledit codeur

Publications (2)

Publication Number Publication Date
CA2949488A1 CA2949488A1 (fr) 2016-02-14
CA2949488C true CA2949488C (fr) 2019-10-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CA2949488A Active CA2949488C (fr) 2014-08-14 2014-09-25 Codeur de verification de parite a faible densite ayant une longueur de 64 800 bits et un taux de code de 4/15 et procede de codage de verification de parite a faible densite employant ledit codeur

Country Status (3)

Country Link
KR (3) KR102184832B1 (fr)
CA (1) CA2949488C (fr)
MX (1) MX350601B (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6930376B2 (ja) * 2017-10-31 2021-09-01 ソニーグループ株式会社 送信装置及び送信方法
JP6930377B2 (ja) * 2017-10-31 2021-09-01 ソニーグループ株式会社 送信装置及び送信方法
JP6930374B2 (ja) * 2017-10-31 2021-09-01 ソニーグループ株式会社 送信装置及び送信方法

Also Published As

Publication number Publication date
MX2014012118A (es) 2016-02-15
CA2949488A1 (fr) 2016-02-14
KR102312433B1 (ko) 2021-10-15
MX350601B (es) 2017-09-11
KR20210124157A (ko) 2021-10-14
KR20160020996A (ko) 2016-02-24
KR20200136341A (ko) 2020-12-07
KR102184832B1 (ko) 2020-12-01
KR102506682B1 (ko) 2023-03-07

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