CA935931A - Optimum apparatus and method for check bit generation and error detection, location and correction - Google Patents
Optimum apparatus and method for check bit generation and error detection, location and correctionInfo
- Publication number
- CA935931A CA935931A CA100056A CA100056A CA935931A CA 935931 A CA935931 A CA 935931A CA 100056 A CA100056 A CA 100056A CA 100056 A CA100056 A CA 100056A CA 935931 A CA935931 A CA 935931A
- Authority
- CA
- Canada
- Prior art keywords
- correction
- location
- error detection
- check bit
- bit generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US88785869A | 1969-12-24 | 1969-12-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA935931A true CA935931A (en) | 1973-10-23 |
Family
ID=25392006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA100056A Expired CA935931A (en) | 1969-12-24 | 1970-12-08 | Optimum apparatus and method for check bit generation and error detection, location and correction |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3623155A (fr) |
| JP (1) | JPS5144767B1 (fr) |
| CA (1) | CA935931A (fr) |
| DE (1) | DE2060643C3 (fr) |
| FR (1) | FR2074917A5 (fr) |
| GB (1) | GB1315340A (fr) |
Families Citing this family (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3755779A (en) * | 1971-12-14 | 1973-08-28 | Ibm | Error correction system for single-error correction, related-double-error correction and unrelated-double-error detection |
| US3893070A (en) * | 1974-01-07 | 1975-07-01 | Ibm | Error correction and detection circuit with modular coding unit |
| US3913068A (en) * | 1974-07-30 | 1975-10-14 | Ibm | Error correction of serial data using a subfield code |
| US4005405A (en) * | 1975-05-07 | 1977-01-25 | Data General Corporation | Error detection and correction in data processing systems |
| US4159468A (en) * | 1977-11-17 | 1979-06-26 | Burroughs Corporation | Communications line authentication device |
| JPS5534817A (en) * | 1978-08-31 | 1980-03-11 | Tokyo Electric Power Co | Converter |
| JPS55131860A (en) * | 1979-03-30 | 1980-10-14 | Matsushita Electric Ind Co Ltd | Error correction unit |
| JPS57207960A (en) * | 1981-06-17 | 1982-12-20 | Toshiba Corp | Method for adding error correcting code to variable length data |
| DE3134831A1 (de) * | 1981-09-03 | 1983-03-10 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | System zur uebertragung digitaler informationssignale |
| US4771378A (en) * | 1984-06-19 | 1988-09-13 | Cray Research, Inc. | Electrical interface system |
| CA1228677A (fr) * | 1984-06-21 | 1987-10-27 | Cray Research, Inc. | Systeme d'interface peripherique |
| DE3482509D1 (de) * | 1984-12-28 | 1990-07-19 | Ibm | Geraet zum korrigieren von fehlern in speichern. |
| DE3882175T2 (de) * | 1987-07-20 | 1994-01-27 | Ibm | Fehlerkorrektur-Kode für einen B-bit-pro-Chip-Speicher mit verminderten Redundanz. |
| US4862463A (en) * | 1987-07-20 | 1989-08-29 | International Business Machines Corp. | Error correcting code for 8-bit-per-chip memory with reduced redundancy |
| US4868829A (en) * | 1987-09-29 | 1989-09-19 | Hewlett-Packard Company | Apparatus useful for correction of single bit errors in the transmission of data |
| US5283791A (en) * | 1988-08-02 | 1994-02-01 | Cray Research Systems, Inc. | Error recovery method and apparatus for high performance disk drives |
| US5218689A (en) * | 1988-08-16 | 1993-06-08 | Cray Research, Inc. | Single disk emulation interface for an array of asynchronously operating disk drives |
| JPH02125532A (ja) * | 1988-11-04 | 1990-05-14 | Sony Corp | Bch符号の復号装置 |
| GB9213818D0 (en) * | 1992-06-30 | 1992-08-12 | Inmos Ltd | Digital signal comparison circuitry |
| US5491702A (en) * | 1992-07-22 | 1996-02-13 | Silicon Graphics, Inc. | Apparatus for detecting any single bit error, detecting any two bit error, and detecting any three or four bit error in a group of four bits for a 25- or 64-bit data word |
| US5774481A (en) * | 1995-03-31 | 1998-06-30 | International Business Machines Corporation | Reduced gate error detection and correction circuit |
| US5745507A (en) * | 1995-03-31 | 1998-04-28 | International Business Machines Corporation | Systematic symbol level ECC for use in digital memory systems |
| JP3234130B2 (ja) * | 1995-05-30 | 2001-12-04 | 三菱電機株式会社 | 誤り訂正符号復号化方法およびこの方法を用いる回路 |
| US5761221A (en) * | 1995-12-11 | 1998-06-02 | International Business Machines Corporation | Memory implemented error detection and correction code using memory modules |
| US5768294A (en) * | 1995-12-11 | 1998-06-16 | International Business Machines Corporation | Memory implemented error detection and correction code capable of detecting errors in fetching data from a wrong address |
| US6003144A (en) * | 1997-06-30 | 1999-12-14 | Compaq Computer Corporation | Error detection and correction |
| FR2823035B1 (fr) * | 2001-04-03 | 2003-07-11 | St Microelectronics Sa | Code de detection et/ou de correction d'erreurs a haute efficacite |
| US7117420B1 (en) * | 2001-05-17 | 2006-10-03 | Lsi Logic Corporation | Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories |
| FR2875352B1 (fr) * | 2004-09-10 | 2007-05-11 | St Microelectronics Sa | Procede de detection et de correction d'erreurs pour une memoire et circuit integre correspondant |
| US7653862B2 (en) * | 2005-06-15 | 2010-01-26 | Hitachi Global Storage Technologies Netherlands B.V. | Error detection and correction for encoded data |
| US7962837B2 (en) * | 2007-09-13 | 2011-06-14 | United Memories, Inc. | Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix |
| FR2941806A1 (fr) * | 2009-02-03 | 2010-08-06 | Commissariat Energie Atomique | Procede de codage correcteur d'erreurs avec bits de parite totale et procede de detection d'erreurs multiples |
| US8539321B2 (en) * | 2010-11-10 | 2013-09-17 | Infineon Technologies Ag | Apparatus and method for correcting at least one bit error within a coded bit sequence |
| US9450613B2 (en) | 2010-11-10 | 2016-09-20 | Infineon Technologies Ag | Apparatus and method for error correction and error detection |
| US9800271B2 (en) * | 2015-09-14 | 2017-10-24 | Qualcomm Incorporated | Error correction and decoding |
| JP2018074545A (ja) * | 2016-11-04 | 2018-05-10 | 富士通株式会社 | データ処理システム及びデータ処理装置 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL267314A (fr) * | 1960-03-02 | |||
| US3458860A (en) * | 1965-03-08 | 1969-07-29 | Burroughs Corp | Error detection by redundancy checks |
| US3411135A (en) * | 1965-03-15 | 1968-11-12 | Bell Telephone Labor Inc | Error control decoding system |
| US3416132A (en) * | 1965-04-05 | 1968-12-10 | Ibm | Group parity handling |
| US3504340A (en) * | 1967-05-08 | 1970-03-31 | Ibm | Triple error correction circuit |
-
1969
- 1969-12-24 US US887858A patent/US3623155A/en not_active Expired - Lifetime
-
1970
- 1970-10-27 FR FR7040287A patent/FR2074917A5/fr not_active Expired
- 1970-11-11 JP JP45098826A patent/JPS5144767B1/ja active Pending
- 1970-11-13 GB GB4502370A patent/GB1315340A/en not_active Expired
- 1970-12-08 CA CA100056A patent/CA935931A/en not_active Expired
- 1970-12-09 DE DE2060643A patent/DE2060643C3/de not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2060643B2 (de) | 1979-03-22 |
| DE2060643C3 (de) | 1979-11-15 |
| JPS5144767B1 (fr) | 1976-11-30 |
| GB1315340A (en) | 1973-05-02 |
| DE2060643A1 (de) | 1971-07-01 |
| US3623155A (en) | 1971-11-23 |
| FR2074917A5 (fr) | 1971-10-08 |
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