CA978604A - Single line per bit asynchronous circuit and system - Google Patents

Single line per bit asynchronous circuit and system

Info

Publication number
CA978604A
CA978604A CA162,265A CA162265A CA978604A CA 978604 A CA978604 A CA 978604A CA 162265 A CA162265 A CA 162265A CA 978604 A CA978604 A CA 978604A
Authority
CA
Canada
Prior art keywords
single line
per bit
line per
asynchronous circuit
bit asynchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA162,265A
Other languages
English (en)
Other versions
CA162265S (en
Inventor
Dallas J. Mallerich (Jr.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DYAD SYSTEMS
Original Assignee
DYAD SYSTEMS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DYAD SYSTEMS filed Critical DYAD SYSTEMS
Application granted granted Critical
Publication of CA978604A publication Critical patent/CA978604A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Shift Register Type Memory (AREA)
  • Read Only Memory (AREA)
CA162,265A 1972-02-01 1973-01-29 Single line per bit asynchronous circuit and system Expired CA978604A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22252072A 1972-02-01 1972-02-01

Publications (1)

Publication Number Publication Date
CA978604A true CA978604A (en) 1975-11-25

Family

ID=22832548

Family Applications (1)

Application Number Title Priority Date Filing Date
CA162,265A Expired CA978604A (en) 1972-02-01 1973-01-29 Single line per bit asynchronous circuit and system

Country Status (7)

Country Link
US (1) US3736575A (it)
JP (1) JPS4887740A (it)
CA (1) CA978604A (it)
DE (1) DE2304007A1 (it)
GB (1) GB1427993A (it)
IT (1) IT978720B (it)
NL (1) NL7301371A (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3972034A (en) * 1975-05-12 1976-07-27 Fairchild Camera And Instrument Corporation Universal first-in first-out memory device
US4163291A (en) * 1975-10-15 1979-07-31 Tokyo Shibaura Electric Co., Ltd. Input-output control circuit for FIFO memory
US4110842A (en) * 1976-11-15 1978-08-29 Advanced Micro Devices, Inc. Random access memory with memory status for improved access and cycle times
NL7713708A (nl) * 1977-12-12 1979-06-14 Philips Nv Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met vaste ingang en variabele uitgang.
FR2573890B1 (fr) * 1984-11-27 1987-07-24 Bendix Electronics Sa Dispositifs electroniques d'acquisition des signaux periodiques asynchrones
US4679213A (en) * 1985-01-08 1987-07-07 Sutherland Ivan E Asynchronous queue system
FR2632091A1 (fr) * 1988-05-30 1989-12-01 Chauffour Jean Claude Procede de memorisation electronique de donnees au moyen de cellules a deux etats, et ses moyens de mise en oeuvre

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3544992A (en) * 1967-06-01 1970-12-01 Bell Telephone Labor Inc Code translator

Also Published As

Publication number Publication date
DE2304007A1 (de) 1973-08-09
GB1427993A (en) 1976-03-10
NL7301371A (it) 1973-08-03
US3736575A (en) 1973-05-29
IT978720B (it) 1974-09-20
JPS4887740A (it) 1973-11-17

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