CH516871A - Procedimento per ottenere dispositivi a semiconduttore con minimi dislivelli in superficie, e dispositivo a semiconduttore ottenuto mediante detto procedimento - Google Patents

Procedimento per ottenere dispositivi a semiconduttore con minimi dislivelli in superficie, e dispositivo a semiconduttore ottenuto mediante detto procedimento

Info

Publication number
CH516871A
CH516871A CH744070A CH744070A CH516871A CH 516871 A CH516871 A CH 516871A CH 744070 A CH744070 A CH 744070A CH 744070 A CH744070 A CH 744070A CH 516871 A CH516871 A CH 516871A
Authority
CH
Switzerland
Prior art keywords
device obtained
surface unevenness
semiconductor device
minimal surface
obtaining
Prior art date
Application number
CH744070A
Other languages
English (en)
Inventor
Franco Dr Morandi
Original Assignee
Soc Gen Semiconduttori Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soc Gen Semiconduttori Spa filed Critical Soc Gen Semiconduttori Spa
Publication of CH516871A publication Critical patent/CH516871A/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0128—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising multiple local oxidation process steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
CH744070A 1969-07-30 1970-05-20 Procedimento per ottenere dispositivi a semiconduttore con minimi dislivelli in superficie, e dispositivo a semiconduttore ottenuto mediante detto procedimento CH516871A (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT5283069 1969-07-30

Publications (1)

Publication Number Publication Date
CH516871A true CH516871A (it) 1971-12-15

Family

ID=11277825

Family Applications (1)

Application Number Title Priority Date Filing Date
CH744070A CH516871A (it) 1969-07-30 1970-05-20 Procedimento per ottenere dispositivi a semiconduttore con minimi dislivelli in superficie, e dispositivo a semiconduttore ottenuto mediante detto procedimento

Country Status (7)

Country Link
AU (1) AU1774570A (it)
BE (1) BE753976A (it)
CH (1) CH516871A (it)
DE (1) DE2031918A1 (it)
FR (1) FR2053271A7 (it)
IL (1) IL35015A0 (it)
NL (1) NL7011252A (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
US3966514A (en) * 1975-06-30 1976-06-29 Ibm Corporation Method for forming dielectric isolation combining dielectric deposition and thermal oxidation
JPS5693344A (en) * 1979-12-26 1981-07-28 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
FR2053271B3 (it) 1973-04-27
DE2031918A1 (de) 1971-02-11
FR2053271A7 (en) 1971-04-16
NL7011252A (it) 1971-02-02
IL35015A0 (en) 1970-09-17
AU1774570A (en) 1972-01-20
BE753976A (fr) 1970-12-31

Similar Documents

Publication Publication Date Title
BR6915742D0 (pt) Dispositivo semicondutor
NL162253C (nl) Halfgeleiderinrichting.
CH507591A (de) Halbleitervorrichtung
NL161617B (nl) Halfgeleiderinrichting met vlak oppervlak en werkwijze voor het vervaardigen daarvan.
NL161923C (nl) Halfgeleiderinrichting.
CH504108A (de) Halbleiteranordnung
BR7018863D0 (pt) Dispositivo semicondutor integrado
BR7310275D0 (pt) Aperfeicoamento em dispositivo semicondutor de juncoes multiplas
BR6909280D0 (pt) Dispositivo semicondutor com multiplos terminais
HK72478A (en) Semiconductor device
CH511512A (de) Halbleitervorrichtung
BR6909999D0 (pt) Dispositivo semicondutor
BE753246A (fr) Dispositif semi-conducteur a heterojonction
BR7308693D0 (pt) Dispositivo semicondutor
AT300961B (de) Halbleiteranordnung
NL163672C (nl) Halfgeleiderinrichting.
BR7310282D0 (pt) Aperfeicoamento em dispositivo semicondutor de juncoes multiplas
CH487504A (de) Halbleitervorrichtung
CH516871A (it) Procedimento per ottenere dispositivi a semiconduttore con minimi dislivelli in superficie, e dispositivo a semiconduttore ottenuto mediante detto procedimento
DE1903342B2 (de) Halbleitervorrichtung
BR6908675D0 (pt) Dispositivo semicondutor em embalagem rasa
CH499204A (de) Halbleitervorrichtung
CH513515A (de) Halbleiteranordnung
IE34505L (en) Semiconductor device
AT310811B (de) Halbleiterelement mit Kühleinrichtung

Legal Events

Date Code Title Description
PL Patent ceased