CH548708A - Verfahren zur aufrechterhaltung des gleichlaufes einer sende- und empfangseinrichtung fuer eine synchrone datenuebertragung. - Google Patents

Verfahren zur aufrechterhaltung des gleichlaufes einer sende- und empfangseinrichtung fuer eine synchrone datenuebertragung.

Info

Publication number
CH548708A
CH548708A CH1758571A CH1758571A CH548708A CH 548708 A CH548708 A CH 548708A CH 1758571 A CH1758571 A CH 1758571A CH 1758571 A CH1758571 A CH 1758571A CH 548708 A CH548708 A CH 548708A
Authority
CH
Switzerland
Prior art keywords
sending
procedure
receiving device
data transfer
synchronous data
Prior art date
Application number
CH1758571A
Other languages
English (en)
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of CH548708A publication Critical patent/CH548708A/de

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
CH1758571A 1971-01-27 1971-12-03 Verfahren zur aufrechterhaltung des gleichlaufes einer sende- und empfangseinrichtung fuer eine synchrone datenuebertragung. CH548708A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19712103825 DE2103825A1 (de) 1971-01-27 1971-01-27 Verfahren zur Aufrechterhaltung des Gleichlaufes der Sende und Empfangseinrichtung in Synchron Daten ubertragungs anlagen

Publications (1)

Publication Number Publication Date
CH548708A true CH548708A (de) 1974-04-30

Family

ID=5797077

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1758571A CH548708A (de) 1971-01-27 1971-12-03 Verfahren zur aufrechterhaltung des gleichlaufes einer sende- und empfangseinrichtung fuer eine synchrone datenuebertragung.

Country Status (8)

Country Link
BE (1) BE778563A (de)
CH (1) CH548708A (de)
DE (1) DE2103825A1 (de)
FR (1) FR2131302A5 (de)
GB (1) GB1336271A (de)
IT (1) IT946798B (de)
LU (1) LU64657A1 (de)
NL (1) NL7200528A (de)

Also Published As

Publication number Publication date
DE2103825A1 (de) 1972-08-24
GB1336271A (en) 1973-11-07
LU64657A1 (de) 1972-08-23
BE778563A (fr) 1972-07-27
IT946798B (it) 1973-05-21
NL7200528A (de) 1972-07-31
FR2131302A5 (de) 1972-11-10

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Legal Events

Date Code Title Description
PL Patent ceased