CH570707A5 - - Google Patents

Info

Publication number
CH570707A5
CH570707A5 CH1714072A CH1714072A CH570707A5 CH 570707 A5 CH570707 A5 CH 570707A5 CH 1714072 A CH1714072 A CH 1714072A CH 1714072 A CH1714072 A CH 1714072A CH 570707 A5 CH570707 A5 CH 570707A5
Authority
CH
Switzerland
Application number
CH1714072A
Original Assignee
Suwa Seikosha Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suwa Seikosha Kk filed Critical Suwa Seikosha Kk
Publication of CH570707A5 publication Critical patent/CH570707A5/xx

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate
CH1714072A 1971-11-25 1972-11-24 CH570707A5 (mo)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP46094703A JPS4859781A (mo) 1971-11-25 1971-11-25

Publications (1)

Publication Number Publication Date
CH570707A5 true CH570707A5 (mo) 1975-12-15

Family

ID=14117515

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1714072A CH570707A5 (mo) 1971-11-25 1972-11-24

Country Status (5)

Country Link
US (1) US3942241A (mo)
JP (1) JPS4859781A (mo)
CH (1) CH570707A5 (mo)
DE (1) DE2255171B2 (mo)
GB (1) GB1348235A (mo)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0145927A1 (en) * 1983-12-12 1985-06-26 International Business Machines Corporation Integrated circuit fet structure

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5928992B2 (ja) * 1975-02-14 1984-07-17 日本電信電話株式会社 Mosトランジスタおよびその製造方法
US4085499A (en) * 1975-12-29 1978-04-25 Matsushita Electric Industrial Co., Ltd. Method of making a MOS-type semiconductor device
US4277881A (en) * 1978-05-26 1981-07-14 Rockwell International Corporation Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4358891A (en) * 1979-06-22 1982-11-16 Burroughs Corporation Method of forming a metal semiconductor field effect transistor
DE2926874A1 (de) * 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
FR2461360A1 (fr) * 1979-07-10 1981-01-30 Thomson Csf Procede de fabrication d'un transistor a effet de champ du type dmos a fonctionnement vertical et transistor obtenu par ce procede
US4359816A (en) * 1980-07-08 1982-11-23 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits
US4414737A (en) * 1981-01-30 1983-11-15 Tokyo Shibaura Denki Kabushiki Kaisha Production of Schottky barrier diode
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
US4712125A (en) * 1982-08-06 1987-12-08 International Business Machines Corporation Structure for contacting a narrow width PN junction region
US4507171A (en) * 1982-08-06 1985-03-26 International Business Machines Corporation Method for contacting a narrow width PN junction region
JPH01151268A (ja) * 1987-12-08 1989-06-14 Mitsubishi Electric Corp 半導体装置の製造方法
KR940005729B1 (ko) * 1989-06-13 1994-06-23 삼성전자 주식회사 디램셀의 제조방법 및 구조
US6039857A (en) * 1998-11-09 2000-03-21 Yeh; Ching-Fa Method for forming a polyoxide film on doped polysilicon by anodization
JP2006339355A (ja) * 2005-06-01 2006-12-14 Nec Electronics Corp 半導体集積回路装置及びその設計方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3475234A (en) * 1967-03-27 1969-10-28 Bell Telephone Labor Inc Method for making mis structures
US3566518A (en) * 1967-10-13 1971-03-02 Gen Electric Method for fabricating field-effect transistor devices and integrated circuit modules containing the same by selective diffusion of activator impurities through preselected portions of passivating-insulating films
US3699646A (en) * 1970-12-28 1972-10-24 Intel Corp Integrated circuit structure and method for making integrated circuit structure
US3750268A (en) * 1971-09-10 1973-08-07 Motorola Inc Poly-silicon electrodes for c-igfets

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0145927A1 (en) * 1983-12-12 1985-06-26 International Business Machines Corporation Integrated circuit fet structure

Also Published As

Publication number Publication date
GB1348235A (en) 1974-03-13
DE2255171B2 (de) 1976-07-08
DE2255171A1 (de) 1973-05-30
JPS4859781A (mo) 1973-08-22
US3942241A (en) 1976-03-09

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Legal Events

Date Code Title Description
PL Patent ceased
PL Patent ceased