CH609201GA3 - - Google Patents
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- Publication number
- CH609201GA3 CH609201GA3 CH1077275A CH1077275A CH609201GA3 CH 609201G A3 CH609201G A3 CH 609201GA3 CH 1077275 A CH1077275 A CH 1077275A CH 1077275 A CH1077275 A CH 1077275A CH 609201G A3 CH609201G A3 CH 609201GA3
- Authority
- CH
- Switzerland
- Prior art keywords
- divider circuit
- dividing
- divider
- stages
- cascade
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G3/00—Producing timing pulses
- G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
- G04G3/022—Circuits for deriving low frequency timing pulses from pulses of higher frequency the desired number of pulses per unit of time being obtained by adding to or substracting from a pulse train one or more pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/662—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by adding or suppressing pulses
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Electric Clocks (AREA)
- Electromechanical Clocks (AREA)
- Oscillators With Electromechanical Resonators (AREA)
Abstract
A divider for an electronic timepiece comprises a multistage divider circuit having a plurality of 1/2 dividing stages connected in cascade. Logic circuitry connected to the first and last stages develops a preselected number of pulse signals smaller in number than the dividing number of the divider circuit to effect selective stopping of the counting of only one input signal pulse applied to the divider circuit to thereby obtain fine adjustment of the final output signal pulses.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9480574A JPS5614007B2 (en) | 1974-08-19 | 1974-08-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CH609201B CH609201B (en) | |
| CH609201GA3 true CH609201GA3 (en) | 1979-02-28 |
Family
ID=14120259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CH1077275A CH609201B (en) | 1974-08-19 | 1975-08-19 | DIVIDER FOR THE TIME-GUARD CIRCUIT OF AN ELECTRONIC CLOCK PART. |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4009445A (en) |
| JP (1) | JPS5614007B2 (en) |
| CH (1) | CH609201B (en) |
| DE (1) | DE2536953A1 (en) |
| FR (1) | FR2282752A1 (en) |
| GB (1) | GB1497479A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994029959A1 (en) * | 1993-06-16 | 1994-12-22 | Nokia Telecommunications Oy | A method for multiplying the frequency of a digital signal and a frequency multiplier circuit |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5291471A (en) * | 1976-01-28 | 1977-08-01 | Toshiba Corp | Clock pulse generator |
| US4093873A (en) * | 1976-10-28 | 1978-06-06 | Intel Corporation | Compensating digital counter for quartz crystal oscillator |
| US4310801A (en) * | 1977-03-25 | 1982-01-12 | Stewart-Warner Corporation | Programmable divider |
| JPS5945261B2 (en) * | 1977-06-21 | 1984-11-05 | シチズン時計株式会社 | Digital frequency adjustment circuit |
| US4199726A (en) * | 1977-09-23 | 1980-04-22 | Bukosky Allen A | Digitally tunable integrated circuit pulse generator and tuning system |
| GB2089539B (en) * | 1980-12-08 | 1984-08-01 | Plessey Co Ltd | Adjustable ratio divider |
| GB2111269B (en) * | 1981-11-25 | 1986-04-09 | Plessey Co Plc | Adjustable ratio divider |
| JP3180494B2 (en) * | 1992-04-17 | 2001-06-25 | セイコーエプソン株式会社 | Logic device |
| EP2916193B1 (en) * | 2014-03-06 | 2016-07-27 | EM Microelectronic-Marin SA | Time base including an oscillator, a frequency-divider circuit and a timing pulse inhibition circuit |
| JP6498031B2 (en) * | 2015-05-18 | 2019-04-10 | セイコーインスツル株式会社 | Frequency divider, frequency divider control method, and analog electronic timepiece |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CH585271A4 (en) * | 1971-04-22 | 1973-02-15 | ||
| US3823551A (en) * | 1971-05-03 | 1974-07-16 | Riehl Electronics Corp | Solid state electronic timepiece |
| GB1349023A (en) * | 1971-07-16 | 1974-03-27 | Omega Brandt & Freres Sa Louis | Adjustable frequency pulse generator |
| US3833854A (en) * | 1972-12-14 | 1974-09-03 | Singer Co | Digital phase shifter |
| US3863224A (en) * | 1973-01-30 | 1975-01-28 | Gen Electric | Selectively controllable shift register and counter divider network |
-
1974
- 1974-08-19 JP JP9480574A patent/JPS5614007B2/ja not_active Expired
-
1975
- 1975-08-15 US US05/605,062 patent/US4009445A/en not_active Expired - Lifetime
- 1975-08-18 GB GB34245/75A patent/GB1497479A/en not_active Expired
- 1975-08-19 FR FR7525653A patent/FR2282752A1/en active Granted
- 1975-08-19 DE DE19752536953 patent/DE2536953A1/en not_active Withdrawn
- 1975-08-19 CH CH1077275A patent/CH609201B/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994029959A1 (en) * | 1993-06-16 | 1994-12-22 | Nokia Telecommunications Oy | A method for multiplying the frequency of a digital signal and a frequency multiplier circuit |
| GB2295286A (en) * | 1993-06-16 | 1996-05-22 | Nokia Telecommunications Oy | A method for multiplying the frequency of a digital signal and a frequency multiplier circuit |
| GB2295286B (en) * | 1993-06-16 | 1997-04-30 | Nokia Telecommunications Oy | A method for multiplying the frequency of a digital signal and a frequency multiplier circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| GB1497479A (en) | 1978-01-12 |
| US4009445A (en) | 1977-02-22 |
| FR2282752A1 (en) | 1976-03-19 |
| JPS5614007B2 (en) | 1981-04-01 |
| DE2536953A1 (en) | 1976-03-04 |
| FR2282752B1 (en) | 1981-04-17 |
| JPS5122359A (en) | 1976-02-23 |
| CH609201B (en) |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PL | Patent ceased |