CH616792A5 - Method for multiplexing and demultiplexing binary signals and device to carry out the method - Google Patents

Description

616 792 2

PATENT CLAIMS, such that after N cycles, where N is the specified

1. Method for multiplexing and demultiplexing said constant number of consecutive sampling binary characters, values meaning a complete count code word is formed,

- A device is provided to which a multi-which has three areas, each of which consists of a number of input lines (1) and output lines (2) 5 and an associated signal value indication, each being connected via which the binary characters arrive or number indicates how often the assigned signal value was sampled without polar polarity, change of activity,

- Each binary character from a predetermined number - by a second counter circuit (10), which consists of character elements at each cycle, which character elements step the content of the assigned line reduced by one of two signal values, each 10 sub-elements, such that after N cycles the memory line lasts for a predetermined time, is empty, and the respective sub-element as a binary character sub-element

- In order to detect the binary line to be multiplexed for the duration of the cycle time, all input lines (1) are sent out to the assigned exchanges with respect to the line on them,

currently available signal values are sampled cyclically - by a second address generator (13), which

and and the cycle time is so short that for each character-15 chron with the first address generator (7) the takeover element a predetermined number of samples is omitted. complete count code words from the first (5) to the second (19)

- The samples of each input line under and from the fourth (20) in the third (6) memory controls, using stored data assigned to the lines to - and by at least one processor (17, 18), which and the drawing elements code-addressed words conversion of counting code words into code-addressed words can be put together, which words control on a multiplex 20 and vice versa.

busbar (15) are issued,

- And wherein each via the multiplex busbar (15)

incoming code addressed word for demultiplexing in

transformed a binary sign and as such onto the by the

Word specified output line (2) is sent, 25

characterized by two processing steps each in The invention relates to a method for multiplexing

Multiplexing and demultiplexing direction with the following proper and demultiplexing of binary characters according to the preamble: the first claim. It also relates to a device

- in the multiplexing direction by the first processing to exercise the method mentioned.

processing step for each input line (1), one in each case 30 From the Swiss patent specification 482 366 it is known

to transmit the remaining number of consecutive samples together asynchronously arriving binary characters, by adding a count code word each, which specifies in which one the incoming characters are scanned, which are to be scanned in the

The order of how much successive sample results contain redundancy through logical processing values which signal values follow one another; reduced and the character words thus obtained in a syn-

- in the direction of multiplexing, the chronological process is transmitted by the second processing method. The processing step using the stored data assigned to the single arrangements for input circuits of telex transmission lines (1) is of particular importance for each input line switch to which many telecommunications stations from the successive counting code words are connected to one another. The scanning and the processing-following character elements and from these code-addressed device advantageously takes place in time-division multiplex words, which after completion are output to the <0 ren to the high operating speed of electronic switching multiplex busbar (15); to be able to exploit circles.

- In the demultiplexing direction is described by the first processor. In Hasler-Mitteilungen 33 (1974), Issue 3, a fully electronic telexcentric is described in three steps using the stored, the off, in which data associated with the transmission lines (2) each Via the multi-plex bus (15) incoming code-addressed word in 45 is used - the above method of signal sampling. The processing of the individual samples is converted into a sequence of counter code words, which sequence using semipermanent data which are assigned to the lines assigned to the output line (2) determined by the word. Such data are, for example, net; the code used and the walking speed. Continue

- And in the direction of the multiplexing, there are temporary data by the second, which constantly indicate the current state of the processing step on each output line (2) so processing. The data are contained in memories, signal values are issued, the type, duration and sequence of which are determined by the count code words provided for each input line, which are provided by the first line. Such a line will occur one after the other for each processing step. saved and then unchanged or changed again

2. Device for practicing the method after registered.

Claim 1, characterized, 55 The number of lines through a multiplexing

- By at least four memories (5, 6, 19, 20), which can be queried, is limited by the time that memory lines have, the lines of the first (5) and being used for a processing step. Therefore, the second (19) memory of the input lines (1) and the time generally only relatively simple processing of the third (6) and the fourth (20) memory of the output steps are possible if the number of lines is not too small lines (2) are assigned to be 60. It is also known to be certain right at the entrance

- By means of a first address and clock generator (7) to select the scanning results, and only to further process the addresses of the memory lines with the sampling clock; however, part of the information, in particular the first (5) and the third (6) memory, is called up and immediately lost through distortion of the telegraph characters. The timing of the processing time that is too short for the assigned input line (1) is avoided and for the assigned output line (2) a send-out is triggered by using a method for multiplexing and step-demultiplexing binary characters with the

- By a first counting circuit (9), the properties of each sample, the part of the first claim, with the content of the assigned line of the first memory (5).

3,616,792

Reversible device in the second claim - a send processor 18 for converting character formats. in counting code words, a character processing memory 20 for

In the following, the method and the device intermediate storage during the dismantling of the character formats, for example with reference to the figures, is explained. Shown are: character memory 22 for temporary storage of the incoming

Fig. 1 is a block diagram of the circuit arrangement for 5 NEN character formats, and an input buffer memory 24 for

Practice of the procedure Storage of the time arriving on Transferstrasse 15

2a shows the format of a format used in the circuit arrangement according to the principle of the queue and for the third count code word and an example of the same, transfer to the character memory 22.

FIG. 2b, a transmission and reception side assigned to the counting code word from FIG. 2a is common, apart from the second

Scan group, 10 th address generator 13 a line data memory 14, the

3 is a flowchart which shows the process of forming the count code word which remains constant for each line over a longer period of time and contains data which is stored in a semi-permanent manner. All in the two-

4 shows a flowchart to explain the memory called the effective processing stage, apart from instructing the entire circuit. gear and the output buffer memory 23 and 24 have for

1 shows a circuit arrangement for transmission, each input or output line is a memory line, binary-coded characters from input lines 1 to a multi-. In the following, a number is used to clarify the processes.

plextransferstrasse 15 and given for the transfer from this to the lenbeispiel. The number of lines 1 and 2 is 256,

Output lines 2. Their speed is 200 vol. Each drawing element

The circuit arrangement consists of two stages, namely has a duration of 5 ms and is scanned 18 times. Thus, the collecting and distribution stage I and the signal processing 20 take place on all channels during this time.

stage II. stage I contains: a multiplexer 3 and a demultiple: '18x256 = 4608 samples and 921 600 during a plexer 4, which contains one second of line connection, so that on average one sample is taken every 1.085 jxs,

ten are connected to the lines. For sending and receiving, 18 consecutive samples of the same catch are drawn separate lines, but line can also be combined and described in

each line pair is formed into a two-wire line in the same way in a counting code word, which will then be summarized in parallel. transferred to the second processing stage so that for the

5 is a receive counter memory, 6 is a transmit counter memory. processing of each individual code word 18x1.085 p, s = 19.53

Both have a memory line for each line. 7 is an address, s are available. The same times apply to the sengenerator, which continuously generates address signals. Conversion of counter code words into the signals of the

and delivers on address line 8. Each address is a single line.

tion pair and the associated memory lines. Fig. 2a shows the format of a fully assembled count code is a receive counter circuit, 10 a transmit counter circuit. An address is called up in words in the receive and transmit counter memories 5 and 6 and in each collecting and distributing step — an example of such a counter code word. Above are the numbers and thus a sample from demultiplexer 3 and the numbers of the digits of the counting code word. Since the time corresponding to a corresponding memory line from the receive counter memory 5 35 sample group is the same as the time of a character to receive counter circuit 9, furthermore the corresponding elements, during this time even with the highest memory line from the transmit counter memory 6, distortions occurring to the transmit counter cannot occur more than 2 polarity circuit 10 and a character sub-element of this occur for change.

Démultiplexer 4 transmit. At the end of the work step In a finished counter code word, changed counter code words are written in the two memory lines 40 0: The polarity of the last bit (A3) of the scanning group, which contains a summary of the 1 ... 6: binary number of the successive bits unchanged Scanning results obtained at a specific point in time or the polarity at the end of the scanning group (Z3)

up to a certain point in time - 7: penultimate polarity (A2, opposite to AI) (if previous

Are sub-elements. act)

A certain number of scanning results or 45 8 ... 13: number of bits (Z2) belonging to this polarity (if available)

Step sub-elements are combined into a group)

and the counting code words corresponding to the groups become 14: polarity of the third to last group (AI) (if present)

to a receive buffer memory 11 or transmit buffer memory 15 ... 20: associated number of bits (ZI) (if available)

rather transmitted 12. 2b shows a scanning group (1st scanning on the right, the link between the collecting and distribution stage I and the last one on the left), which belongs to the counting code word in FIG. 2a. The

Signal processing stage II. The transmission of the counting code scanning group contains a polarity change, accordingly

words to the receive buffer and to the transmit buffer while chend 2 polarities are entered, the first with 7, the second of a sampling and distribution pause is by a second address with 11 bits. The structure of the receive counter code word sengenerator 13 controlled via the second address line 16. happens as follows: (see flowchart Fig. 3) at

This address generator is via address line 8 from 55 of each sample, the multiplexer 3 becomes the sample value A

synchronizes the first address generator such that during a line and from the receive counter memory 5 the

transfer 18 lines of stage I each line of stage II speaking to the reception counter circuit 9,

expires, accordingly for a correspondingly long time from the transmitted count code word and the sample value

Available. a new counting code word is formed and returned to the

The signal processing stage II contains 60 received count memory 5. In the first sample value side: a reception processor 17 for converting the counting co- (Z3 = 0) comes into position 0, the polarity (A - A3) and into the word in character formats, a counting field associated with a character structure memory 19 (Z3, bits 1-6) the number 1. With each taper buffering when building the character formats, with the same polarity (A = A3) of the same line, the one character memory 21 for buffering the finished number in this counting field is increased by 1 (Z3 + 1 - Z3). If the gene character formats and an output buffer memory 23 change to 65 polarity (A ^ A3), the first polarity from position 0 to intermediate storage of the position 7 on multiplex transfer line 15, the number to be output from the first counting field into the second counting field according to the principle of Queue. (Bits 8-13) and the new polarity at position 0 The transmission side of signal processing stage II contains: and the number 1 is written in the first counting field. The wide-

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Ren scans of the second polarity are counted in the first counting buffer 24 and the character memory 22 to the character field. In the event of a second polarity field change of the character formats transferred to the building memory with the aid of the sensor, there is again a shift by seven digits to the left of the deprocessor 18. The timing of the individual steps and the counting continues in the first field. This continues for so long and the collaboration between the first and second continues until 18 scans are counted, then the 5 levels are shown in the flow diagram of FIG. 4. In the count code word transferred to the receive buffer 11 and the first signal processing stage is first set to 0 in a step-related memory counter. At the same time, the number m = 0 entered and the address L in the address - but in the opposite direction, the conversion of the generator 7 is increased by 1, then the new address is counting code words, which are scanned from the transmission buffer 12 to the transmission counter and assigned line the word has been transmitted in the reception memory 6. 10 memory changed according to FIG. 3. Likewise, in the signal processing stage II, the line data line of the same number stores a partial character element which is semipermanently transmitted by the memory 14, the polarity determined for each line and the count code word, and this in static data. Such data relate to the line speed transmit counter memory existing count code word corresponding to the changed code (5,7 or 8 steps per character) changed. The number m is increased by 1. This happens 18 times. u. a. In the character build-up memory 19 and in the character breakdown 15, simultaneously with the processing of 18 lines in the collective memory 20, as the names indicate, the data are given, and distribution stage I, the processing of a scan takes place which changes as it is passed through, such as e.g. B. an indication group or the generation of a distribution group in the signal about the current activity of the line, an indication processing stage II. Then a line is transferred over the number that has occurred since the start of the start character from the reception counter memory to the reception buffer memory and the samples or the number of samples since the beginning of 20 from the transmit buffer memory to the transmit counter memory. The line in the last character step and the number of this step receive count memory is deleted and the address in the two-character character, etc. For each processing step, the ten address generator 13 is increased by one, so that the next line contains a count code word from the receive buffer and the most Processing step the next line is processed, the corresponding lines of the line data memory 14 and the processing of the addresses does not have to transfer the character structure memory 19, and the new lines are made cyclically therefrom in 25 when the connected lines operate the character format memory to be entered at different speeds. This worked out. If this character format contains the entire character, then speeds can be between 50 and 400 baud, it is sent to the character memory 21 and from there via the output. The number of samples or partial character elements can also be transferred to the bus 15 via the buffer line 15. To be different for a drawing element, for different speaking ways, the conversion takes place over the one-30 speeds.

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3 sheets of drawings