CH660102A5 - DEVICE FOR GENERATING PSEUDO RANDOM bit sequences. - Google Patents

Description

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PATENT CLAIM Device for generating pseudo random bit sequences of a scrambling circuit (4) with seven successive logical blocks (A1-A7), which are driven synchronously with a signal of a predetermined frequency and which each assume the logical level of the associated input at their output, the input signal is applied via a set / reset line (30), the output of the first, second, third, fourth, fifth, sixth block each being connected to the input of the second, third, fourth, fifth, sixth, seventh block and the outputs of the sixth and seventh blocks are connected to the inputs of an EXCLUSIVE-OR gate (5), the output of which is connected to the input of the first block (AI), and there is also a logic circuit to connect four discrete lines (T1 -T4), which carry a binary coded information with a frequency equal to the frequency mentioned, to a line for the transmission of binary codes ignalen with a frequency which is about four times greater than the frequency mentioned, which logic circuit has four AND gates (6-9) with two inputs, the first inputs of which are each coupled to one of the four lines mentioned, and the second inputs thereof receive a synchronization signal from a line (S), further four gate circuits (16-19) with at least two inputs, the first input of which has one output of one of the AND gates (6-9) and the second input of which has one of the outputs (G1-G3) of said scrambling circuit (4) is connected, and finally there is a multiplexer (1) with four inputs, each of which is coupled to the output of the first, second, third and fourth gate circuits (16-19) and whose output (A) is connected to a transmission line, characterized in that a fifth gate circuit (20) is provided with three inputs, each with one of the outputs (Q1, Q4, Q6) of the said first, fourth and sixth blocks (AI, A4, A6) are connected and their output is connected to the second input of the first gate circuit (16), further a sixth gate circuit (21) whose input is connected to the output (Q6) of the sixth block (A6) and whose output is connected to the second input of the second gate circuit (17), further a seventh gate circuit (22) with three inputs, each with an output (Q2, Q4, Q5) of the second, fourth and fifth blocks (A2, A4 , A5) and whose output is connected to the second input of the third gate circuit (18), further an eighth gate circuit (23) with two inputs, each with an output (Q2, Q5) of the second and fifth blocks (A2, A5) and whose output is connected to the second input of the fourth gate circuit (19), further characterized in that the set / reset line (30) with a third input of the fourth gate circuit (19) and further with the set inputs (S) the first, third, fourth, sixth and seventh blocks (AI, A 3, A4, A6, A7) and with the reset inputs (R) of the remaining two blocks (A2, A5).

The present invention relates to a device for generating pseudo random bit sequences according to the preamble of the single claim.

A known device of this type is shown in Fig. 1. This device has a self-synchronizing parallel scrambler 3, to the inputs of which four lines are connected, which deliver data T1, T2, T3, T4 with a frequency of 141 Mbit / s, and whose four outputs are connected to a multiplexer 1 which is clocked by a clock oscillator 2 with a frequency of 565 MHz. A frequency divider 2a is connected to the clock oscillator 2 in order to generate a clock frequency of approximately 141 MHz for the scrambler. The data TI, T2, T3, T4 are scrambled at the output A of the multiplexer 1 and are applied to a transmission line at a frequency of 565 Mbit / s.

The scrambling circuit 3 of the device according to FIG. 1, however, has two known disadvantages, namely

1) Line errors are multiplied by three;

2) additional control logic is necessary to reduce the possibility that long recurring sequences of successive bits with the logic level “0” occur.

In order to overcome the disadvantages mentioned under 1) and 2), the known and e.g. resettable scrambler recommended by the German and French telecommunications administrations, the block diagram of which is shown in FIG. 2.

The actual scrambling circuit is designated by 4 in FIG. 2a and is actually a source of a pseudo-random bit sequence. This source or generator consists of seven identical, successive blocks or flip-flops A1, A2, A3, A4, A5, A6 and A7, with D, Q, Ck, PR being the input, the output, the clock input, which of divider 2a received clock pulses with a frequency of approximately 141 MHz, and designated the set input.

The outputs Ql, Q2, Q3, Q4, Q5 and Q6 are directly connected to the D inputs of blocks A2, A3, A4, A5, A6, AI, while the outputs Q6 and Q7 of blocks A6 and A7 are connected with an EXCLUSIVE OR gate 5 are connected, the output of which is connected to the D input of block AI.

The data T1, T2, T3, T4 arrive together with the synchronization signal S at AND gates 6, 7, 8, 9. The outputs of these AND gates are each connected to an input of gate circuits 16, 17, 18, 19, the second inputs are connected to the outputs Q2, Ql, Q7, Q5 of the blocks A2, AI, A7, A5. The outputs c, d, e, f of the gates 16, 17, 18, 19 are connected to corresponding inputs of the multiplexer 1.

The multiplexer 1 delivers at its output A the data present at its inputs, specifically under the control of a logic circuit 10 and in accordance with the truth table H1 from FIG. 2b. It should be noted that the input a of the logic circuit 10 is connected to the output Q of the first of two flip-flops IIa, which together form the frequency divider 2a, while the input b of the logic circuit 10 is connected to the output of an AND gate 12, at its two inputs there is the synchronization signal S and the output signal obtained from the Q output of the second flip-flop IIa of the divider 2a.

The mode of operation of the circuit according to FIG. 2a can easily be found in the truth table H2 from FIG. 2b.

In this table, the first column indicates the elementary times t, which are determined by the clock signals supplied by the divider 2a. Columns 2-8 indicate the logic level of the outputs Q1-Q7, the ninth column indicates the logic level of the set signal PR, the tenth column the logic level of the synchronization signal S, the columns 11 to 14, the signals Gl, G2, G3 , G4 of the source 4 used for the scrambling, and finally the columns 15-18 indicate the logic levels of the signals which are in this order, ie from the fifteenth to the eighteenth column, appear at output A of multiplexer 1.

At elementary time 0, the set signal is at “0” and signal S is also at “0”. The outputs of blocks A1-A7 are «1», i.e. The logic levels of inputs c, d are present at output A, as can be seen from table Hl.

With the second and third clock pulse, the set signal is at "1", while the signal S is at "0", as a result of which the logic levels present at the inputs c, d are sequentially applied to the output A. Through the three clock pulses er5

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the frame sync word F appears at output A (FIG. 2b, table H2), which is known to be 11 1 110100000.

At the fourth clock pulse, the signal S is at “1”, as a result of which all four outputs Q2, Ql, Q7, Q5 of blocks A2, Al, Al, A5 are used to carry out the scrambling of the data signals TI, T2, T3, T4 Table H2 can be seen from the fourth line in columns 15-18. The device shown in FIG. 2a, in addition to overcoming the disadvantages 1) and 2), which the device according to FIG. 1 has, has the great advantage that it generates the frame sync word F in plain text by resetting.

However, this known reset scrambling circuit has a major disadvantage. If the signals T1, T2, T3, T4 are periodic, in particular if T1 = T2 = T3 = T4 = "0", the multiplex signal at output A does not represent a pseudo-random bit sequence with a period 27-l, but one Follow with an approximate randomness, which is very disadvantageous, because in these cases too, a sequence should be obtained that is as random as possible.

It is an object of the present invention to provide a device for generating pseudo random bit sequences of the type specified above, which is designed such that a multiplex signal appears at its output, which consists of a pseudo random bit sequence with a period of 27-1 appears, even in the case when the data signals T1, T2, T3, T4 have the logical level “0” at the same time, the frame sync word 111110100000 should appear in plain text.

This problem is solved by the features mentioned in the characterizing part of the single claim.

An embodiment of the invention will now be explained in more detail with reference to the drawing.

The drawing shows:

1 shows the block diagram of a known and already briefly described device for generating pseudo-random bit sequences;

2a shows the block diagram of a further known and already described device for generating pseudo-random bit sequences;

2b the truth tables of the logical blocks of the device according to FIG. 2a;

3 shows the block diagram of a device according to the invention for generating pseudo random bit sequences; and FIG. 4 shows the truth tables for the most significant blocks of the device according to FIG. 3.

From the comparison of Fig. 2a and Fig. 3 it is easy to see that the logical blocks designated 1, 2, 4, 2a, IIa, IIb, 10, 6, 7, 8, 9, 16, 17, 18, 19 are the same in both figures and therefore bear the same reference numerals.

The set / reset line 30 of FIG. 3 is connected to the set inputs of blocks AI, A3, A4, A6, AI and to the reset inputs of blocks A2, A5.

According to the present invention, four further gate circuits 20, 21, 22, 23 are arranged between the four gate circuits 16, 17, 18, 19 and the generator 4, which are connected in the manner shown in FIG. 3 and are described in more detail below.

The fifth gate circuit 20 has three inputs which are connected to the outputs Q1, Q4, Q6 of the blocks AI, A4, A6, while their output is connected to the second input of the first gate circuit 16, the first input of which is connected to the output of the AND -Tores 6 is connected.

The sixth gate circuit 21 has a single variable input which is coupled to the output Q6 of block A6, while its output is connected to the second input of the second gate circuit 17, the first input of which is connected to the output of the AND gate 7.

The seventh gate circuit 22 has three inputs which are connected to the outputs Q2, Q4, Q5 of the blocks A2, A4, A5, while their output is connected to the second input of the third gate circuit 18, the first input of which is the output of the AND -Tores 8 is connected. The eighth gate circuit 23 has two inputs connected to the outputs Q5, Q2 of the blocks A5, A2, while its output is connected to the third input of the third gate circuit 19. The first input of this gate circuit is connected to the output of the AND gate 9 and its second input is connected to the set / reset line 30.

From the truth tables K1, K2, K3 of FIG. 4, which belong to the blocks A7-A1, the AND gates 6-9 and the gate circuits 16-23, and from the consideration of the connections of these different logic blocks to one another, the Operation of the present device can be seen, the truth table is given at K4 of Fig. 4.

The gate circuits 16-23 can be realized with EXCLUSIVE OR gates. The basic shape of such a gate and the associated truth table are shown in Table 4 in Table K3. In order to obtain the link required in table K4, two EXCLUSIVE-OR gates connected in cascade are required per gate circuit, the output of the first gate being connected to one of the inputs of the second gate. The second input of the second gate is the third variable input for the gate circuits 19, 20, 23, while it is continuously the one logic level, e.g., for the gate circuits 16-18 and 23 with two variable inputs. Receives "0". In the gate circuit 21 with only one variable input, the second input of the first gate and the second input of the second gate are continuously at the other logic level, e.g. "1" connected. In Fig. 3 only those inputs of the gate circuits are shown that receive a variable signal.

The gate switching with two inputs Hessen can of course also be realized with a single EXCLUSIVE-OR gate and those with only one input with two inverters in series. Since the present device is operated with a rather high bit frequency, it is advantageous, however, to have the same number of gates connected in series for all signal paths in order to obtain the same signal transit times. Commercially available integrated circuits with four EXCLUSIVE-OR gates each can be used, e.g. Series MC 14 .. or MCA 12 .. from Motorola.

The elementary clock time t generated by the divider 2a operating at approximately 141 MHz is indicated in the first column of table K4, the second column shows the logic level of the signal present on the set / reset line 30, and the logic level in the third column of the synchronization signal S, columns 4-10 indicate the logic levels of outputs Q7-Q1, columns 11 to 14 indicate the logic levels of outputs PI, P2, P3, P4 of gate circuits 20, 21, 22, 23 and columns 15-18 indicate the logic levels of inputs c, d, e, f of multiplexer 1. At time t = 0, S is at “0” and S / R is at “0”, the outputs PI, P2, P3, P4 are at the level “0” and the zero point of the timing is set. In the situation mentioned, the inputs c, d, e, f all have the level “1”.

The connections of the gate circuits 20, 21, 22, 23 to the source 4 have the effect that at time t = 1, at which S and S / R are each at “0”, the outputs PI, P2, P3, P4 are at the levels «1010» are which levels are present at the inputs c, d, e, f at the same time.

At time t = 2, at which S is still "0", but S / R goes to "1", the connection scheme of the gate circuits 20, 21, 22, 23 to the source 4 mentioned above causes the outputs PI , P2, P3, P4 at the logical levels «0001»

are while the inputs c, d, e, f are each at the logic level «0», that is to say «0000». It should be noted that the fourth bit at input f does not have the "1" level of output

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P4 coincides because level "1" is present on line 30 at the second input gate circuit 19.

The three sequences of four bits at output A of multiplexer 1 result in the frame synchronization word, which is known to be “111110100000”.

The logic level «1» of S / R at time t = 2 defines a predetermined combination of logic levels at the outputs Q7, 6, 5, 4, 3, 2, 1 for the time t = 3 of the clock (see line 4 from table K4), which combination, together with the fact that S / R is at “0” and S at “1”, starts the scrambling process for the signals T1, T2, T3, T4 (see inputs c, d, e, f from line 4).

The introduction of the gate circuits 20, 21, 22, 23 and the special connection scheme of these gates to the outputs of the blocks A7-A1 enables a multiplex signal with a frequency of approximately 565 MHz to be output at the output A of the multiplexer 1 is obtained, which also enables a pseudorandom bit sequence with a period of 27-1 for the case that Tl = T2 = T3 = T4 = «0».

Finally, the coupling of the set / reset line 30 with an input of the gate circuit 19 and the connec-lo development scheme of this line with the set or. Reset inputs of blocks A7-A1 that the frame sync word is received in plain text.

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4 sheets of drawings