CH714180A2 - Converter for the transmission of electrical energy between a DC and an AC system. - Google Patents

Abstract

The invention relates to a converter for transmitting electrical energy between a DC (DC) system and an AC system. On the DC side, it has a positive DC input voltage rail (1) and a negative DC input voltage rail (2) and at least two output phase terminals (a, b, c) on the AC voltage side. In this case, there is a phase converter for each of the output phase terminals (a, b, c), which on a first side to the positive DC input voltage rail (1) and the negative DC input voltage rail (2) and on a second side to this output phase terminal (a ; b; c) is connected and designed as a boost / buck converter. The converter has a control which is designed, in the operation of the converter, to convert each of the phase converters, depending on a ratio of a DC input voltage to instantaneous values of output phase voltages to be generated at the output phase connections (a, b, c), either as a pure step-down converter or operate as a pure boost converter.

Description

Description The power electronic conversion of a DC voltage into a three-phase AC system (DC / AC conversion) is industrially e.g. in drive technology, in uninterruptible power supplies (UPS) and in the feeding of photovoltaic energy into the three-phase network wide application.

The input DC voltage level in this case has a relatively large fluctuation due to the typically strongly dependent on the state of charge terminal voltage electrochemical storage or fuel cells (drive technology or UPS) or due to the temperature dependence of the characteristic of solar cells (photovoltaic), so that the power electronic converter typically two stages, i. is performed with an input side DC / DC boost converter, a voltage intermediate circuit and an output side three-phase DC / AC converter (inverter) (see Fig. 1). In this way, the inverter, which in the end acts as a step-down converter in the case of power flow from the DC side to the three-phase AC side, can advantageously be designed for operation with a constant intermediate circuit voltage and thus with minimum construction output. Furthermore, the higher DC link voltage level compared with the DC input voltage makes it possible to generate a relatively high output voltage, which can be maintained independently of the battery state of charge, or can operate at photovoltaic systems regardless of irradiance and temperature at the point of maximum power delivery. In drive technology, the high DC link voltage offers the advantage of mastering a wide speed range of a powered AC machine.

By the inverter is generated from the DC link voltage, a three-phase pulse width modulated voltage system and placed in the realization of a variable speed drive in the simplest case directly to the motor terminals. However, this results according to the steep voltage edges a significant insulation load of the stator windings of the motor, further, the stator typically has a high switching frequency Rippei, which can lead to high rotor losses and thus due to the air gap limited cooling to a significant thermal load on the rotor. Furthermore, caused by the switching frequency common mode component of the machine terminal voltages bearing currents, which can lead to a destruction of the raceways of the bearing, to call disadvantageous. The mentioned disadvantages can be avoided by a three-phase LC output filter of the inverter, which suppresses switching-frequency harmonics of the pulse-width-modulated inverter output phase voltages and thus ensures a smooth, typically sinusoidal inverter output voltage characteristic.

For UPS systems, this LC output filter is to be arranged in any case, since the connected AC consumers i.A. must be supplied with a, deviating only slightly from a purely sinusoidal voltage. The same applies to photovoltaic applications, where the LC output filter is the first stage of an EMC filter intended to suppress the propagation of switching-frequency electromagnetic disturbances (currents) into the three-phase network.

In this context, it should be noted that the converter structure described above, even when the energy direction is reversed, ie for applications in which, starting from a three-phase mains voltage, a widely varying DC voltage must be generated, as e.g. in the battery charge of electric vehicles is the case, can be used. The DC / DC step-up converter then works as a DC / DC step-down converter due to the reversed direction of energy from the intermediate circuit voltage (it is antiparallel to the boost converter diode, a power transistor and antiparallel to the boost converter power transistor to provide a diode) and regulates the power flow from the DC link in the battery. The three-phase AC / DC converter acts as an active rectifier in this case and ensures a sinusoidal profile of the currents absorbed by the grid and a constant value of the DC link voltage.

However, the overall system with the inductance of the DC / DC boost converter, the DC link capacitor and arranged in each of the three output phases of the inverter filter inductance and filter capacitance on the whole a lot of passive components, resulting in a relatively high volume or relatively high realization costs are to be accepted. Furthermore, the two-stage energy transformation with regard to high energy efficiency is disadvantageous.

In the literature, therefore, single-stage DC / AC converters have been proposed which are formed of three identical bidirectional DC / DC phase converters having a common negative voltage rail and from the same DC supply voltage, three sinusoidally varying, phase-shifted, offset-biased, i. always produce positive voltages (phase converter output voltages) relative to the negative voltage rail. The unipolarity of the phase converter output voltages is formed by shifting a balanced phase in-phase load voltage system (which is ultimately to occur between the associated phase terminal and the free neutral point of the three-phase load to be fed) by a positive offset equal to the amplitude of the phase in-line load voltages. Thus, at the output of a phase converter, voltage values between twice the amplitude of the phase in-line load voltage and zero occur, so that in each phase in the general case both the operation with an output voltage level above the input voltage and below the input voltage must be mastered. As a phase converter Cuk Kon-verter are therefore proposed in corresponding publications with or without electrical isolation for the realization of the DC / DC converter.

Since the outside of the load between two positive output terminals of the Cuk DC / DC phase converter tapped outer conductor voltages correspond to the difference of the two associated phase converter output voltages, the same for all phases offset shift occurs in the occurring at the terminals of the three-phase load Außenleiterspannungen (Verbraucheraussenleiterspannungen) no expression, the external power supply voltages accordingly have a sinusoidal symmetrical course.

As a variant of the above-described generation of unipolar output voltages by continuous clocking of all three Cuk DC / DC phase converter, a control method is known for which a phase converter output each clamped for one third of the output voltage period on the negative voltage rail, wherein each phase is clamped with the most negative instantaneous value of the associated phase sinus load voltage and generate only the other two Cuk DC / DC phase converter clocks and output voltages such that compared to the clamped phase output sections of the respective outer conductor voltages are generated. Thus, a reduction of the switching losses of the system is possible, further occurs at the output of a phase converter at most the value of the amplitude of the fundamental to be formed Verbraucheraussenleiterspannung and not twice the value of the amplitude of the phase sink voltage.

For both control methods, the Verbraucheraussenleiterspannung shows a smooth course due to the arranged at the output of the Cuk DC / DC phase converter smoothing capacitors. A required for conventional inverter with pulse width modulated output voltage LC output filter (see above) can thus be omitted. However, nevertheless, a high implementation cost of the overall system is given, since instead of a boost converter inductance of the conventional two-stage system described above (see Fig. 1) now use three input inductances and instead of the DC link capacitance three capacitances as Kemelemente based on capacitive power transfer Cuk-DC / DC phase converter are. Furthermore, significantly higher blocking voltage loads, which are defined by the sum of input and output voltage of a phase converter and not either by the input voltage or the output voltage, and thus ultimately also high switching losses, occur at the power semiconductors. The well-known single-stage Cuk-based DC / AC converter is therefore only for consumers with relatively low effective value of Aus-senleiterspannung used and relatively low switching frequency feasible, which limits the possibility of increasing the switching frequency to minimize the size of the filter elements.

Furthermore, the control of the phase converter of the single-stage system has been carried out only einschleifig, resulting in view of the high number of energy storage or the high order of the systems, a clear limitation of the dynamics of the control of the phase converter output voltages and the Verbraucheraussenleiterspannungen, which especially for highly dynamic drives with requirements for rapid speed or voltage increase or reduction is disadvantageous.

The object of the invention is therefore to provide a converter for the transmission of electrical energy between a DC and an AC system which overcomes at least one of the above-mentioned disadvantages and has at least one of the following properties: that it in each phase can operate with overlapping input and output voltage range and generates continuous (filtered) output phase AC voltages that it has a minimum number of inductive elements that they are of small size, that one, preferably defined by the input or output voltage of the phase converter reverse voltage load and / or switching losses the power semiconductors are low, that it has a multi-loop control of the phase converter, so that a high dynamics of the control of the phase converter output voltages is given.

This object is achieved by a converter for the transmission of electrical energy between a DC and an AC system according to the claims.

The converter for transmitting electrical energy between a DC (DC) system and an AC (AC) system, the DC side has a positive DC input voltage rail and a negative DC input voltage rail and AC side at least two output phase terminals. In this case, there is a phase converter for each of the output phase terminals, which is connected on a first side to the positive DC input voltage rail and the negative DC input voltage rail and on a second side to this output phase terminal and is designed as a boost / buck converter. The converter has a control which is designed, during operation of the converter, to operate each of the phase converters, as a function of a ratio of a DC input voltage to instantaneous values of output phase voltages to be generated at the output phase terminals, either temporarily as a pure buck converter or as a pure boost converter.

Thus, the phase converter is not designed as a DC / DC Cuk converter, but as a multi-loop regulated low-set DC / DC converter, wherein the specification of the setpoints of the phase converter output voltages is such that on the one hand, a minimum maximum value of the output voltages is required and on the other hand results in a minimal fluctuation of the currents in the inductors of the phase converter. In this way, small inductance values can be selected for a given switching frequency, and small switching frequencies can be selected for given inductance values, or low switching losses can occur.

In embodiments, the scheme is adapted to restrict in the operation of the converter in each of the phase converter, a clocking of switches of the phase converter temporarily on an input side buck converter part or bridge branch or on an output side Hochsetzstellerteil or bridge branch of the phase converter.

In embodiments, the scheme is adapted to make in the operation of the converter, the timing of all phase converter such that for all phase converter the same clock frequency is present and a synchronization of the clocking of the converter minimizes a differential voltage contained in the output phase voltages.

In embodiments, the scheme is adapted to make the operation of the converter, the timing of all phase converter such that for all phase converter has the same clock frequency and a synchronization of the timing of the converter minimizes a common-mode voltage component contained in the output phase voltages.

In embodiments, the controller is configured to bias the converter to provide output phase voltage setpoints from load phase voltage setpoints such that a phase output voltage setpoint equal to zero results in each time period for the phase converter whose associated load phase voltage setpoint has the highest negative value whereby said phase converter need not be clocked and its output phase terminal may remain clamped to a reference voltage rail, and the course of the output phase voltage setpoints of non-clamped phase converters is defined by setpoint output voltage voltages to be generated across the clamped output phase terminal and subtracted from each of two load phase voltage setpoints in that time period so that a total of sinusoidal course of all Lastaussenleiterspannungen is present again.

In embodiments, the phase converters are each formed as a cascaded down-up converter (buck-boost converter).

In embodiments, the phase converters are each realized by a circuit in which a bridge branch is disposed between the positive DC input voltage rail and an associated output phase terminal, a phase converter inductance is connected between a midpoint of the bridge branch and the negative DC input voltage rail has an output capacitance between the output phase terminal and a common reference voltage rail is connected, which is connected to the DC input voltage rail.

In embodiments, in the phase converters, an output diode is connected in each case between the output phase connection and the reference voltage rail, which ensures a positive output phase voltage at the output phase connection with respect to the reference voltage rail.

In addition to the output diode, a switch can also be connected in parallel, or the output diode can be replaced by a switch with antiparallel output diode. Thus, the phase with the lowest voltage can each be clamped over one third of the period (no switching losses for this phase) and thus the converter efficiency can be increased.

In embodiments, the control is designed to select a constant offset of the output phase voltages during operation of the converter with relatively small amplitudes of the output phase voltages such that, on the one hand, a fluctuation of the output phase voltages caused by the load phase voltages to be generated is symmetrical about a level of the DC voltages. On the other hand, a double maximum amplitude of load phase voltages is not exceeded, this being achieved by lowering the offset at high amplitudes of the load phase voltages.

In the following, the subject invention based on preferred embodiments, which are illustrated in the accompanying drawings, explained in more detail. Each show schematically:

Fig. 1: Bidirectional three-phase buck-boost converter DC / AC converter system according to the prior art with input side DC / DC boost converter, DC link capacitor, output side voltage intermediate circuit three-phase inverter and downstream LC output filter for generating a smoothed three-phase AC output voltage.

Fig. 2: Converter system with arrangement of a respective DC / DC Tiefhochstellstellers per output phase, each phase converter has an input side and an output side bridge branch and arranged between the bridge arms, used for buck and boost converter operation phase converter inductance.

Fig. 3: Time characteristic of the phase converter output voltages to be generated during feeding of a three-phase machine for (FIG. 3.1) time-constant offset shift uoff of the load-phase voltage system actually to be generated in the amount of the amplitude of the load phase voltage; (Figure 3.2) with a constant offset shift and additional superimposition of an alternating component of the offset signal with three times the output frequency and a phase position such that the maximum value of the phase converter output voltages is minimized; (Fig. 3.3) at offset displacement of the load phase voltage system to be generated such that for a

Phase converter output over one-third of the output period a setpoint equal to zero, and this converter can therefore remain in the clamped state.

Fig. 4: execution of the phase converters with virtually minimal complexity, the output terminals of the phase converter show negative potential, and further to allow a simple run-up of the system, starting from the output terminals of the phase converter diodes are placed against the reference voltage rail. In each case, a diode in parallel with an output capacitor may have a parallel switch, this analogous to the circuit in Fig. 2 allows the clamping of the phase with the lowest voltage over one third of the period and thus reducing the switching / converter losses.

Fig. 5: Time characteristic of the setpoint values uout * of the phase converter output voltages uout (uout in summary the individual voltages uan, ubn, ucn are designated for the converter circuits of Fig. 2, which with respect to the DC input voltage Uin small amplitude UMpk the setpoints the load phase voltages uM * can be used to achieve a minimization of the switching-frequency fluctuation of the current in the phase converter inductance (see Fig. 5.1) .Figure 5.2 shows the time characteristic associated with the converter circuit according to Fig. 4, which alternative to Fig. 5.1 2uMpk, max denotes the maximum value of the phase converter output voltages uout occurring at the maximum load phase voltage amplitude, and the associated time profiles of uout are shown in dashed lines in each case.

Fig. 6: Device for controlling the output voltages of the phase converter to set a predetermined curve uM * the load phase voltages uM, as required for UPS systems or in the supply of variable speed three-phase machines. The regulation has the same structure for each phase and is shown for the sake of clarity only for one phase.

7 shows a device for regulating the DC output voltage formed in the interaction of all the phase converters when the converter system is used as a three-phase pulse rectifier circuit, whereby a subordinate control ensures a sinusoidal profile of the network phase currents, in each case in phase with the associated mains phase voltage. The regulation has the same structure for each phase and is shown for the sake of clarity only for one phase.

8: Modification of a part of the control devices according to FIG. 6 and FIG. 7.

9 shows an alternative embodiment of a part of the control circuit according to FIG. 6 to FIG. 8.

Each phase converter of the system (see Fig. 2) has a lying between the positive DC input voltage rail 1 and the negative DC input voltage rail 2 input side bridge branch 3a, 3b, 3c, which by series connection of an upper, typically collector or drain side connected to the positive DC input voltage rail and a lower, typically emitter or source side connected to the negative DC input voltage rail switch, generally a power transistor is realized, to both transistors, a freewheeling diode is connected in anti-parallel and the two transistors common circuit point (connection the emitter or source terminal of the upper and the collector or drain terminal of the lower transistor) forms the bridge branch output 4a, 4b, 4c, from which a phase converter inductance La, Lb, Lc branches off, which with its second end to the input 5a, 5b, 5c another exit side bridge arms 6a, 6b, 6c is set, wherein the source terminal of the lower switch or transistor of this bridge branch with a reference voltage rail n and the drain terminal of the upper transistor of this bridge branch with the associated output phase terminal a, b, c is connected, wherein to ensure a smooth course the output phase voltage between the output phase terminal and the reference voltage rail, a smoothing capacitance Ca, Cb, Cc is set. The reference voltage rail n common to all phase converters is finally connected to the negative rail 2 of the DC input voltage, whereby each phase converter advantageously has the structure of a low-boost converter DC / DC converter and the entire three-phase DC / AC converter system advantageously only three inductors La, Lb, Lc.

A three-phase load is connected with its phase terminals to the output phase terminals a, b, c of the three phase converter and has a free neutral point, so that only the concatenated phase converter output voltages (Lastaussenleiterspannungen), defined as the difference of two phase converter output voltages or from a load phase terminal determined against a Laststernpunkt measured load phase voltage, the formation of the load phase currents.

The phase converter output voltages are generated in such a way that the nominal values of the load phase voltages u_an, u_bn, u_cn, which typically have an output frequency sinusoidal and form a symmetrical three-phase system, are shifted to positive values by means of a temporally constant offset u_off in the simplest case (see FIG. 3.1). in that each phase output voltage is unipolar, ie only positive values or minimal shows the value zero. As mentioned above, this offset does not become effective in the load output voltages, and thus does not affect the current generation of the load. In embodiments, at this constant offset, another offset having three times the output frequency and an amplitude and phase may be added such that the unipolarity of the output phase voltages is ensured with a minimum value of the constant offset, whereby the voltage loading of the transistors of the output side bridge branches 6a, 6b , 6c the phase converter can be minimized at a defined load phase voltage amplitude to be generated (see Fig. 3.2).

With regard to the timing of the input and output side bridge branches 6a, 6b, 6c of the phase converter is to be noted that in areas in which a lying above the DC input voltage phase converter output voltage must be generated, the upper switch or power transistor of the input-side bridge branch 3a, 3b, 3c of a phase converter can remain switched through, and only the output-side bridge branch 6a, 6b, 6c is clocked. The voltage ratio of the converter then corresponds to a step-up converter for power flow from the DC input voltage to the phase converter output voltage, the phase converter inductance La, Lb, Lc as boost converter inductance, the lower power transistor of the output side bridge branch 6a, 6b, 6c as boost converter transistor and the antiparallel diode of the upper power transistor acts as a boost converter freewheeling diode, wherein in embodiments always the upper power transistor is turned on, ie the power transistors of the output side bridge branch 6a, 6b, 6c are operated in push-pull. Since antiparallel diodes are arranged to all power transistors, then a power flow from the phase converter output voltage to the DC input voltage can then take place, the function of the phase converter in this case corresponds to a lying between phase converter output voltage and DC input voltage buck converter.

In regions in which a phase converter output voltage lying below the DC input voltage has to be generated, in embodiments the upper power transistor of the output side bridge branch 6a, 6b, 6c of the phase converter remains switched through, and the timing is applied to the input-side bridge branch 3a, 3b, 3c limited. The voltage ratio of the converter then corresponds to a step down converter for power flow from the DC input voltage to the phase converter output voltage, the phase converter inductance as buck converter inductance, the upper power transistor of the input side bridge branch 3a, 3b, 3c as buck converter transistor and the lower power transistor antiparallel diode as buck converter flywheel diode acts, in embodiments always switched through the lower power transistor, ie the power transistors of the input-side bridge branch 3a, 3b, 3c are operated in push-pull. Since antiparallel diodes are arranged to all power transistors, then a power flow from the phase converter output voltage to the DC input voltage can then take place, wherein the function of the phase converter in this case corresponds to a lying between phase converter output voltage and DC input voltage boost converter.

With regard to the timing of all phase converter should be noted that in embodiments for all phase converter the same clock frequency is selected and a synchronization of the timing of the converter is such that the phase converter output voltages contained in the push-pull voltage component, which to switching-frequency currents and thus possibly to high-frequency losses in the connected three-phase load is minimized, ie switching frequency changes of the phase converter output voltages are mainly formed as common mode components, which cause a similar voltage shift relative to the reference voltage rail for all phase outputs.

For consumers, which are particularly sensitive to high-frequency common mode shifts, on the other hand, a synchronization of working again with the same clock frequency phase converter can be made such that the switching frequency common mode voltages are minimized, in which case, however, a higher push-pull component of the phase converter output voltages is to be accepted.

An alternative course to FIG. 3.1 and FIG. 3.2 is defined such that for the phase converter whose associated load phase voltage has the highest negative value, an output phase voltage setpoint equal to zero results (see FIG. 3.3), whereby this phase converter does not must be clocked, or the associated output phase terminal may remain clamped to the reference voltage rail, which for the above-described phase converter topology (see Fig. 2) can be achieved by simultaneously switching through the upper and lower power transistor of the output side bridge branch 6a, 6b, 6c. Advantageously, then the lower power transistor of the input-side bridge branch 3a, 3b, 3c durchzuschalten. The course of the output voltage setpoint values of the two other phase converters is then defined directly by the sections of the setpoint values of the load outer conductor voltages to be generated in relation to the clamped phase and formed by subtracting two load phase voltage setpoint values, so that a total sinusoidal profile of all three load external conductor voltages is again achieved. Since the clamping is passed cyclically between the phases, each phase remains clamped for a third of the load phase voltage period when generating a sinusoidal balanced load phase voltage system and thus without switching losses, thus increasing the efficiency of energy transfer is achieved.

With regard to the realization of the phase converters, it should be noted that in addition to the embodiment described above there are a number of advantageous modifications: In embodiments, the input and / or output side bridge branch can advantageously be designed in a multi-level structure, e.g. be performed as Flying Capacitor Multilevelbrückenzweig, whereby for the adjustment of the voltage ratio between DC input voltage and phase converter output voltage, a higher number of voltage levels is available, whereby a lower switching frequency Rippei the currents in the phase inductances occurs.

Furthermore, in embodiments, the phase converters can be realized by a plurality of parallel, out of phase clocked systems, whereby the power fed into the output capacitance and the current drawn from the DC input voltage compared with a single system advantageously has a higher effective frequency and a smaller variation.

A converter system in embodiments with phase converters of relatively low complexity is shown in Fig. 4, wherein in each phase for the realization of the bidirectional DC / DC Tiefhochstellstellers only a bridge branch between the positive terminal of the DC input voltage and the associated output or Load phase terminal is arranged and the associated phase converter inductance is connected from the center of the bridge branch to the reference voltage rail. Depending on the function, the reference voltage rail then has positive potential or the output terminals of the phase converter exhibit negative potential, which must be taken into account when specifying the setpoint values of the output phase voltages (ie, the voltage count is made against the phase terminals starting from the reference voltage rail).

In order to enable a simple run-up of the system can be placed in embodiments, further starting from the output terminals of the phase converter diodes against the reference voltage rail. Corresponding to a clamp circuit, in the presence of an active three-phase load or when connecting a three-phase network instead of a three-phase load, a polarity reversal of the phase converter output voltages is inhibited and a positive output voltage is ensured in a wide interval of the output period without clocking the power transistors, which can be used for booting up the system. In addition to each output diode, a switch can also be connected in parallel in each case, or the output diode can be replaced by a switch with antiparallel output diode. Thus, as for the circuit of FIG. 2, the phase with the lowest voltage can be clamped over one third of the period (no switching losses for this phase) and thus the converter efficiency can be increased.

It should be noted that for phase converter with an input and output side bridge branch (see Fig. 2), the freewheeling diodes of the output side bridge branch act as clamping diodes during startup and therefore no explicit further diodes are provided.

For use of the system of FIG. 2 or FIG. 4 for feeding a three-phase machine (load) located at the output phase terminals, different amplitudes of the load phase voltage or different amplitudes of the associated phase converter output voltages are to be generated depending on the speed of the machine, typically At highest speed, the highest amplitude values occur, for which the power semiconductors of the output-side bridge branch are to be designed.

Advantageously, for the circuit of Fig. 2 at low speeds, or relatively small amplitudes of the phase converter output voltages, the constant offset can be chosen so large that on the one hand, caused by the load phase voltages to be generated fluctuation of the phase converter output voltages symmetrically about the level of DC input voltage comes to rest, and on the other hand, the maximum speed associated with twice maximum amplitude of the load phase voltage is not exceeded, this being achieved by lowering the offset correspondingly at high amplitudes of the load phase voltages. As shown in Fig. 5.1, the setpoint values of the phase converter output voltages then typically have minimum values significantly greater than zero, and the currents in the phase converter inductors exhibit a relatively low ripple, since then the input and output side bridge branches operate alternately at duty ratios close to one (ie each upper power transistors are almost constantly through-connected), which is known to result in a low switching-frequency fluctuation of the current in the phase converter, which in turn finds expression in low high-frequency losses. Even taking into account the then due to the higher switched phase converter output voltage higher switching losses of the output side bridge branch thus an improvement in the efficiency of energy transfer can be achieved.

For the circuit of Fig. 4, in contrast to Fig. 5.1, the phase converter output phase voltages are always as low as possible, i. The constant offset regardless of the amplitude of the load phase voltage or machine speed to keep as small as possible, so only to choose so large that zero occurs as a minimum voltage value (see Fig. 5.2). This is because then the upper power transistors of the input side bridge branches of the phase converters have low duty cycles, again resulting in a small variation in the currents in the phase converter inductors.

A cascaded control of the three-phase converter system of Fig. 2 is shown in Fig. 6. The control circuit is similar for each phase and shown in the interest of clarity only for one phase. Voltages are measured as registered with respect to the reference voltage rail n or the negative rail DC- of the DC input voltage Uin.

The setpoint of a phase converter output voltage uout * is formed by adding the typically sinusoidal setpoint value uM * of the associated load phase voltage uM a fed three-phase load (eg an electric machine M) and the same for all phases setpoint uoff * of the offset uoff, which typically by Addition of a constant portion over the output period uoffDC * and a three times the output frequency fluctuating portion uoffAC * is generated. Advantageously, the time course of uoff * is chosen such that uout * remains limited to the lowest possible values for a given prior to generating load phase voltage system uM *, whereby the reverse voltage stress and the switching losses of the output side bridge branches BB of the phase converter are minimized. This includes a default of uoff * such that one phase converter each remains in the clamped state for one-third of the output period, i. uout * has correspondingly broad intervals with uout * = 0.

The phase converter output voltage setpoint uout * is compared with the measured actual value of the phase converter output voltage and the deviation Deltauout fed to a phase converter output voltage regulator Ruout, at the output of the required to correct delta output output capacitor current setpoint iCout * is formed, which by pre-control of the measured associated load phase current iLoad determines the output current i of the output side bridge branch BB of the phase converter, which can be converted by dividing by the relative duty cycle dB of the upper transistor T3 of this bridge branch into a desired value iL * of the current iL in the phase converter inductance L. By comparing iL * with the measured actual value iL, the deviation DeltaiL of the current is then formed in L and fed to a phase inductance current regulator RiL, which at its output forms the desired value uL * of the voltage to be applied to L for correcting the deviation DeltaiL.

Starting from the assumption of an operation with continuously switched-through upper transistor T3 of the output side bridge branch BB, which is characterized by the occurrence of uout at the input terminal B of BB and thus also at the output end of L, then the setpoint uA * is the to be applied to the input-side end A of L or to be generated at the output A of the input-side bridge branch BA to be generated voltage uA by adding uL * and uout. The duty cycle dA, i. the duty ratio of the upper transistor T1 of BA is then simply obtained in the sense of a buck converter function of BB by dividing uA * and the actual value of the DC input voltage Vin.

Since dA is limited to values between zero and one, uA * is to be limited correspondingly upwards by Uin and downwards by the value zero. Advantageously, according to this limitation, the relative duty cycle of the bridge branch BB can be easily generated by subtracting from uA * the measured DC input voltage Uin. The difference delta uA * thus obtained is limited downwards by the value zero and upwards by uout, which corresponds to the physically adjustable limits of uA. If a positive value DeltauA * now occurs, this ultimately means that BB can not generate the voltage value uL * to be generated via L for correct current regulation, even with maximum modulation of BA with dA = I or uA = Uin. Correspondingly, then, the input B of BB may not further have the duty ratio dB = I or T3 may no longer remain permanently in the through-connected state as assumed above. The input B is thus voltage-wise to lower DeltauA *, or ultimately a desired value uB * of the voltage to be generated at B according to a subtraction of the limited value of uA * of uout, the duty cycle dB of BB then with respect to the buck converter function from BB from uout to uB by dividing uB * by uout.

For values of the DC input voltage Uin above uout *, the converter system is then predominantly in buck converter mode, i. work with BA timing, BB will remain on continuously with dB = I or T3. Only with rapid transient changes of uout * or iLoad will a temporary clocking of BB occur.

However, the control circuit according to FIG. 6 also controls the operation for voltages Uin <uout, since the activation of the bridge branches BA and BBja is derived directly from the desired value uL * and the actual values uout and Uin. Advantageously, the control circuit is therefore independent of the respective ratio of Uin and uout * and also for both power flow directions, i. for supplying a motor M Uin or feedback of braking energy of the motor M can be used in Uin.

The drive signals of the push-pull operated bridge arms BA and BB are obtained from dA and dB by appropriate pulse width modulation.

As mentioned above, the converter circuit on the one hand for supplying an electric machine M, on the other hand, but also as a three-phase rectifier system with advantageously sinusoidal mains currents iN and a regulated to a constant value DC output voltage Uout can be used.

As shown in Fig. 7, then, using as much as possible the designations introduced in connection with Fig. 6, the positive outputs of the phase converters are to be connected and connected to the positive terminal DC + of an output capacitor Cout common to all phases, its negative rail DC- with the reference voltage rail n, against which the input-side bridge branches BA are connected. Furthermore, the inputs of the bridge branches BA of the phase converters, which are all located at the positive terminal of the DC input voltage for FIG. 6, are now carried out separately and are conducted via phase connection inductances LN to the terminals aN, bN, cN of the three-phase network N. Furthermore, in each phase converter, a filter capacitor Cin is connected in parallel to the respective input-side bridge branch BA from the respective input terminal a, b, c against the common reference voltage rail n for all phase converters.

For the regulation of Vout, the difference between the DC output voltage setpoint Uout * and the measured value uout is formed and the control deviation Deltauout is fed to an output voltage regulator Ruout which is common to all phase converters and at its output the required current value iCout for a corresponding charge change of Cout * to which the measured value iLoad of the current flowing to a DC consumer RLoad is advantageously added in order to obtain the desired value iout * of the output current iout (total of the output currents i of the output-side bridge branches BB) to be formed in total by the parallel connection of the phase converters. By multiplying by Uout *, a nominal value pout * of the converter output power is then obtained and assuming a symmetric and sinusoidal characteristic of the mains phase voltages uN by dividing by the threefold square of the amplitude UNpk of a mains phase voltage and dividing by 2, 3/2 UNpkA2, into the nominal value of The equivalent conductance G * of the phase branches of a resistor replacement star connection, which is to be represented by the converter system for the network in order to ensure an ohmic network behavior, is converted. By multiplying G * by the measured value of the assigned mains phase voltage uN, it is then easy to obtain the desired value iN * of the line phase current iN to be obtained from the respective phase converter, from which the measured value iN of the mains phase current is subtracted in order to obtain a system deviation DeltaiN which corresponds to a line current controller RiN is supplied, which generates at its output the setpoint uLN * of the voltage to be generated over the associated Phasenvorschaltinduktivität LN uNN which is to be subtracted from uN to get the setpoint uinY * to be generated at the input of the phase converter relative to the Netzsternpunkt Y phase voltage uyY to which a setpoint value of a same offset for all phases, uoff, is added to obtain the setpoint value uin * of the phase converter input voltage uin related to the reference voltage rail n. The offset setpoint uoff * is typically generated by adding a constant component uoffDC * over the network period and a component uoffAC * fluctuating with three times the network frequency, and is designed such that uin * is limited to the lowest possible values uN * for a given mains phase voltage system, whereby the reverse voltage stress and the switching losses of the input side bridge branches of the phase converter can be minimized. This includes a specification of uoff * such that in each case a phase converter remains in the clamped state for one third of the output period, in which case the associated uin * has correspondingly broad intervals with uout * = 0.

The phase converter input voltage setpoint uin * is then compared with the measured actual value of the phase converter input voltage uin and the control deviation Deltauin fed to a phase converter input voltage controller Ruin, at whose output required for the correction of delta input capacitor current setpoint iCin * is subtracted from the setpoint iN * of the associated network phase current to obtain the set value iin * of the input current iin of the input-side bridge branch BA of the phase converter. By dividing iin * by the duty ratio dA of the upper transistor of BA, the setpoint value iL * of the current iL in the phase converter inductance L can then be obtained. The comparison (subtraction) of iL * with the associated measured value iL then leads to the control deviation DeltaiL of the current in L which is supplied to a Phaseninduktivitätsstromregler RiL, at its output the setpoint uL * the voltage to be applied to correct the deviation DeltaiL L to be laid forms. The remaining control circuit between iL * and the relative turn-on durations dA and dB of the bridge branches BA and BB is the same as for the circuit of FIG. 6, for which reason a description can be omitted here.

The control circuit of FIG. 6 and FIG. 7 assumes a buck converter operation of the input-side bridge branch BA and a through-connected state of the transistor T3 of the output side bridge branch BB as a regular operation, but also the case of a lying above the input voltage output voltage of a phase converter, ie the boost converter operation is mastered.

Alternatively, the boost converter operation of the converter, i. a steady state of T1 and clocking of the bridge branch BB are considered to be regular operation, thus resulting in the alternative embodiment shown in Fig. 8 of a part of the control circuits of Fig. 6 and Fig. 7. The remaining parts of the control circuits remain unchanged. The following description is therefore limited to the part of the already described devices to be replaced.

For determining the relative turn-on of the bridge arms BA and BB, the setpoint uL * is inverted and then adds this physically-from the output side to the input side directed voltage -uL * to the input voltage uin the phase converter and so to be set at input B of BB voltage setpoint transmitted. After limiting to uout up and zero down - it is only possible to set dB between zero and one - so the duty cycle, i. obtained the duty cycle of the upper transistor T3 of BB.

In order to be able to set the required voltage uL * even when uB * exceeds the value uout, the difference delta uB * of uB * and uout is furthermore determined and after limitation with uin up and zero down from the input voltage subtracted. This follows the consideration that to set a desired value uL * which leads to uB * = uout or db = I, the output A of the bridge branch BA must be released from the input voltage and lowered in potential by appropriate timing. The duty cycle dA to be set then can be obtained simply by dividing uA * by uin.

For values of the input voltage u in which are below uout, then the converter system is operated predominantly in boost converter mode, i. work with BB timing, BA will remain on continuously with dA = I or T1. Only in case of rapid transient changes of uin * or iLoad will BA temporarily be clocked. However, the control circuit also controls the operation for voltages uin> uout, since the activation of the bridge branches BB and BA yes directly from the setpoint uL * (and the actual values uin and uout) is derived. Advantageously, the control circuit is therefore independent of the respective ratio of uin and uout and also for both power flow directions, i. for supply of a motor M from uin, or for realization of a photovoltaic inverter for feeding photovoltaic generated power (uin then represents the voltage of the solar panel) or for the recovery of braking energy of a three-phase motor M in the DC input voltage uin, or for the operation of the Device can be used as an active three-phase rectifier system (generation of a DC output voltage uout).

An alternative embodiment of a part of the control circuit according to FIG. 6, which is used to calculate the duty cycles dA and dB, in contrast to the two control concepts according to FIGS. 6 to 8, both modes of operation, ie. Buck and boost operation, equally favored, is shown in FIG. On the one hand, for the bridge branch BA, a bucking operation is assumed, i. it is assumed that the bridge branch BA is clocked and, on the other hand, a bridge operation is assumed for the bridge branch BB, i. it is assumed that the bridge branch BB is clocked. In order to obtain the setpoint voltage uA * of the bridge branch BA, the setpoint value uL * is added to the output voltage uout and limited up to uin and down to zero. Conversely, for the calculation of the setpoint voltage uB * of the bridge branch BB, the setpoint value uL * is subtracted from the input voltage uin and limited up to uout and down to zero. By this mutual offset of the output voltage uout in the target voltage uA * and the input voltage uin in the target voltage uB * and the corresponding limitation on the possible adjustment range, the two modes are finally excluded from each other, i. The converter works despite initial consideration of both modes, either in pure buck or pure boost mode. The duty cycle dA and dB to be set can then be obtained simply by dividing uA * by uin or uB * by uout.

Claims (22)

claims A converter for transmitting electrical energy between a DC (DC) system and an AC (AC) system, comprising on the DC side a positive DC input voltage rail (1) and a negative DC input voltage rail (2) and AC side at least two Output phase terminals (a, b, c), wherein for each of the output phase terminals (a, b, c), a phase converter (10a, 10b, 10c) is present, which on a first side to the positive DC input voltage rail (1) and the negative DC Connected to this output phase terminal (a; b; c) and formed as a step-up / step-down converter, and wherein the converter has a control, which is designed, in the operation of the converter, each of the Phase converter (10a, 10b, 10c), in response to a ratio of a DC input voltage to instantaneous values of at the output phase terminals (a, b, c) eugenden output phase voltages, temporarily operated either as a pure buck converter or as a pure boost converter. 2. Converter according to claim 1, wherein the scheme is adapted to the operation of the converter in each of the phase converter (10a, 10b, 10c) a timing of switches of the phase converter (10a, 10b, 10c) temporarily on an input side subcircuit part or bridge branch or to restrict to an output-side boost converter part or bridge branch of the phase converter (10a, 10b, 10c). 3. Converter according to claim 1, or 2 wherein the scheme is adapted to make the operation of the converter, the timing of all the phase converter (10a, 10b, 10c) such that for all phase converter (10a, 10b, 10c) is the same clock frequency and a Synchronization of the clocking of the converter to minimize a differential voltage contained in the output phase voltages to minimize. 4. Converter according to claim 1, or 2 wherein the control is designed to perform the operation of the converter, the timing of all phase converter (10a, 10b, 10c) such that for all phase converter (10a, 10b, 10c) is the same clock frequency and a Synchronization of the clocking of the converter minimizes a common-mode voltage component contained in the output phase voltages. 5. Converter according to one of the preceding claims, wherein the control is adapted to specify during operation of the converter, an offset to form output phase voltage setpoint from load phase voltage setpoints, such that in each time period for that phase converter (10a, 10b, 10c), whose associated Load phase voltage setpoint has the highest negative value, an output phase voltage setpoint equal to zero results, so this phase converter (10a, 10b, 10c) must not be clocked and its output phase terminal (a; b; c) may remain clamped to a reference voltage rail (s), and the course the output phase voltage setpoint of non-clamped phase converters is defined by setpoint values of load output voltage voltages to be generated relative to the clamped output phase connection and formed by subtracting in each case two load phase voltage setpoints in this time segment, so that a total of s Inusförmiger course of all Lastaussenleiterspannungen present. 6. Converter according to one of claims 1 to 4, wherein the control is designed to select a constant offset of the output phase voltages so large during operation of the converter at relatively small amplitudes of the output phase voltages, that on the one hand, caused by to be generated load phase voltages fluctuation of the output phase voltages symmetrically about a level of the DC input voltage, and on the other hand a two-fold maximum amplitude of load phase voltages is not exceeded, this being achieved by lowering the offset at high amplitudes of the load phase voltages. 7. Converter according to claim 6, wherein the control is adapted to superimpose a third harmonic in addition to the constant offset. 8. Converter according to one of the preceding claims, wherein the phase converter (10a, 10b, 10c) are each formed as a cascaded down-up converter (buck-boost converter). 9. A converter according to one of claims 1 to 5, wherein the phase converters (10a, 10b, 10c) are each realized by a circuit in which a bridge branch between the positive DC input voltage rail (1) and an associated output phase terminal (a; b; c), a phase converter inductance (La, Lb, Lc) is connected between a midpoint of the bridge branch and the negative DC input voltage rail (2), an output capacitance (Ca, Cb, Cc) between the output phase terminal (a; b; c) and a common reference voltage rail (s) connected to the DC input voltage rail (2). 10. Converter according to claim 9, wherein in the phase converters (10a, 10b, 10c) in each case an output diode (Da, Db, De) between the output phase terminal (a; b; c) and the reference voltage rail (s) is connected which a positive Ensure output phase voltage at the output phase terminal (a; b; c) with respect to the reference voltage rail (s). 11. A converter according to claim 9 and 10, wherein in which the phase converters (10a, 10b, 10c) each in parallel with the output diode (Da, Db, De), a switch is connected in antiparallel or is replaced by a bidirectional switch. 12. A converter according to claim 9 and 11, wherein the control is designed to always choose a constant offset of the output phase voltages equal to the amplitude of the load phase voltage during operation of the converter. 13. A converter according to claim 9 to 12, wherein the control is adapted to superimpose a third harmonic in operation of the converter in addition to the constant offset, wherein the ratio of constant offset and the amplitude of the third harmonic can be freely selected and the sum the two components are always chosen so that the minimum output phase voltage just reaches the potential of the negative DC input voltage rail. 14. A converter according to claim 11, wherein the controller is designed to provide an offset for the formation of output phase voltage setpoints from load phase voltage setpoint values during operation of the converter, such that in each time period for the phase converter (10a, 10b, 10c), whose associated load phase voltage setpoint the has the highest negative value, an output phase voltage setpoint equal to zero results, which means that this phase converter (10a, 10b, 10c) does not need to be clocked and its output phase terminal (a; b; c) can remain clamped to a reference voltage rail (s) and the waveform of the output phase voltage setpoints is defined by non-clamped phase converters by setpoint values of load outer conductor voltages which are to be generated with respect to the clamped output phase connection and formed by subtracting in each case two load phase voltage nominal values in this time segment, so that overall a sinusoidal profile is again established of all load line voltages. (This claim is the same as claim 5 but for the circuit of Fig. 4, ie claim 11. One could therefore combine claim 5 with 14, saying "converter according to one of claims 1 to 4 or claim 11, ...» ) 15. Converter according to one of claims 1 to 8, wherein the scheme is designed to operate during operation of the converter starting from a buck converter operation of the converter as a regular operation, clocking an input-side bridge branch (BA) with switched upper switch (T3) of an output-side bridge branch ( BB), to generate a three-phase load phase voltage system uM * when feeding the converter by a DC input voltage Uin, the control circuit performing an automatic change between buck and boost converter operation of the phase converters. 16. A converter according to one of claims 1 to 8, wherein the control is designed, in operation of the converter, starting from a buck converter operation of the converter as a regular operation, clocking an input side bridge branch (BA) with a switched upper switch (T3) of an output side bridge branch ( BB), the converter as a three-phase pulse rectifier system, which generates a regulated DC output voltage and the network draws sinusoidal currents to operate, wherein the control circuit performs an automatic change between buck and boost converter operation of the phase converter. 17. Converter according to one of claims 1 to 8, wherein the control is adapted to, during operation of the converter, starting from a boost converter operation of the converter, in the permanent on state of an upper transistor (T1) of an input-side bridge branch (BA) and clocking an output-side bridge branch ( BB) as a regular operation, wherein for the determination of relative turn-on of the input and output side bridge arms (BA, BA) inverts a setpoint uL * and then adds this physically from the output side to the input side directed voltage -uL * to the input voltage uin the phase converter and so on the set voltage value uB * to be set at the input B of the output side bridge branch (BB) is determined, and after limiting to uout upwards and zero downwards - physically only duty cycle dB lying between zero and one can be set - the duty cycle, ie the relative duty cycle of the upper transistor (T3) of the output side bridge branch (BB) is obtained, and then, to be able to set the required voltage uL *, if uB * exceeds the value uout, then the difference delta uB * of uB * and uout is determined and subtracted after limiting with uin up and zero down from the input voltage uin, following the consideration that to set a setpoint uL * which leads to uB * = uout or db = I, the output of the input side Bridge branch (BA) must be solved by the input voltage and must be lowered in terms of potential by appropriate timing, wherein the duty cycle dA then to be set is obtained by dividing uA * by uin. 18. Converter according to one of claims 1 to 8, wherein the control is designed to operate in the operation of the converter, starting from both modes of the converter as a regular operation, by mutual settlement of the output voltage uout in the setpoint voltage uA * and the input voltage uin in the setpoint voltage uB * and the corresponding limitation to the possible setting range, depending on the setpoint voltage uL * and the two voltages uin and uout the correct operating mode, ie either pure buck or pure boost operation to determine. 19. A converter according to any one of claims 1 to 8, wherein the control is adapted to each form a switching frequency triangular or trapezoidal current in the phase converter inductance (La, Lb, Lc) during operation of the converter, such that when switching off a power transistor always a correspondingly directed current for the charging of a parasitic capacitance of the switching off and the discharge of the parasitic capacitance of the subsequent turn on transistor of a bridge branch is available, so that turning on the subsequent transistor is de-energized, thus ensuring a lossless or ideal lossless (de-energized) switching is, in particular for current shaping respectively the input side and the output side bridge branch of a phase converter are clocked simultaneously. 20. A converter according to one of claims 1 to 8, wherein the control is designed to operate synchronously in the operation of the converter, the deep boost converter DC / DC converter, with the same switching frequency and a carrier signal of the modulation such that a current load of a feeding DC Voltage is minimized by superimposed by the individual bridge branches recorded current pulses such that overall there is a relatively low switching frequency fluctuation of the total input current taken from the DC voltage. 21. Converter according to one of claims 1 to 10, wherein the control is adapted to operate during operation of the converter with a supply voltage in the form of a rectified, but not smoothed Einphasenwechselspannung, hereinafter referred to as absolute value voltage, by the input side with respect to a local, Extending over a clock period, a mean value of the absolute magnitude is taken from a proportional, ie also amounts sinusoidal current, and on the other hand by the phase converter (10a, 10b, 10c) output voltages are formed such that for the three-phase load a symmetrical sinusoidal sen-senspannungsspannung system is present the output capacitors (Ca, Cb, Cc) are used for the compensation of a difference between the constant power delivered to a three-phase load and the double mains frequency fluctuation of the power drawn from the network in such a way that a simultaneous gle Ie increase or decrease of all output voltages by addition of an offset made and thus in the output capacitors (Ca, Cb; Cc) energy is increased or decreased, leaving the output output voltages unchanged. 22. A converter according to any one of claims 1 to 10, wherein the control is adapted to operate during operation of the converter with respect to a phase shift of load voltage and load current adjustable electrical load, wherein the phase shift is selected such that one for a transhipment of the output capacitors (Ca, Cb, Cc) compensated reactive power and thus does not have to be supplied via the phase converter inductances (La, Lb, Lc), thus reducing the current load on the power semiconductors of the phase converters (10a, 10b, 10c) and the phase converter inductors (La, Lb, Lc) is reached.