CN100433105C - display device - Google Patents

Abstract

A display device has elements efficiently arranged in pixels. The pixel circuit includes a capacitor for charging a voltage corresponding to the data signal transmitted from the data line. The first transistor of the pixel circuit outputs a current corresponding to the voltage charged in the capacitor. The plurality of emission elements emit light corresponding to the current output from the driving transistor. A plurality of emission control transistors are connected between the first transistor and the plurality of emission elements. The emission control transistor includes a plurality of semiconductor layers having substantially the same internal resistance as each other.

Description

display device

technical field

The present invention relates to display devices. More specifically, the present invention relates to organic electroluminescence displays using organic electroluminescence (hereinafter referred to as "EL") substances.

Background technique

In general, organic electroluminescent (EL) displays electrically excite organic fluorescent compounds, thereby emitting light. The organic emission elements (or organic emission units) are arranged in an n×m matrix to form an organic EL display panel, and the EL display panel is driven by voltage or current to display image data.

The organic emission element has the characteristics of a diode and is therefore also called an organic light emitting diode (OLED). An organic emissive element includes an anode (ITO), an organic thin film and a cathode layer (metal). The organic thin film has a multilayer structure including an emission layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) for maintaining a balance between electrons and holes and improving emission efficiency. In addition, the organic emission element includes an electron injection layer (EIL) and a hole injection layer (HIL). The organic emitting elements are arranged in an n×m matrix to form an organic EL display panel.

Methods of driving the organic EL display panel include a passive matrix method and an active matrix method using thin film transistors (TFTs). The passive matrix method includes forming anodes and cathodes that cross (or straddle) each other or are substantially perpendicular, select lines, and drive an organic EL display panel. The active matrix method includes sequentially turning on a plurality of TFTs respectively connected to data lines and scanning lines according to signals for selecting scanning lines and driving the organic EL display panel.

Hereinafter, a pixel circuit of a general active matrix organic EL display will be described.

FIG. 1 shows a pixel circuit, one of n×m pixels, which is located in the first row and first column.

As shown in FIG. 1 , a pixel 10 includes three sub-pixels 10r, 10g and 10b, and the three sub-pixels 10r, 10g and 10b include LEDs for emitting red light (R), green light (G) and blue light (B) respectively. The organic EL elements OLEDr, OLEDg and OLEDb. Further, in this structure, the sub-pixels are arranged in a stripe form, and the sub-pixels 10r, 10g, and 10b are connected to the respective data lines D1r, D1g, and D1b and the common scanning line S1.

The red sub-pixel 10r includes two transistors M11r and M12r and a capacitor C1r for driving the organic EL element OLEDr. Likewise, the green subpixel 10g includes two transistors M11g and M12g and a capacitor C1g for driving the organic EL element OLEDg, and the blue subpixel 10b includes two transistors M11b and M12b and a capacitor C1b for driving the organic EL element OLEDb. Since the connection and operation of the sub-pixels 10r, 10g, and 10b are substantially the same, only the connection and operation of the sub-pixel 10r will now be described as an example.

The driving transistor M11r is connected between the power supply voltage VDD and the anode of the organic EL element OLEDr, and supplies a current for emitting light to the organic EL element OLEDr. The cathode of the organic EL element OLEDr is connected to a voltage VSS which is lower than the power supply voltage VDD. The amount of current flowing in the driving transistor M11r is controlled by the data voltage applied through the switching transistor M12r. The capacitor C1r is connected between the source and the gate of the transistor M11r, and controls the applied voltage during a predetermined period. The scan line S1 for transmitting the on/off selection signal is connected to the gate of the transistor M12r, and the data line D1r for transmitting the data voltage corresponding to the red sub-pixel 10r is connected to the source of the transistor M12r.

Here, the switching transistor M12r is turned on in response to a selection signal applied to the gate. Then, the data voltage VDATA is applied from the data line D1r to the gate of the transistor M11r through the transistor M12r. Then, a current I _OLED flows to (and/or through) transistor M11r corresponding to the voltage V _GS charged between the gate and source of transistor M11r by capacitor Clr. The organic EL element OLEDr emits red light corresponding to the current I _OLED . The current flowing to the organic EL element OLEDr is calculated according to Equation 1 below.

[Equation 1]

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; OLED</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DATA</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; |</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

Here, _VTH is the threshold voltage of the transistor M11r, and β is a constant.

As shown in Equation 1, a current corresponding to the data voltage is supplied to the organic EL element OLEDr in the pixel circuit shown in FIG. 1, and the organic EL element OLEDr emits red light at a brightness corresponding to the supplied current. Here, the data voltages are supplied to have multi-level voltage values within a predetermined range, thereby displaying a specific gray scale.

Thus, in the organic EL display, one pixel 10 includes three sub-pixels 10r, 10g, and 10b, and each sub-pixel includes a driving transistor M11r, M11g, or M11b, a switching transistor M12r, M12g, or M12b, and a capacitor Clr, C1g, or C1b. , for driving the organic EL element OLEDr, OLEDg or OLEDb. Also, each sub-pixel is connected to a data line for transmitting a data signal and a power line for transmitting a power supply voltage V _DD .

Therefore, many lines for transmitting voltages and signals to transistors and capacitors need to be provided in each pixel, and it is difficult to arrange all the lines in one pixel.

Contents of the invention

In an example embodiment of the invention, there is provided a light emitting display whose elements are effectively arranged in pixels.

In order to illustrate the above and other features, according to one aspect of the present invention, a display device is provided, which includes a plurality of scan lines for transmitting selection signals, a plurality of data lines for transmitting data signals, and the scan lines and data A plurality of pixel circuits connected by lines. Here, at least one pixel circuit includes a capacitor, a driving transistor, a plurality of emission elements, and a plurality of emission control transistors. The capacitor charges a voltage corresponding to a data signal transmitted from a corresponding one of the data lines. The transistor outputs current corresponding to the voltage charged in the capacitor. A plurality of emission elements emit light corresponding to the current output by the drive transistor. A plurality of emission control transistors is connected between the drive transistor and the plurality of emission elements. Here, the emission control transistor includes a plurality of semiconductor layers having substantially the same internal resistance as each other.

In addition, the aspect ratio of each semiconductor layer may be substantially the same as that of another semiconductor layer, and two emitting elements among the plurality of emitting elements may emit red light, green light, respectively, in response to the current output by the driving transistor. One of light and blue light.

The length of each semiconductor layer formed corresponding to one emission control transistor may include a source region length, a channel region length and a drain region length of a corresponding one emission control transistor. The width of the semiconductor layers each forming a corresponding one of the emission control transistors may be measured in a direction substantially perpendicular to the direction in which the length of the semiconductor layers is measured.

Also, at least two semiconductor layers among the plurality of semiconductor layers may be disposed substantially parallel to each other.

According to another aspect of the present invention, a display device is provided, which includes a plurality of scan lines for transmitting selection signals, a plurality of data lines for transmitting data signals, and a plurality of pixels connected to the scan lines and the data lines circuit. Here, at least one pixel circuit disposed in the pixel region includes first, second and third emitting elements, first, second and third semiconductor layers, and first, second and third control electrode lines. The first, second and third emission elements include pixel electrodes to which a current is applied for emitting light corresponding to the applied current. The first, second and third semiconductor layers are connected to the pixel electrodes of the first, second and third emitting elements through the first, second and third contact holes, respectively. The first, second and third control electrode lines are insulated and cross the first, second and third semiconductor layers and are substantially parallel to each other. Aspect ratios of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are substantially the same as each other.

The first semiconductor layer may form a first emission control transistor having an insulated channel region intersecting the first control electrode line, and the second semiconductor layer may form a second emission control transistor having an insulated channel region intersecting the second control electrode line. For the transistor, the third semiconductor layer may form a third emission control transistor having an insulating channel region crossing the third control electrode line.

In addition, the length of each of the first, second and third semiconductor layers may include a source region length, a channel region length and a drain region length of a corresponding one of the first, second and third emission control transistors. The width of each of the first, second and third semiconductor layers may be measured in a direction substantially perpendicular to a direction in which the length of one of the corresponding first, second and third semiconductor layers is measured.

According to another aspect of the present invention, a display device is provided, including a plurality of scan lines for transmitting selection signals, a plurality of data lines for transmitting data signals, and a plurality of pixel circuits connected to the scan lines and the data lines. Here, at least one pixel circuit includes a first capacitor, a first transistor, first, second and third emission elements, and first, second and third emission control transistors. The first capacitor charges a voltage corresponding to a data signal transmitted from a corresponding one of the data lines. The first transistor outputs a current corresponding to the voltage charged in the first capacitor. The first, second and third emitting elements emit light corresponding to the current output from the first transistor, and the first, second and third emission control transistors are respectively connected between the first transistor and the first, second and third emitting elements between. Here, the first semiconductor layer forming the first emission control transistor is generally disposed symmetrically with the second semiconductor layer forming the second emission control transistor with respect to the third semiconductor layer forming the third emission control transistor.

At least two semiconductor layers among the first, second and third semiconductor layers may be substantially parallel to each other, and the first, second and third semiconductor layers forming the first, second and third emitting elements may be doped with the same types of impurities.

Here, at least one pixel circuit may further include a second transistor, a third transistor, and a second capacitor. The second transistor may be connected between the control electrode of the first transistor and a node between the first transistor and the first, second and third emission control transistors. The third transistor may have a first electrode connected to the first electrode of the first capacitor and a second electrode connected to the second electrode of the first capacitor. The second capacitor may have a first electrode connected to the second electrode of the third transistor and a second electrode connected to the control electrode of the first transistor.

According to another aspect of the present invention, a display device is provided, including a plurality of scanning lines for transmitting selection signals, a plurality of data lines for transmitting data signals, and connecting the scanning lines and data lines and arranged in a matrix form multiple pixel circuits. Here, at least one pixel circuit disposed in the pixel region includes first, second and third emitting elements, a semiconductor layer and first, second and third control electrode lines. The first, second and third emission elements include pixel electrodes to which a current is applied for emitting light corresponding to the applied current. The semiconductor layer includes a first semiconductor layer region connected to the pixel electrode of the first emission element through the first contact hole, a second semiconductor layer region connected to the pixel electrode of the second emission element through the second contact hole, and a second semiconductor layer region connected to the pixel electrode of the second emission element through the third contact hole. The hole is connected to the third semiconductor layer region of the pixel electrode of the third emissive element. The first, second and third control electrode lines are insulated, cross the semiconductor layer and are substantially parallel to each other. Here, the first semiconductor layer is generally arranged symmetrically with the third semiconductor layer with respect to the second semiconductor layer.

Here, at least one semiconductor layer region among the first, second and third semiconductor layer regions may be substantially parallel to at least one data line.

At least one semiconductor layer region among the first, second and third semiconductor layer regions may be substantially parallel to at least one scan line.

Description of drawings

The drawings and specification illustrate example embodiments of the invention and, together with the description, serve to explain principles of the invention.

Figure 1 shows a pixel circuit of a conventional light-emitting display panel;

2 is a schematic diagram of an organic EL display according to an exemplary embodiment of the present invention;

3 shows an equivalent circuit of a pixel circuit according to an example embodiment of the present invention;

4 is a layout diagram of a pixel circuit according to a first exemplary embodiment of the present invention;

Fig. 5 is a cross-sectional view along I-I' in Fig. 4;

Fig. 6 is a cross-sectional view along II-II' in Fig. 4;

FIG. 7 is a layout diagram of a pixel circuit according to a second exemplary embodiment of the present invention.

Detailed ways

In the detailed description that follows, there are shown and described certain exemplary embodiments of the invention, simply by way of illustration. As those skilled in the art would realize, the described example embodiments may be modified in different forms, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and descriptions are to be regarded as explanatory in themselves, and not restrictive.

Parts shown in the drawings or parts not shown in the drawings may not be discussed in the specification because they are not necessary for a complete understanding of the invention. The same reference numerals denote the same elements. Thicknesses are exaggerated to more clearly show several layers and several regions in the figures. When a layer, film, panel, etc. is said to be "on" another part, the other parts can be considered to be therebetween.

Additionally, several terms for scanlines are defined. The "current scanning line" refers to the scanning line transmitting the current selection signal, and the "previous scanning line" refers to the scanning line transmitting the selection signal before the current selection signal.

In addition, "current pixel" refers to a pixel that emits light according to the selection signal of the current scanning line, "previous pixel" refers to a pixel that emits light according to the selection signal of the previous scanning line, and "next pixel" refers to a pixel that emits light according to the selection signal of the next scanning line. Select the pixels that emit light from the signal.

As shown in FIG. 2 , an organic EL display according to an exemplary embodiment of the present invention includes a display panel 100 , a scan driver 200 , an emission controller 300 and a data driver 400 . The display panel 100 includes a plurality of scanning lines S0, S1...Sk...Sn and a plurality of emission control lines E1...Ek...En arranged in the row direction, and a plurality of data lines arranged in the column direction D1 . . . Dk . . . Dm and a plurality of power supply lines for applying a power supply voltage VDD, and a plurality of pixels 110 . Each pixel 110 is formed at the pixel region defined or surrounded by any two scan lines Sk-1 and Sk and any two adjacent data lines Dk-1 and Dk, and according to the current scan line Sk, the previous scan line Signals transmitted by Sk-1, the emission control line Ek and the data line Dk drive the pixel 110 . Moreover, each emission scan line E1 to En is composed of three emission control lines (for example, E1 includes E1r, E1g, and E1b, En includes Enr, Eng, and Enb, and Ek includes Ekr, Ekg, and Ekb, as shown in FIG. 3 ).

The scan driver 200 sequentially applies selection signals for selecting corresponding lines to the scan lines S0 to Sn so that data signals may be applied to pixels of the corresponding lines. The emission controller 300 sequentially applies emission control signals for controlling the emission of the organic EL elements OLEDr, OLEDg, and OLEDb shown in FIG. 3 to the emission control lines E1 to En. As long as the selection signal is sequentially applied, the data driver 400 applies the data signal corresponding to the pixels of the line to which the selection signal is applied to the data lines D1 to Dm.

The scan driver 200, the emission controller 300, and the data driver 400 may be connected to a substrate on which the display panel 100 is formed. Alternatively, the scan driver 200 , the emission controller 300 and/or the data driver 400 may be directly formed on the glass substrate of the display panel 100 . Also, a driving circuit composed of scan lines, data lines and transistors may be formed on the substrate of the display panel 100 . Also, the scan driver 200, the emission controller 300, and/or the data driver 400 may be adhered and connected to a substrate of the display panel 100, such as a tape carrier package (TCP), a flexible printed circuit (FPC), or a tape automatic bonding (tape automatic) bonding, TAB) and so on.

In an exemplary embodiment of the present invention, one field can be divided into three subfields to be driven. Red, green and blue data are applied, and red, green and blue light is emitted in three subfields. Here, the scan driver 200 sequentially applies selection signals to the scan lines S0 to Sn in each subfield. The emission controller 300 sequentially applies emission control signals to the emission control lines E1 to En so that each color organic EL element emits at each subfield. The data driver 400 applies data signals corresponding to red, green, and blue organic EL elements to the data lines D1 to Dm in three subfields.

Hereinafter, specific operations of the organic EL display according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 3 .

FIG. 3 shows an equivalent circuit of one pixel 110 in the organic EL display of FIG. 2 . In FIG. 3, for example, a pixel Pk connected to the _kth row of any scanning line Sk and the _kth column of the data line Dk is described, and all transistors are p-channel type transistors.

As shown in FIG. 3, a pixel circuit according to an exemplary embodiment of the present invention includes a driving transistor M1, a diode transistor M3, a capacitor transistor M4, a switching transistor M5, three organic EL elements OLEDr, OLEDg, and OLEDb, and a device for controlling three organic EL elements. Three emission controlling transistors M2r, M2g and M2b and two capacitors Cst and Cvth for the emission of the elements OLEDr, OLEDg and OLEDb. The launch control line Ek is composed of three launch control lines Ekr, Ekg and Ekb. The emission control transistors M2r, M2g, and M2b respond to emission control signals transmitted through the emission control lines Ekr, Ekg, and Ekb, respectively, and selectively transmit current transmitted from the driving transistor M1 to the organic EL elements OLEDr, OLEDg, and OLEDb.

Specifically, the transistor M5 whose gate is connected to the current scan line Sk and whose source is connected to the data line Dk responds to the selection signal transmitted from the scan line Sk, and transmits the data voltage applied from the data line Dk to the capacitor Cvth. The first electrode or node B. The transistor M4 responds to the selection signal transmitted from the previous scan line Sk-1, and connects the node B of the capacitor Cvth to the power supply VDD. The transistor M3 is connected between the second electrode or node A of the capacitor Cvth and the drain of the transistor M1. The transistor M3 is turned on in response to the selection signal transmitted by the previous scan line Sk-1, so that the transistor M1 is diode-connected. The gate of the drive transistor M1 for driving the organic EL element OLED (eg, OLEDr, OLEDg, and/or OLEDb) is connected to node A of the capacitor Cvth, and the source thereof is connected to the power supply VDD. The driving transistor M1 controls the current applied to the OLED of the organic EL element according to the voltage applied to the gate.

Also, the first electrode of the capacitor Cst is connected to the power supply VDD, the second electrode of the capacitor Cst is connected to the drain of the transistor M4 at or near the node B, and the first electrode of the capacitor Cvth is connected to the second electrode of the capacitor Cst, Two capacitors are connected in series, and the second electrode of the capacitor Cvth is connected to the gate of the driving transistor M1 at or near the node A.

The drain of the driving transistor M1 is connected to the sources of the emission control transistors M2r, M2g and M2b, and the gates of the transistors M2r, M2g and M2b are connected to the emission control lines Ekr, Ekg and Ekb, respectively. Drains of the emission control transistors M2r, M2g, and M2b are connected to anodes of the organic EL elements OLEDr, OLEDg, and OLEDb, respectively. A power source V _SS having a lower voltage level than the power source V _DD is applied to the cathodes of the organic EL elements OLEDr, OLEDg, and OLEDb. A negative voltage or a ground voltage can be used for the power supply V _SS .

When the low-level scan voltage is applied to the previous scan line Sk-1, the transistors M3 and M4 are turned on. When the transistor M3 is turned on, the transistor M1 becomes a diode-connected state. Therefore, the voltage difference between the gate and the source of the transistor M1 changes until the voltage difference becomes the threshold voltage Vth of the transistor M1. At this time, since the source of the transistor M1 is connected to the power supply _VDD , the sum of the power supply voltage _VDD and the threshold voltage Vth is applied to the gate of the transistor M1, ie, at or near the node A of the capacitor Cvth. Also, when the transistor M4 is turned on and the power supply voltage VDD is applied to the node B, the voltage V _Cvth charged by the capacitor Cvth can be calculated according to Equation 2 below.

[Equation 2]

_VCvth = _VCvthA - _VCvthB = (VDD+Vth) - VDD = Vth

Here, _VCvth refers to the voltage charged to the capacitor Cvth, _VCvthA refers to the voltage applied to the node A of the capacitor Cvth, and _VCvthB refers to the voltage applied to the node B of the capacitor Cvth.

When the low-level scan voltage is applied to the current scan line Sk, the transistor M5 is turned on, and the data voltage Vdata is applied to the node B. Also, since the capacitor Cvth is charged with a voltage corresponding to the threshold voltage Vth of the transistor M1, a voltage corresponding to the sum of the data voltage Vdata and the threshold voltage Vth is applied to the gate of the transistor M1. That is, the voltage Vgs between the gate and source of the transistor M1 can be calculated according to Equation 3 below. Here, a high-level signal is applied to the emission control line Ek (eg, Ekr, Ekg, and/or Ekb), and the transistor M2 (eg, M2r, M2g, and/or M2b ) is turned off to block current.

[Equation 3]

Vgs=(Vdata+Vth)-VDD

Then, the transistor M2 is turned on in response to a low-level signal from the emission control line Ek. Accordingly, a current I _OLED corresponding to the gate-source voltage Vgs of the transistor M1 is applied to the organic EL element through the transistor M2, and the organic EL element OLED (for example, OLEDr, OLEDg, and/or OLEDb) is emitted. The current I _OLED can be calculated according to Equation 4 below.

[Equation 4]

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; OLED</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Vgs</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vth</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Vdata</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; Vth</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; VDD</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vth</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; VDD</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vdata</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

Here, _IOLED denotes a current flowing into the organic EL element OLED, _VGS denotes a voltage between the source and gate of the transistor M1, Vth denotes a threshold voltage of the transistor M1, Vdata denotes a data voltage, and β denotes a constant.

When the data voltage Vdata is a red data signal and the emission control transistor M2r is turned on in response to the low-level emission control signal transmitted from the emission control line Ekr, the current _IOLED is transmitted to the red organic EL element OLEDr and red light emission occurs.

Also, when the data voltage Vdata is a green data signal and the emission control transistor M2g is turned on in response to the low-level emission control signal transmitted from the emission control line Ekg, the current _IOLED is transmitted to the green organic EL element OLEDg and green light emission occurs. Also, when the data voltage Vdata is a blue data signal and the emission control transistor M2b is turned on in response to the low-level emission control signal transmitted from the emission control line Ekb, the current _IOLED is transmitted to the blue organic EL element OLEDb and blue light emission occurs. The three emission control signals respectively applied to the three emission control lines have low-level periods that do not overlap with each other within one field, so one pixel can display red, green, and blue.

Then, in the organic EL display according to the first exemplary embodiment of the present invention, the arrangement structure in the pixel region where the pixel circuit is provided is described in detail with reference to FIGS. 4 , 5 and 6 . Here, elements of the current pixel Pk are assigned reference numerals, and elements of the previous pixel Pk-1 are assigned the same reference numerals except for adding an apostrophe ("'") to the reference numerals. A prime ("'") is used to distinguish elements of the current pixel from elements of the previous pixel.

FIG. 4 is a layout diagram of a pixel region in which the pixel circuit shown in FIG. 3 is provided according to a first exemplary embodiment of the present invention. Fig. 5 is a cross-sectional view along I-I' in Fig. 4 . Fig. 6 is a cross-sectional view along II-II' in Fig. 4 .

First, as shown in FIGS. 4 , 5 and 6 , a cut-off layer 3 is formed on an insulating substrate 1 . The cut-off layer 3 is composed of, for example, silicon oxide or the like. The polysilicon layers 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , and 29 are semiconductor layers formed on the cutting layer 3 .

。多晶硅层23形成包括在当前像素Pk中晶体管M2g的源区、漏区和沟道区的半导体层，在列方向上设置该多晶硅层23。多晶硅层24形成包括在当前像素Pk中晶体管M2b的源区、漏区和沟道区的半导体层，该多晶硅层24的形状类似于形状

。连接多晶硅层22、23和24以形成字母‘m’的形状。多晶硅层22位于多晶硅层23的左侧，多晶硅层24位于多晶硅层23的右侧。多晶硅层22通常与多晶硅层24关于多晶硅层23对称。The polysilicon layer 21 forms a semiconductor layer including a source region, a drain region and a channel region of the transistor M5 in the current pixel Pk, and the polysilicon layer 21 is shaped like a letter "U". The polysilicon layer 22 forms a semiconductor layer including a source region, a drain region and a channel region of the transistor M2r in the current pixel Pk, and the shape of the polysilicon layer 22 is similar to that of

. The polysilicon layer 23 forms a semiconductor layer including a source region, a drain region, and a channel region of the transistor M2g in the current pixel Pk, and is arranged in the column direction. The polysilicon layer 24 forms a semiconductor layer including a source region, a drain region and a channel region of the transistor M2b in the current pixel Pk, and the shape of the polysilicon layer 24 is similar to that of

. The polysilicon layers 22, 23 and 24 are connected to form the shape of the letter 'm'. The polysilicon layer 22 is located on the left side of the polysilicon layer 23 , and the polysilicon layer 24 is located on the right side of the polysilicon layer 23 . Polysilicon layer 22 is generally symmetrical with polysilicon layer 24 about polysilicon layer 23 .

The polysilicon layer 25 is located at or near the center of the pixel area and is arranged in the column direction, and the bottom end of the polysilicon layer 25 is connected to the polysilicon layers 22 , 23 and 24 . The polysilicon layer 26 is located on the left side of the polysilicon layer 25 , and the polysilicon layer 27 is located on the right side of the polysilicon layer 25 . Polysilicon layer 26 is generally symmetrical with polysilicon layer 27 about polysilicon layer 25 . Polysilicon layer 26 is generally square and forms the second electrode (node A) of capacitor Cvth, and generally rectangular polysilicon layer 27 forms the first electrode of capacitor Cst. The polysilicon layer 28 is letter 'n' shape, and one end of the polysilicon layer 28 is connected to the polysilicon layer 26, and the other end of the polysilicon layer 28 is connected to the polysilicon layer 25, and forms the source, drain and channel regions of the transistor M3. Polysilicon layer 29 is letter 'n' shape, and one end of polysilicon layer 29 is connected to polysilicon layer 28, and forms channel region and drain region of transistor M1 and source region, channel region and drain region of transistor M4.

Gate insulating film 30 is formed on polysilicon layers 21 to 19 .

Gate electrodes 41 , 42 , 43 , 44 , 45 , 46 , and 47 are formed on gate insulating film 30 . Specifically, the gate line 41 is arranged in the row direction and corresponds to the current scan line Sk of the current pixel Pk, and the gate line 41 is insulated and crosses the polysilicon layer 21 to form the gate of the transistor M5 in the current pixel Pk. . The gate line 42 is arranged in the row direction and corresponds to the emission control line Ekb in the current pixel Pk to form the gate of the transistor M2b. The gate line 43 is arranged in the row direction and corresponds to the emission control line Ekg of the current pixel Pk to form the gate of the transistor M2g. The gate line 44 is arranged in the row direction and corresponds to the emission control line Ekr of the current pixel Pk to form the gate of the transistor M2r. The gate line 45 is insulated and crosses the polysilicon layer 26 to form the gate of the transistor M1. A generally square gate 46 is disposed on polysilicon layer 26 to form a first electrode (node B) of capacitor Cvth. A generally rectangular gate 47 is disposed on polysilicon layer 27 to form a second electrode (node B) of capacitor Cst.

The gate line 41' is arranged in the row direction, which corresponds to the previous scan line Sk-1 of the previous pixel Pk-1, and is insulated and crosses the polysilicon layer 21' to form the gate of the transistor M5 of the previous pixel Pk-1. In addition, the gate line 41' is insulated and crosses the polysilicon layers 28 and 29 to form the gates of the transistors M3 and M4 of the current pixel Pk.

A layer insulating film 50 is formed on the gate electrodes 41 , 42 , 43 , 44 , 45 , 46 and 47 . The data line 61, the power line 62, and the electrodes 63, 64, 65, 66r, 66g, and 66b are formed on the layer insulating film 50 so that the data line 61, the power line 62, and the electrodes 63, 64, 65, 66r, 66g, and 66b pass through The contact holes 51a, 51b, 53, 54a, 54b, 55, 56a, 56b, 57r, 57g, and 57b are in contact with corresponding electrodes.

The data line 61 is disposed between two pixel regions in the column direction, and is connected to the polysilicon layer 21 through the contact hole 51a, so that the data line 61 is connected to the source of the transistor M5. The contact hole 51 a penetrates the layer insulating film 50 and the gate insulating film 30 .

The power supply line 62 is arranged in the column direction, and is connected to the polysilicon layers 27 and 29 through the contact hole 55, so that the power supply line 62 supplies power to the first electrode of the capacitor Cst and the source of the transistor M1. The contact hole 55 penetrates the layer insulating film 50 and the gate insulating film 30 .

The electrode 63 is close to the data line 61, is substantially parallel to the data line 61, and passes the drain region of the polysilicon layer 21 through the contact hole 51b of the layer insulating film 50 and the gate insulating film 30, and the contact hole 53 of the layer insulating film 50. , connected to gate 46. Electrode 63 becomes node B.

The electrode 64 is close to the gate 41', is substantially parallel to the gate 41', and connects the drain region to the polysilicon through the contact hole 54a penetrating the insulating film 50 and the gate insulating film 30 and the contact hole 54b penetrating the insulating film 50. Gate 45 of transistor M3 in layer 28 . Electrode 64 becomes node A.

The substantially rectangular electrode 65 is close to the gate 41', and the drain region is connected to the transistor in the polysilicon layer 29 through the contact hole 56a penetrating the layer insulating film 50 and the gate insulating film 30 and the contact hole 56b penetrating the layer insulating film 50. Gate 47 of M4. Electrode 65 becomes node B.

Electrodes 66r, 66g and 66b connect the pixel electrodes 81r, 81g and 81b of each emissive element to the drains of transistors M2r, M2g and M2b, respectively. Of the electrodes 66r, 66g, and 66b, each is substantially rectangular, and their row direction is longer than their column direction. Here, the data lines 62 are arranged in the column direction, and the gate electrodes 42 to 44 are arranged in the row direction. Electrodes 66r, 66g, and 66b are connected to polysilicon layers 22, 23, and 24 through contact holes 57r, 57g, and 57b penetrating gate insulating film 30 and layer insulating film 50, respectively, and to drains of transistors M2r, M2g, and M2b.

A flatting film 70 is formed on the electrodes 63, 64, 65, 66r, 66g, and 66b. The pixel electrodes 81r, 81g, and 81b are connected to the electrodes 66r, 66g, and 66b through the contact holes 71r, 71g, and 71b, respectively. In FIGS. 5 and 6, red, green, and blue organic films 85r, 85g including an emission layer (EML), an electron transport layer (ETL) and a hole transport layer (HTL) are formed on the pixel electrodes 81r, 81g, and 81b. and 85b's multilayer.

Thus, the polysilicon layers 22, 23 and 24 forming the emission control transistors are connected to each other. The polysilicon layer 23 forms the emission control transistor M2g of the organic EL element located in the middle of the three organic EL elements. The polysilicon layer 22 forms the emission control transistor M2r of the organic EL element located on the left side of the three organic EL elements. The polysilicon layer 24 forms the emission control transistor M2b of the organic EL element located on the right side of the three organic EL elements. Polysilicon layer 22 is generally disposed symmetrically with polysilicon layer 24 about polysilicon layer 23 . Therefore, elements including the driving transistor M1 and the n-channel emission control transistors M2r, M2g, and M2b can be efficiently disposed in the pixel region while the internal resistance of the polysilicon layer remains substantially unchanged.

Next, an arrangement structure of a pixel region according to a second exemplary embodiment of the present invention will be described in detail with reference to FIG. 7 .

The second exemplary embodiment of the present invention differs from the first exemplary embodiment in that each of the polysilicon layers 122, 123, and 124 for respectively forming the emission control transistors M2r, M2g, and M2b has a substantially constant aspect ratio, Therefore emission control transistors M2r, M2g and M2b have similar or substantially the same internal resistance. Hereinafter, elements of the second exemplary embodiment of FIG. 7 that differ from corresponding elements of the first exemplary embodiment of FIG. 4 will be described.

As shown in FIG. 7 , the polysilicon layer 122 has a length Lr and a width Wr, the polysilicon layer 123 has a length Lg and a width Wg, and the polysilicon layer 124 has a length Lb and a width Wb.

In general, the internal resistance of the polysilicon layer can be calculated according to Equation 5 below.

[Equation 5]

$\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; L</span>}}{\mathrm{<span\; class="notranslate">\; W</span>}}$

Here, R is the internal resistance of the polysilicon layer, L is the length of the polysilicon layer, that is to say the total length of the source region, channel region and drain region, and W is the width of the polysilicon in a direction substantially perpendicular to the direction in which the length is measured . In addition, R _S is a planar resistance, which is the resistance of a polysilicon layer having a unit width W and a unit length L. As an example, the plane resistance may have a value of 5Ω/plane.

In this case, the respective internal resistances of each of the polysilicon layers 122, 123 and 124 are determined by respective Lr/Wr, Lg/Wg and Lb/Wb. Accordingly, the polysilicon layers 122, 123, and 124 have a relationship as given in Equation 6 below, and thus the internal resistance R of each of the polysilicon layers 122, 123, and 124 has a similar or substantially the same value.

[Equation 6]

$\frac{\mathrm{<span\; class="notranslate">\; Lr</span>}}{\mathrm{<span\; class="notranslate">\; Wr</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; LG</span>}}{\mathrm{<span\; class="notranslate">\; w</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; Lb</span>}}{\mathrm{<span\; class="notranslate">\; wb</span>}}$

In this way, the characteristics of the emission control transistors M2r, M2g, and M2b can be kept substantially constant by using the polysilicon layers 122, 123, and 124 having substantially the same aspect ratio.

Thus, by using the polysilicon layers 122, 123, and 124 having substantially the same aspect ratio so that the characteristics of the emission control transistors M2r, M2g, and M2b can be set to be substantially the same, the currents transmitted through the emission control transistors M2r, M2g, and M2b I _OLED can be kept substantially constant.

According to an exemplary embodiment of the present invention, when one pixel region includes three organic EL elements, and each emission control transistor is connected between the source of the driving transistor and the corresponding organic EL element, the polysilicon layer forming the emission control transistor may be Connect as one. Also, when the polysilicon layer forming the emission control transistor of the organic EL element located in the middle of the three organic EL elements is located in the middle, the polysilicon layer located on the left side of the three organic EL elements is usually separated from the polysilicon layer located on the right side of the three organic EL elements. Symmetrical about the polysilicon layer located in the middle. In addition, the emission control transistors can have substantially the same characteristics by using polysilicon layers having substantially the same aspect ratio.

In this way, each element is more efficiently disposed on a small pixel area, while the internal resistance of the polysilicon layer forming the emission control transistor remains substantially unchanged. In addition, the emission control transistors have substantially the same current transfer characteristics, so the current output from the driving transistors can be substantially stably transferred to the corresponding emission elements.

Although the invention has been described in connection with specific exemplary embodiments, it will be understood by those skilled in the art that the invention is not limited to the disclosed embodiments, but that the invention is to cover various modifications and modifications included within the spirit and scope of the appended claims. Equivalent setting.

Claims (10)

1, a kind of display device comprises being used to transmit many sweep traces selecting signal, being used for many data lines of transmission of data signals and being connected to a plurality of image element circuits of this sweep trace and data line, wherein

At least one image element circuit comprises:

Capacitor is used to charge and the corresponding voltage of data-signal that comes from corresponding data lines transmission;

Driving transistors is used for exporting the electric current of the voltage that fills corresponding to capacitor;

A plurality of radiated elements are used for the galvanoluminescence corresponding to driving transistors output; With

Be connected a plurality of emission control transistors between this driving transistors and this a plurality of radiated elements,

Wherein these a plurality of emission control transistors comprise that each all has a plurality of semiconductor layers of substantially the same each other internal resistance.

2, the display device of claim 1, wherein the length breadth ratio of each semiconductor layer is substantially the same.

3, the display device of claim 2, the electric current of two the radiated element response driving transistorss output in wherein a plurality of radiated elements, a kind of light in red-emitting, green glow and the blue light respectively.

4, the display device of claim 3, wherein the length of a transistorized semiconductor layer of emission control of each formation correspondence comprises the corresponding transistorized source region of emission control length, channel region length and a drain region length.

5, the display device of claim 4, wherein with the vertical substantially direction of the direction of measuring semiconductor layer length on measure the width that each forms a corresponding transistorized semiconductor layer of emission control.

6, the display device of claim 2, at least two semiconductor layers in wherein a plurality of semiconductor layers are substantially parallel to each other.

7, a kind of display device comprises being used to transmit many sweep traces selecting signal, being used for many data lines of transmission of data signals and being connected to a plurality of image element circuits of this sweep trace and data line, wherein

At least one image element circuit that is arranged in the pixel region comprises:

First, second and the 3rd radiated element, they all comprise the pixel electrode that is applied in electric current, are used for corresponding to the galvanoluminescence that is applied; With

First, second and the 3rd semiconductor layer, they are connected to the pixel electrode of first, second and the 3rd radiated element respectively by first, second and the 3rd contact hole; With

First, second and the 3rd control electrode line, they are insulated and intersect with first, second and the 3rd semiconductor layer, and substantially parallel each other,

Wherein the length breadth ratio of first semiconductor layer, second semiconductor layer and the 3rd semiconductor layer is substantially the same each other.

8, the display device of claim 7, wherein this first semiconductor layer forms the first emission control transistor with the insulated trenches district that intersects with the first control electrode line;

This second semiconductor layer forms the second emission control transistor with the insulated trenches district that intersects with the second control electrode line; With

The 3rd semiconductor layer forms the 3rd emission control transistor with the insulated trenches district that intersects with the 3rd control electrode line.

9, the display device of claim 8, wherein each first, second and the length of the 3rd semiconductor layer comprise source region length, channel region length and the drain region length of one of corresponding first, second and the 3rd emission control transistor.

10, the display device of claim 9, the wherein width of measurement each first, second and the 3rd semiconductor layer on the direction vertical substantially with measuring corresponding first, second and the direction of one of the 3rd semiconductor layer length.

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