CN100584103C - Signal scheduling method and system in optical transport network - Google Patents

Abstract

The invention discloses a signal scheduling method in an optical transmission network, which includes: converting a received optical signal into an electrical signal through photoelectric conversion, and then performing demapping processing to adapt to a unified granular level. Based on the Asynchronous cross-connect scheduling processing is performed in the granular-level asynchronous cross-connect matrix. At the same time, a signal scheduling system in an optical transmission network is also disclosed, including: a photoelectric conversion unit, a demapping unit, an adaptation device, and an asynchronous cross matrix. After the optical signal is converted into an electrical signal by the photoelectric conversion unit, it is input to the demapping unit. , after demapping processing and output, enter the adaptation device for adaptation processing, output at a unified granular level, and enter the asynchronous cross-connect matrix for asynchronous cross-connect scheduling. The present invention realizes the cross-scheduling of signals of various high and low rate levels, reduces the complexity of system design, realizes the functions of add-drop multiplexing and cross-connection between signals of various rate levels, and improves the networking flexibility of the OTN network.

Description

Signal scheduling method and system in optical transport network

technical field

The present invention relates to signal scheduling technology in optical transport network (OTN), in particular to a method and system for realizing signal scheduling in OTN.

Background technique

Optical Transport Hierarchy (OTH) technology is a new generation transmission system after Synchronous Digital Hierarchy (SDH)/Synchronous Optical Network (Sonet). The advantage of the OTN network is to meet the explosive development requirements of data bandwidth. It is a transparent transmission technology developed to meet the large-capacity and coarse-grained scheduling requirements at the backbone network level, and adopts digital encapsulation technology.

In order to realize data transmission in OTH, the International Telecommunication Union Standardization Department (ITU-T) G.709 proposes to define the optical data unit (ODUk), where k=1, 2, 3, as three levels of connection signals, the rates are respectively for:

ODU1: 239/238×2.48832Gbps=2.498775126Gbps;

ODU2: 239/237×9.95328Gbps=10.037273924Gbps;

ODU3: 239/236×39.81312Gbps=40.319218983Gbps.

That is, the rate of ODUk (k=1, 2, 3) satisfies: 239/(239-k)×"STM-N".

And, optical transmission unit (OTUk), where k=1, 2, 3, as three levels of transmission signals, the rates are:

OTU1: 255/238×2.48832Gbps=2.66605714285714Gbps;

OTU2: 255/237×9.95328Gbps=10.7092253164557Gbps;

OTU3: 255/236×39.81312Gbps=43.018413559322Gbps.

That is, the rate of OTUk (k=1, 2, 3) satisfies: 255/(239-k)×"STM-N".

In addition, signals such as optical payload unit (OPUk) and tributary unit group (ODTUGk) are also defined, where k=1, 2, 3, to realize different functions.

Moreover, ITU-T G.709 also defines the mapping and time division multiplexing (TDM) method for the mutual conversion between the above-mentioned various signals, and the conversion path is shown in Figure 1.

As can be seen from Figure 1, the provided mapping and time division multiplexing paths mainly include:

1. STM16->OPU1->ODU1->OTU1

2. STM64->OPU2->ODU2->OTU2

3. STM256->OPU3->ODU3->OTU3

4. 4×STM16->4×OPU1->4×ODU1->ODTUG2->OPU2->ODU2->OTU2

5. 16×STM16->16×OPU1->16×ODU1->ODTUG3->OPU3->ODU3->OTU3

6. 4×STM64->4×OPU2->4×ODU2->ODTUG3->OPU3->ODU3->OTU3

In order to ensure the transparent transmission of customer data and its synchronization timing by the OTN network, when performing signal cross-scheduling, the OTN network performs scheduling based on ODUk (k=1, 2, 3) signals of different particles, and the cross-scheduling unit processes separately, so that Complete the connection scheduling function of ODUk (k=1, 2, 3) signals.

At present, the scheduling based on the ODUk (k=1, 2, 3) connection is realized by using a high-speed asynchronous crossover network chip. However, the port rate of the mature high-speed and large-capacity asynchronous electrical crossover network chip in the industry can generally reach 3.6Gbps, and it can only complete the scheduling function for ODU1 serial signals.

In this way, for the ODU2/ODU3 serial signal, that is, the ODU2/ODU3 signal obtained through the above-mentioned mapping multiplexing paths 2 and 3, since its internal customer data is in a large-grained form, such as STM64 and STM256, it should be directly implemented for ODU2/ODU3 Scheduling function, but the existing asynchronous cross-chip technology level cannot achieve such a high bit rate scheduling function, so it must be demultiplexed to obtain a low bit rate signal, which is called the equivalent ODU1 signal here, and then scheduling. Wherein, the equivalent ODU1 signal here has the same frame structure as the normal ODU1, but the rate is higher than that of the ODU1.

The currently proposed signal scheduling schemes in the OTN network mainly include the following two types:

The first technical solution is the U.S. Patent No. US 2002/0080442. As shown in Figure 2, the system for implementing signal scheduling includes: three independent asynchronous cross-connect matrices S3, S2, and S1, respectively based on 43G, 10.7G, and 2.7G particles, for crossing signals of corresponding rates; three asynchronous The cross matrixes are coupled through time division multiplexing and demultiplexing units MUX2 and MUX1.

The specific working method is: the OTU3 signal with a rate of 43G enters the input/output port IO3, after being converted into an ODU3 signal, enters the asynchronous cross matrix S3 based on 43G particles, and outputs after scheduling; enters MUX2 for demultiplexing into 4 channels of 10.7G ODU2 signals enter the asynchronous cross-connect matrix S2 based on 10.7G particles, and output after scheduling; enter MUX1, each 10.7G ODU2 signal is demultiplexed into four 2.7G ODU1 signals, and enters the asynchronous cross-connect based on 2.7G particles Matrix S 1, for scheduling.

For the input signal OTU2 with a rate of 10.7G, it directly enters IO2, and after being converted into an ODU2 signal, enters the asynchronous cross matrix S2 based on 10.7G particles, and outputs it after scheduling; enters MUX1, and the 10.7G ODU2 signal is demultiplexed into 4 The 2.7G ODU1 signal enters the asynchronous cross-connect matrix S1 based on 2.7G particles for scheduling.

The input signal OTU1 with a rate of 2.7G directly enters IO1, and after being converted into an ODU1 signal, it enters the asynchronous cross matrix S1 based on 2.7G particles for scheduling.

However, because the current asynchronous cross-connect chip technology is not yet mature, it is not possible to provide such large-capacity 43Gbps and 10.7Gbps granular-level asynchronous electrical cross-connect chips, so it is impossible to achieve equivalent ODU2 and ODU3 serial signal scheduling. In addition, due to the coupling relationship between matrices at all levels, the scheduling path is complicated; the entire system uses three levels of asynchronous cross-connect matrices based on 43G/10.7G/2.7G particles, which makes the cross-connect design very complicated.

The existing second technical solution comes from the US patent No. US 2003/001616416. Referring to Fig. 3, the system is mainly composed of a crystal oscillator unit, a mapping unit (Map), a demapping unit (Demap), a serial/parallel unit, a parallel/serial unit and a synchronous crossover network.

During the signal cross-scheduling process, the input OTU3/OTU2/OTU1 signals enter the Map units 21, 24, and 27 corresponding to the rate respectively, and after a certain number of bytes are stuffed and mapped, they reach a higher rate to complete the transparent mapping of the signal. At this time The rate of each signal is just an integer multiple of the SDH basic rate unit STM-1 (155.52Mbps), that is, OTU3->288×155.52Mbps=44.78976Gbps, OTU2->72×155.52Mbps=11.19744Gbps, OTU1->18× 155.52Mbps = 2.79936Gbps. The role of these stuffing byte mapping processes is to complete the smoothing of the frequency difference from OTUk signals to SDH containers, which is an asynchronous mapping process to ensure the synchronization of all OTUk signals.

Then, these serial high-speed signals output from Map units 21, 24, and 27 are respectively converted into 64/16/4 parallel signals through S/P units 22, 25, and 28, and the single-wire rate is 699.84Mbps, that is, S/P Units 22, 25, and 28 respectively complete the conversion of 44.78976Gbps->64×669.84Mbps, 11.19744Gbps->16×669.84Mbps, 2.79936Gbps->4×669.84Mbps, so that the dispatching system can perform synchronous dispatching on the reference frequency of 669.84MHz , so as to realize the scheduling function of the OTU3/2/1 signal.

After the parallel signal enters the synchronous cross network sheet 10 based on 699.84Mbps particles for cross scheduling, it enters the P/S units 32, 35, and 38 and converts them into serial high-speed signals respectively. 35 and 38 completed the conversion of 64×669.84Mbps->44.78976Gbps, 16×669.84Mbps->11.19744Gbps, 4×669.84Mbps->2.79936Gbps respectively.

Finally, the serial high-speed signals enter the Demap units 31, 34, and 37 to perform a de-stuffing and de-mapping process opposite to the Map process, and recover the internal OTU3/2/1 service data output from the high-speed serial signals.

Wherein, crystal oscillator unit 15 outputs clock signal fo of 44.78976GHz, and this clock signal fo further enters 1/4 frequency division unit 16, 1/16 frequency division unit 17 and 1/N frequency division unit 18; clock signal fo passes through 1 The /4 frequency division unit 161/16 divides frequency by the frequency division unit 17 to obtain 11.19744GHz and 2.79936GHz clock signals fo/4 and fo/16. These output clock signals can be sent to corresponding Map/Demap units for asynchronous mapping/demapping between OTU3/2/1 services and 44.78976Gbps, 11.19744Gbps, 2.79936Gbps serial high-speed signals. The frequency division ratio N of 1/N frequency division unit 18 is 16 times of serial/parallel (S/P) unit 28 parallel bit widths, namely 4 * 16=64, is used to produce each S/P unit, backplane scheduling system , The reference frequency of the P/S unit is 699.84MHz.

The disadvantage of prior art 2 is that this technology is based on the scheduling of OTU1/OTU2/OTU3 signal transmission units, and does not realize the connection level function of ODU1/ODU2/ODU3, so the connection monitoring and management of OTN networks cannot be realized, and it is not a complete The OTN equipment unit only completes the scheduling function of OTU1/OTU2/OTU3. The asynchronous mapping of OTU1/OTU2/OTU3 has different filling methods, so the transmission units cannot communicate with each other, and can only form an independent OTN network of OTU1 or OTU2 or OTU3, which limits the OTN network networking.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a method for realizing signal scheduling in an optical transport network, realize cross-scheduling of high and low rate level signals, reduce the complexity of system design, and realize splitting between signals of various rate levels. Insert multiplexing and cross-connection functions to improve the networking flexibility of the OTN network.

Based on the above purpose, the present invention provides a signal scheduling method in an optical transport network, including:

The received optical signal is converted into an electrical signal by photoelectric conversion, and then demapped, the signal rate is adapted to a uniform granular level, and asynchronous cross-connect scheduling processing is performed in the asynchronous cross-connect matrix based on the granular level;

The process of the signal rate adaptation includes:

For the case where the rate of the current signal is greater than the granular level,

If the received signal is formed by mapping and multiplexing the low-speed signal whose rate is the granular level, the current signal is time-decomposed and multiplexed into multiple low-speed signals;

If the received signal is mapped from a high-speed signal with a rate greater than the granular level, split the current signal into multiple parallel signals with a rate equal to the granular level;

If the received signal is formed by mapping and multiplexing of more than one high-speed signal whose rate is greater than the granular level, the current signal is time-decomposed and multiplexed into multiple high-speed signals described above, and each obtained high-speed signal is split into multiplexed parallel signals at the granular level.

The process of signal rate adaptation described in the method includes:

After the demapping process, if the rate of the current signal is equal to the granular level, the current signal is directly sent to the asynchronous cross-connect matrix for asynchronous cross-connect scheduling;

If the rate of the current signal is lower than the granular level, multiple signals of the same type as the current signal are combined into one signal whose rate is the granular level.

The received optical signal described in the method is an optical signal under the ITU-T G.709 protocol.

The unified granular level described in the method is the ODU1 rate level;

If the received optical signal is an OTU1 mapped from one ODU1, the process of signal rate adaptation is to perform ODU framing and scrambling on the ODU1 formed after demapping, and then send it to the asynchronous crossover The matrix performs asynchronous cross-scheduling;

If the received optical signal is an OTU2 formed by mapping and multiplexing 4-way ODU1, the process of signal rate adaptation is to decompose and multiplex the ODU2 formed after demapping into 4-way ODU1, and then perform ODU framing , scrambling code processing;

If the received optical signal is an OTU3 formed by mapping and multiplexing 16-way ODU1, the process of signal rate adaptation is to decompose and multiplex the ODU3 formed after demapping into 16-way ODU1, and perform ODU framing, After scrambling;

If the received optical signal is an OTU2 mapped from one ODU2, the signal rate adaptation process is to perform ODU framing and scrambling on the ODU2 formed after demapping, and then use channelization framing Split into 4 parallel signals whose rate is ODU1 rate level;

If the received optical signal is an OTU3 mapped from one ODU3, the signal rate adaptation process is to perform ODU framing and scrambling on the ODU3 formed after demapping, and then use channelization framing Split into 16 parallel signals whose rate is ODU1 rate level;

If the received optical signal is an OTU3 formed by mapping and multiplexing 4-way ODU2, the process of signal rate adaptation is to decompose and multiplex the ODU3 formed after demapping into 4-way ODU2, and then perform ODU framing 1. Scrambling code processing, splitting each obtained ODU2 channel into 4 channels of parallel signals with a rate equal to the ODU1 rate level by using channelization and framing method.

The demapping process described in the method includes: OTU framing, descrambling, FEC decoding, OTU overhead termination, and ODU demapping.

The splitting process described in this method is: after the signal is frame-fixed, it is buffered in the order of the frames, and whenever n frames are full, the data of the n frames are sent in parallel, and the above splitting process is repeated ; where n is the number of channels to split the current signal into.

The process of demapping described in the method further includes after ODU demapping is performed: ODU mapping, OTU framing, FEC coding, adding FEC area, and scrambling; the unified granular level is OTU1 rate level;

If the received optical signal is an OTU1 mapped by one ODU1, the signal rate adaptation process is to perform ODU1 mapping, OTU1 framing, FEC encoding, and scrambling on the ODU1 signal formed after the demapping process After processing, OTU1 is formed and sent to the asynchronous cross-connect matrix for asynchronous cross-connect scheduling;

If the received optical signal is OTU2 formed by mapping and multiplexing 4-way ODU1, then the process of signal rate adaptation is to decompose and multiplex the ODU2 formed after the demapping process into 4-way ODU1 signal, and perform ODU1 After mapping, OTU1 framing, FEC encoding, and scrambling processing, 4 channels of OTU1 are formed and enter asynchronous cross-scheduling;

If the received optical signal is an OTU3 formed by mapping and multiplexing 16 ODU1 channels, the signal rate adaptation process is to decompose and multiplex the ODU3 formed after the demapping process into 16 ODU1 signals, and perform ODU1 After mapping, OTU1 framing, FEC encoding, and scrambling processing, 16 channels of OTU1 are formed and enter asynchronous cross-scheduling;

If the received optical signal is an OTU2 mapped from one ODU2, the signal rate adaptation process is to perform ODU2 mapping, OTU2 framing, FEC encoding, and scrambling processing on the ODU2 formed after the demapping process After that, OTU2 is formed, which is split into 4 parallel signals whose rate is OTU1 rate level by channelized framing method, and enters asynchronous cross-scheduling;

If the received optical signal is an OTU3 mapped by one ODU3, the signal rate adaptation process is to perform ODU3 mapping, OTU3 framing, FEC encoding, and scrambling processing on the ODU3 formed after the demapping process After that, OTU3 is formed, which is split into 16 parallel signals whose rate is OTU1 rate level by channelized framing method, and enters asynchronous cross-scheduling;

If the received optical signal is an OTU3 formed by mapping and multiplexing 4-way ODU2, the process of signal rate adaptation is to decompose and multiplex the ODU3 formed after the de-mapping process into 4-way ODU2 signals, and perform ODU2 After mapping, OTU2 framing, FEC encoding, and scrambling processing, 4 channels of OTU2 are formed, and each channelized OTU2 is split into 4 channels of parallel signals with a rate of OTU1 rate level, and enters asynchronous cross-scheduling .

The splitting process described in this method is: buffer the signal in the order of frames, and send out the data of the n frames in parallel every time n frames are stored, and repeat the above splitting process; where n is the number of current signals The number of paths to split into.

The method is characterized in that, after the asynchronous cross-connect scheduling processing, it further includes: performing a reverse process of the signal rate adaptation process, performing demapping processing and electro-optical conversion into an optical signal and then outputting it.

Another main purpose of the present invention is a system for implementing signal scheduling in an optical transport network, which can support cross-scheduling of signals of various rate levels, reduce the complexity of system design, and support add-drop multiplexing between signals of various rate levels. Use and cross-connection functions to improve the networking flexibility of the OTN network.

Based on this purpose, the present invention provides a signal scheduling system in an optical transmission network, including:

at least one photoelectric conversion unit for converting received optical signals into electrical signals;

at least one demapping unit, configured to demap signals;

at least one adapting device for adapting the input signal to a uniform granular level signal; and

Asynchronous cross matrix, used for asynchronous cross scheduling of signals at a uniform granularity level;

After the received optical signal is converted into an electrical signal by the photoelectric conversion unit, it is input to the demapping unit, and after being processed and output by demapping, it enters the adaptation device, and is adapted into a signal whose rate conforms to the unified granular level, and then input to the asynchronous crossover The matrix performs asynchronous cross-scheduling;

If the input signal is formed by mapping and multiplexing the low-speed signal whose multi-channel rate is the granular level, the adaptation device includes: a signal generation unit and a time division multiplexing unit, and the time division multiplexing unit is used for Time-decomposing and multiplexing the high-speed signal formed by mapping and multiplexing multiple low-speed signals into multiple low-speed signals whose rate is the same granular level, and outputting to the signal generation unit;

If the received signal is mapped from a high-speed signal with a rate greater than the granular level, the adaptation device includes: a signal generating unit and a splitting unit, and the splitting unit is used to process the signal generating unit The output signal is split into multiple parallel signals whose rate is the unified granularity level;

If the received signal is formed by mapping and multiplexing of more than one high-speed signal whose rate is greater than the granular level, the adaptation device includes: a signal generation unit, a time division multiplexing unit and a splitting unit, and a time division multiplexing unit The unit demultiplexes the high-speed signal formed by mapping and multiplexing multiple low-speed signals into multiple low-speed signals and inputs them to the signal generating unit and the splitting unit, and the splitting unit further processes the low-speed signal outputted by the signal generating unit Split into parallel signals at the uniform granularity level.

If the rate of the input signal is at the uniform granularity level, the adapting device is a signal generating unit for signal framing and scrambling.

The splitting unit of the system includes: a framing module, a write address generation module, a read address generation module, an n frequency division module, and 2n first-in-first-out memory FIFOs, where n is the signal split by the splitting unit The number of output signal channels;

The input signal has a synchronous clock along with the channel, and the frame signal is obtained after the frame search process of the framing module. The synchronous clock and the frame signal are input to the write address generation module together, and the generated write address and write permission enter each first-in-first-out memory FIFO respectively, and control The first-in-first-out memory FIFO is written, and the signal clock is also input to the n frequency division module. The output after frequency division by the n frequency division module is input to the read address generation module together with the frame signal, and the read address and read permission are respectively entered into each A first-in-first-out memory FIFO, which controls the readout of the first-in-first-out memory FIFO;

The data of the input signal is sequentially written into n first-in-first-out memory FIFOs in the order of frames, and the data in the n first-in-first-out memory FIFOs are output in parallel after being filled, and the subsequent data are sequentially written into another n first-in first-out memory After the FIFO is full, the data in the other n first-in-first-out memory FIFOs are output in parallel.

The system further includes: at least one electro-optical conversion unit for converting the received electrical signal into an optical signal;

At least one mapping unit, configured to perform mapping processing on signals;

at least one inverse adaptation device, configured to inversely adapt the uniform granular level signal output by the asynchronous crossbar matrix to a signal of a required rate;

The signal output by the asynchronous cross-connect matrix after asynchronous cross-connect scheduling enters the inverse adaptation device for reverse adaptation processing, and is input to the mapping unit. After mapping processing, it enters the electro-optical conversion unit to be converted into an optical signal.

If the rate of the required output signal of the system is the uniform granularity level, the inverse adaptation device includes: a frame alignment unit and a signal recovery unit, and the frame alignment unit outputs the uniform granularity level signal output by the asynchronous cross matrix After performing frame alignment processing, input to the signal recovery unit for descrambling processing and then output;

If the required output is a signal formed by mapping and multiplexing the low-speed signal at the granular level, the inverse adaptation device includes: a frame alignment unit, a signal recovery unit and a time division multiplexing unit, and the time division multiplexing The use unit is used to time-multiplex the multiple low-speed signals output by the frame alignment unit and the signal recovery unit into one high-speed signal of the required rate level and then output it;

If the required output is a signal mapped by a high-speed signal with a rate greater than the granular level, the inverse adaptation device includes: a frame alignment unit, a signal recovery unit and a merging unit, and the frame alignment unit will Each set of parallel signals at the same granularity level output by the asynchronous cross matrix is processed by frame alignment and then input to the merging unit, which merges multiple parallel signals into one high-speed signal of the required rate level and then inputs it to the signal recovery unit for solution. output after scrambling;

If the desired output is a signal formed by mapping and multiplexing more than one high-speed signal whose rate is greater than the granular level, the inverse adaptation device includes: a frame alignment unit, a signal recovery unit, a time division multiplexing unit and a merging unit , the frame-alignment unit performs frame-alignment processing on each group of parallel signals at a uniform granularity level output by the asynchronous cross matrix and then inputs them to the merging unit, and the merging unit merges multiple parallel signals into one signal and then inputs it to the signal recovery The unit descrambles and outputs to the time division multiplexing unit after time division multiplexing into one high-speed signal of the required rate level and then outputs.

The merging unit of the system is internally provided with 2n first-in-first-out memory FIFOs, and each first-in-first-out memory FIFO stores a frame of data, and data and reference frame signals are sequentially written into n first-in-first-out memory FIFOs for alignment processing, and At the same time, the data is sequentially read and output from other n first-in-first-out memory FIFOs at a rate n times higher than that of the write operation; wherein, n is the number of signal paths output after the signal is split by the splitting unit;

The frame alignment unit includes:

The backplane interface module is used to restore the clock and data of the input n-channel signals, input the recovered n-channel clock and data signals to the frame alignment module, and select one of the clocks as a reference clock and send them to the frame alignment module and the frame alignment module respectively. said merging unit;

The fixed frame alignment module is used to perform frame search on each channel of signals, find the respective frame starting positions of n channels of signals, align the frame starting positions of n channels of signals to the same frame phase, and output the n channels of aligned data and reference frame signals to the merging unit.

The asynchronous cross-connect matrix in the system is an asynchronous cross-connect mesh.

It can be seen from the above that the method and system for signal scheduling in an optical transport network provided by the present invention have the following characteristics and advantages:

1) The signal rate adaptation method is adopted, so that signals of any rate level can be converted to a uniform rate level and scheduled in a unified asynchronous cross-connect matrix without the need for multi-level cross-connect units, thereby reducing the cost of system design Complexity, and unified scheduling can realize flexible add-drop multiplexing between signals of various rate levels, which improves the networking flexibility of the OTN network.

2) The present invention expands the time-division multiplexing/demultiplexing technology of signals in the prior art, splits high-speed signals into multiple low-speed parallel signals for bundling and scheduling, and transmits high-speed signal particles on the parallel signals channelized into frames, and in scheduling The same scheduling path is used in the system to realize the scheduling function of high-speed signal particles. On the level of the existing asynchronous cross-chip technology, the scheduling problem of ODU2/ODU3 higher rate signals is solved.

Description of drawings

Figure 1 is a schematic diagram of the mapping and multiplexing paths between various signals defined by ITU-T G.709;

Fig. 2 is the structural diagram of the signal dispatching system of the existing first technical solution;

Fig. 3 is the structural diagram of the signal dispatching system of the second existing technical solution;

Fig. 4 is the structural block diagram of the signal dispatching system of the present invention;

FIG. 5 is a schematic structural diagram of an adaptation device in the signal dispatching system of the present invention;

6 is a schematic structural diagram of an inverse adaptation device in the signal dispatching system of the present invention;

FIG. 7 is a schematic structural diagram of a system that can simultaneously perform unified scheduling based on ODU1/ODU2/ODU3 according to the present invention;

Figure 8 is a schematic diagram of the mapping structure from ODUk to OTUk specified in ITU-T G.709;

9 is a schematic structural diagram of the ODU2 splitting unit in the signal dispatching system of the present invention;

10 is a schematic structural diagram of an ODU2FIFO merging unit for ODU2 signals in the signal dispatching system of the present invention;

Fig. 11 is a schematic structural diagram of the backplane interface module in the ODU2FIFO merging unit of the present invention for ODU2 signals;

FIG. 12 is a schematic structural diagram of the frame alignment module in the ODU2FIFO merging unit for ODU2 signals in the present invention;

FIG. 13 is a timing diagram of the frame alignment process of the frame alignment module of the present invention;

FIG. 14 is a schematic structural diagram of the ODU2FIFO merging unit in the ODU2FIFO merging unit for ODU2 signals in the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

The core idea of the present invention is: on the basis of the existing high-speed asynchronous crossover technology, in order to unify the scheduling unit of the ODU1/ODU2/ODU3 signal, the received optical signal is converted into an electrical signal through photoelectricity, and after demapping processing, Adapt to a unified granular level, and perform asynchronous cross-connect scheduling processing in the same asynchronous cross-connect matrix based on the granular level.

During the adaptation process, if the rate of the signal is greater than the unified granular level, the current signal is decomposed into multiple signals so that the rate of each signal meets the unified granular level; if the signal rate is equal to the unified granular level At the granular level, the signal can be directly sent to the asynchronous cross-connect matrix for asynchronous cross-connect scheduling after demapping; if the signal rate is lower than the unified granular level, multiple signals can be combined into one signal by means of time division multiplexing, etc. , so that the rate of the signal satisfies the grain level.

Among them, when the signal rate is greater than the unified granular level, there are three situations. Take the asynchronous cross matrix based on the 2.5Gbps granular level under the ITU-T G.709 protocol as an example:

In the first case, the signal is formed by mapping and multiplexing the low-speed signal at the granular level. For example, the current OTU2 or OTU3 is formed by mapping and multiplexing 4 or 16 ODU1 channels, then It is only necessary to perform time-decomposition and multiplexing of the current signal, and restore it to a low-speed signal with a multi-channel rate at the granular level, that is, the time-decomposition and multiplexing of the ODU2 signal after demapping OTU2 into 4 channels of ODU1, and the demapping OTU3 signal The ODU3 signal is decomposed and multiplexed into 16 channels of ODU1.

In the second case, the signal is mapped from a high-speed signal with a rate greater than the granular level, for example: the current OTU2 is mapped from ODU2, or OTU3 is mapped from ODU3, then the The current signal is split into multiple parallel signals whose rate is at the granular level. For example, after OTU2 is demapped into ODU2, it is split into 4 signals with a rate of 2.5Gbps, that is, ODU1, using the method of channelization and framing. The rate level is sent to the asynchronous cross matrix in parallel, and the same scheduling path is used during scheduling, so that the parallel signals are bundled and scheduled. Since these 4 signals can be combined to form a complete ODU2, so for the convenience of description, the present invention will disassemble The divided ODU2 is represented as ODU2[3:0], and each ODU2[3:0] contains 4 ODU1 rate level signals; after demapping OTU3 into ODU3, it is split by channelization and framing 16 channels of ODU1 rate-level signals are sent in parallel to the asynchronous cross matrix binding scheduling. For the convenience of description, the present invention expresses the split ODU3 as ODU3[15:0]. Each ODU3[15:0] Contains signals of 16 ODU1 rate levels.

In the third case, the signal is multiplexed by multiplexed high-speed signals with a multi-channel rate greater than the granular level. For example, the current OTU3 is multiplexed by four-channel ODU2. Decompose and multiplex into multiple high-speed signals with a rate greater than the granular level, and then split each obtained high-speed signal into multiple parallel signals with a rate equal to the granular level, that is, after OTU3 is demapped into ODU3, the Multiplexing into 4 channels of ODU2, and then splitting each channel of ODU2 into 4 channels of ODU1 rate level signals, that is, ODU2[3:0], so as to obtain a total of 16 channels of ODU1 rate level signals, that is, 4×ODU2[3 :0], sent to the asynchronous crossbar matrix in parallel.

In order to realize the above method, the present invention provides a signal scheduling system. The structural block diagram of the system is shown in FIG. The conversion unit, the demapping unit and the adaptation device are used for performing rate adaptation on signals before scheduling. The dispatching process is as follows: after the optical signal required for dispatching processing is received by the signal dispatching system, it is converted into an electrical signal by the photoelectric conversion unit, and then input to the demapping unit. After being output by demapping processing, it enters the adaptation device for adaptation processing Finally, output at a unified granular level and enter the asynchronous cross-connect matrix for asynchronous cross-connect scheduling.

The output signal after scheduling can be further reverse-adapted according to the need, and converted into a signal of the required rate for transmission, so that a reverse adaptation device, a mapping unit and an electro-optical conversion unit can also be added to the output of the asynchronous cross matrix. In this way, the output signal scheduled by the asynchronous cross matrix enters the inverse adaptation module to perform the inverse process of adaptation, and converts it into a signal of the required rate. After being remapped by the mapping unit, it enters the electro-optical conversion unit to restore to an optical signal and then outputs .

Based on the various connection signals ODU1/ODU2/ODU3 specified in the current ITU-T G.709 protocol, the structure of the adaptation device of the present invention is shown in Figure 5.

For the ODU1 signal, since the asynchronous cross-connect matrix in this embodiment uniformly adopts the ODU1 rate level, it is sufficient to perform simple operations such as framing and adaptation on the ODU1 signal according to different output signals required. Specifically, if the ODU1 signal needs to be output, the ODU1 adaptation device is the ODU1 signal generation unit 501 for extending the ODU frame header and signal scrambling code; if it is necessary to add control information bits and FEC error correction functions to the signal, the output For the OTU1 signal with FEC encoding, the ODU1 adaptation device is the OTU1 signal generation unit 502 for ODU1 mapping, OTU1 framing, FEC encoding and scrambling.

For the ODU2 signal multiplexed by 4×ODU1, if it is necessary to output the 4×OTU1 signal with FEC encoding, the adapter device of ODU2 includes in sequence according to the signal flow: used to complete the ODU2 signal to 4 low-level ODU1 Time-division-multiplexing unit 511 for signal time-division-multiplexing conversion, and OTU1 signal generation unit 502 for completing ODU1 mapping, OTU1 framing, FEC coding and scrambling for processing the multiple signals; if outputting 4×ODU1 signals is required, then The adapter device of ODU2 includes in sequence according to the signal flow: a time-division-multiplexing unit 511 for completing the time-division-multiplexing conversion of the ODU2 signal to 4 low-level ODU1 signals, and a time-division multiplexing unit 511 for processing the multiple signals to extend the ODU frame header ODU1 signal generating unit 501 for sum signal scrambling. Wherein, since the signals output after the time-demultiplexing and multiplexing unit 511 need to be processed are 4 paths, there should be 4 ODU1 signal generating units 501 and OTU1 signal generating units 502 described here (in FIG. one).

For ODU2 signals that are not multiplexed by low-level signals, if it is necessary to output OTU signals with FEC encoding, the ODU2 adaptation device includes: ODU2 mapping, OTU2 framing, FEC encoding and scrambling according to the signal flow direction The OTU2 signal generation unit 504, and the OTU2 splitting unit 506 for converting the serial OTU2 signal to the OTU2[3:0] parallel signal; if the ODU2 signal needs to be output, the ODU2 adaptation device includes in sequence according to the signal flow direction: The ODU2 signal generating unit 503 for extending the ODU frame header and signal scrambling, and the ODU2 splitting unit 505 for converting the serial ODU2 signal to the ODU2[3:0] parallel signal.

For the ODU3 signal multiplexed by 16×ODU1, if it is necessary to output the 16×OTU1 signal with FEC encoding, the adapter device of ODU3 includes in order of signal flow: used to complete the ODU3 signal to 16 low-level ODU1 The time-division-multiplexing unit 512 for signal time-division multiplexing conversion, and the corresponding 16 OTU1 signal generation units 502; if it is necessary to output 16×ODU1 signals, the ODU3 adaptation device includes in sequence according to the signal flow: for completing the ODU3 signal A time-demultiplexing unit 512 for time-demultiplexing and multiplexing conversion to multiple low-level ODU1 signals, and a corresponding generation unit 501 for 16 ODU1 signals.

For the ODU3 signal multiplexed by 4×ODU2, if it is necessary to output the OTU signal with FEC encoding, the ODU3 adapter device includes in sequence according to the signal flow: for completing the ODU3 signal to 4 low-level ODU2 signals Demultiplexing time demultiplexing unit 513, corresponding four OTU2 signal generating units 504, and corresponding multiple OTU2 splitting units 506 for converting serial OTU2 signals to OTU2[3:0] parallel signals ; If the ODU signal needs to be output, the ODU3 adapter device includes in sequence according to the signal flow: a time-demultiplexing and multiplexing unit 513 for completing the time-demultiplexing and multiplexing conversion of the ODU3 signal to 4 low-level ODU2 signals, and the corresponding 4 ODU2 A signal generating unit 503, and four corresponding ODU2 splitting units 505 for converting a serial ODU2 signal to an ODU2[3:0] parallel signal.

For ODU3 signals that are not multiplexed by low-level signals, if it is necessary to output OTU signals with FEC encoding, the ODU3 adaptation device includes in sequence according to the signal flow: for completing ODU3 mapping, OTU3 framing, FEC encoding and scrambling The OTU3 signal generating unit 508 of the code, and the OTU3 splitting unit 510 used to complete the conversion of the serial OTU3 signal to the OTU3[15:0] parallel signal; if the ODU signal needs to be output, the ODU3 adaptation device includes in sequence according to the signal flow direction : an ODU3 signal generating unit 507 for extending the ODU frame header and signal scrambling, and an ODU3 splitting unit 509 for converting a serial ODU3 signal to an ODU3[15:0] parallel signal.

Wherein, the above-mentioned ODUk/OTUk (k=1, 2, 3) signal generation unit is sometimes collectively referred to as a signal generation unit in the present invention, and the ODUk/OTUk (k=1, 2, 3) splitting unit is also unified called a split unit.

Based on the various connection signals ODU1/ODU2/ODU3 specified in the current ITU-T G.709 protocol, the structure of the reverse adaptation device of the present invention is shown in Figure 6.

For the signal that needs to be de-adapted to ODU1, since the asynchronous cross-connect matrix in this embodiment uniformly adopts the rate level of ODU1, during the de-adaptation process, only simple processing such as frame alignment and descrambling is required. Specifically, if the input is an OTU1 signal, the inverse adaptation device of ODU1 is the OTU1 frame alignment unit 616 for OTU1 signal frame alignment, and completes descrambling, FEC decoding, and ODU1 demapping to form the OTU1 signal output by ODU1 Restoration unit 602; if the input is ODU1 signal, the inverse adaptation device of ODU1 is ODU1 frame alignment unit 615 for frame alignment of ODU1 signal, and ODU1 signal restoration unit 601 for descrambling.

For the signal that needs to be inversely adapted to ODU2, if the input is a 4×OTU1 signal, the inverse adaptation device of ODU2 includes in sequence according to the signal flow: OTU1 frame alignment unit 616 and 4 descrambling, FEC decoding and ODU1 decoding The OTU1 signal recovery unit 602 with mapping function, and the time division multiplexing unit 617 used to complete the time division multiplexing conversion from 4 low-level ODU1 signals to ODU2 signals; if the input is 4×ODU1 signals, the inverse adaptation device of ODU2 According to the signal flow direction, it includes: ODU1 frame alignment unit 615, ODU1 signal recovery unit 601 with ODU1 descrambling function, and time division multiplexing unit 617 for completing multiple low-level ODU1 signals to ODU2 signals.

If the input is an OTU2[3:0] signal, the inverse adaptation device of ODU2 includes in sequence according to the signal flow: 4 OTU2[3:0] frame alignment units 604 for OTU2[3:0] frame alignment , an OTU2FIFO merging unit 612 for converting OTU2[3:0] parallel signals to serial OTU2 signals, and an OTU2 signal recovery unit 606 for completing OTU2 descrambling, FEC decoding and ODU2 demapping functions to form ODU2; if input is the ODU2[3:0] signal, then the reverse adaptation device of ODU2 includes in sequence according to the signal flow: 4 ODU2[3:0] frame alignment units 603 for ODU2[3:0] frame alignment, using The ODU2FIFO merging unit 611 that completes the conversion of the ODU2[3:0] parallel signal to the serial ODU2 signal, and the ODU2 signal recovery unit 605 that completes the ODU2 descrambling function.

For the signal that needs to be inversely adapted to ODU3, if the input is a 16×OTU1 signal, the inverse adaptation device of ODU3 includes in sequence according to the signal flow: OTU1 frame alignment unit 616 and 16 descrambling, FEC decoding and ODU1 decoding OTU1 signal restoration unit 602 with mapping function, and time division multiplexing unit 618 for time division multiplexing conversion from multiple low-level ODU1 signals to ODU3 signals; if the input is 16×ODU1 signal, then ODU3 inverse adaptation device According to the signal flow direction, it includes: ODU1 frame alignment unit 615, 16 ODU1 signal recovery units 601 with descrambling function, and time division multiplexing unit 618 for completing multiple low-level ODU1 signals to ODU3 signals. .

If the input is 4×OTU2[3:0] signal, the inverse adaptation device of ODU3 includes: 4×OTU2[3:0] frame alignment for 4×OTU2[3:0] Frame alignment unit 604, 4 OTU2FIFO merging units 612 for converting OTU2[3:0] parallel signals to serial OTU2 signals, 4 OTU2 signal recovery for OTU2 descrambling, FEC decoding and ODU2 demapping functions Unit 606, and time division multiplexing unit 619; if the input is a 4×ODU2[3:0] signal, the inverse adaptation device of ODU3 includes in sequence according to the signal flow: for 4×ODU2[3:0] frame alignment 4×ODU2[3:0] frame alignment unit 603, four ODU2FIFO merging units 611 for converting ODU2[3:0] parallel signals to serial ODU2 signals, and ODU2 signals for completing ODU2 descrambling functions recovery unit 605, and time division multiplexing unit 619.

If the input is an OTU3[15:0] signal, the inverse adaptation device of ODU3 includes in sequence according to the signal flow: an OTU3[15:0] frame alignment unit 608 for OTU3[15:0] frame alignment, using OTU3FIFO merging unit 614 for converting OTU3[15:0] parallel signals to serial OTU3 signals, and OTU3 signal recovery unit 610 for OTU3 descrambling, FEC decoding and ODU3 demapping functions to form ODU3; if the input is ODU3 [15:0] signal, the inverse adaptation device of ODU3 includes in sequence according to the signal flow: an ODU3[15:0] frame alignment unit 608 for ODU3[15:0] frame alignment, used to complete ODU3[15:0] :0] The ODU3FIFO merging unit 613 for converting parallel signals to serial ODU3 signals, and the ODU3 signal recovery unit 609 for ODU3 descrambling to form ODU3.

Wherein, the above-mentioned ODUk/OTUk (k=1, 2, 3) signal recovery unit is sometimes collectively referred to as a signal recovery unit in the present invention, and the ODU1/OTU1, ODU2[3:0]/OTU2[3:0] , ODU3[15:0]/OTU3[15:0] frame alignment unit is also collectively referred to as frame alignment unit sometimes, and the ODUk/OTUk (k=1, 2, 3) FIFO merging unit is also collectively referred to as merging unit.

A relatively complete system structure that can realize unified scheduling based on all connection signals ODU1/ODU2/ODU3 specified in the current ITU-T G.709 protocol, as shown in Figure 7. The system has three types of interfaces: OTU1, OTU2 and OTU3. For OTU1, OTU2 and OTU3 respectively, and centralize in the asynchronous cross network slice for unified scheduling.

The signal dispatching system of Fig. 7 includes:

The asynchronous crossover network chip is used for cross scheduling of signals. All interface signals of the asynchronous crossover network chip are at the 2.5Gbps level (that is, belong to the 2.5Gbps range);

The Map unit completes the mapping conversion from ODUk to OTUk signals, and sequentially performs ODUk mapping, OTUk overhead insertion, OTUk framing, forward error correction (FEC) coding, and scrambling operations on the input signals;

The Demap unit completes the demapping conversion from OTUk signals to ODUk signals, and sequentially performs OTUk framing, descrambling, FEC decoding, OTUk overhead termination, and ODUk demapping operations on the input signals;

The time-division multiplexing unit completes the time-division multiplexing process from multiple ODU1/2 signals to higher-level ODU2/3 signals. The process is a transparent asynchronous mapping and multiplexing process, which ensures the complete transparent transmission of multiple ODU1/2 signals. Regarding the specific time division multiplexing method, Section 19 of ITU-T G.709 has a detailed definition.

The time-division multiplexing unit completes the time-division multiplexing process from the time-division multiplexed ODU2/3 signal to multiple low-level ODU1/2 signals. Completely transparent transmission of signals, demultiplexing is the reverse process of time division multiplexing, which is also defined in detail in section 19 of ITU-TG.709.

The ODU2FIFO merging unit 611 and the ODU3FIFO merging unit 613 complete the conversion of the parallel signals of ODU2[3:0] and ODU3[15:0] on the side of the asynchronous crossover network chip to the serial ODU2 and ODU3 signals. The conversion process is a physical merging transformation process.

The ODU2 splitting unit 505 and the ODU3 splitting unit 509 use the method of channelization and framing to complete the conversion of the serial ODU2 and ODU3 signals to the parallel signals of ODU2[3:0] and ODU3[15:0] in the direction of the asynchronous crossover network, as A physical split transformation process.

The dotted line box in Figure 7 shows the above-mentioned adaptation/inverse adaptation unit, wherein, in the input direction of the signal to the asynchronous cross network, there is also an ODUk signal generation unit, and in the opposite direction, there is also an ODUk framing unit The alignment unit and the signal recovery unit, k=1, 2, 3, are not shown in FIG. 7 for the sake of simplification, since these units correspond to conventional technologies commonly used in signal processing.

The signal scheduling process of the system is described as follows:

For the input OTU1 (1×ODU1) signal mapped by ODU1, after being converted into an electrical signal by the O/E unit, it enters the Demap unit for demapping processing and converts it into 1×ODU1, and performs ODU framing in the adapter device , scrambling code, etc., and send them to the asynchronous cross-connect network slice for asynchronous cross-connect scheduling.

Here, for the convenience of expression, n×ODUk or n×ODUk[m:0] is used to represent n channels of ODUk signals or ODUk[m:0](m+1)bit parallel signals, where k=1,2,3.

For the input OTU2 (4×ODU1) signal formed by mapping and multiplexing of 4 channels of ODU1, after being converted into an electrical signal by the O/E unit, it enters the Demap unit for demapping processing and converts it into 1×ODU2, and then enters the adapter device , demultiplexed into 4×ODU1 in the time-division multiplexing unit, and after ODU framing, scrambling, etc., it is sent to the asynchronous cross-connect network chip for asynchronous cross-connect scheduling.

For the input OTU3 (16×ODU1) signal formed by mapping and multiplexing of 16 channels of ODU1, after being converted into an electrical signal by the O/E unit, it enters the Demap unit for demapping processing and converts it into 1×ODU3, and then enters the adapter device , in which the time division multiplexing unit demultiplexes into 16×ODU1, and after ODU framing, scrambling and other processing, it is sent to the asynchronous cross-connect network chip for asynchronous cross-connect scheduling.

For the input OTU2 (1×ODU2) signal mapped by 1 ODU2, after being converted into an electrical signal by the O/E unit, it enters the Demap unit and converts it into a 1×ODU2 signal; enters the adapter device, and performs ODU conversion After the frame and scrambling are processed, since the rate of each ODU2 serial signal has reached the 10Gbps level, the asynchronous crossover network cannot meet its transmission requirements, and the rate must be reduced. Therefore, the ODU2 signal needs to enter the ODU2 splitting unit 505 , split into 1×ODU2[3:0] parallel signal form, and the single-wire rate of the parallel signal is reduced to 2.5Gbps level; in this way, the split ODU2[3:0] parallel signal can enter the asynchronous cross-connect unit for asynchronous cross-connect scheduling .

For the input OTU3 (1×ODU3) signal mapped by 1 channel ODU3, after the O/E unit converts it into an electrical signal, it enters the Demap unit and converts it into a 1×ODU3 signal; enters the adapter device, and performs ODU framing, After scrambling and other processing, since the rate of each ODU3 serial signal has reached the 40Gbps level, the asynchronous crossover network cannot meet its transmission requirements, and the rate must be reduced. Therefore, the ODU3 signal must enter the ODU3 splitting unit 509 again, and the It is divided into 1×ODU3[15:0] parallel signal form, and the single-wire rate of the parallel signal is reduced to 2.5Gbps level; in this way, the split ODU3[15:0] parallel signal can enter the asynchronous cross-connect unit for asynchronous cross-connect scheduling.

For the input OTU3 (4×ODU2) signal multiplexed by 4-way ODU2 mapping, after being converted into an electrical signal by the O/E unit, it enters the Demap unit and converts it into a 1×ODU3 signal; when entering the adapter device, first 1× When the ODU3 signal enters, the demultiplexing unit 513 converts it into a 4×ODU2 signal, and performs ODU framing, scrambling and other processing in the ODU2 signal generating unit 503; after that, since the rate of each ODU2 serial signal reaches the 10Gbps level, asynchronous The crossover network slice cannot meet its transmission requirements, and the rate must be reduced. Therefore, each ODU2 signal enters four ODU2 splitting units 505, and is split into ODU2[3:0] parallel signal forms using channelized framing. The single-wire rate of the parallel signal is reduced to 2.5Gbps; in this way, the split 4×ODU2[3:0] parallel signal enters the asynchronous cross-connect unit for asynchronous cross-connect scheduling.

On the basis of 2.5Gbps, the asynchronous cross-connect unit performs asynchronous cross-connect scheduling between similar signals, that is, scheduling between the input ODU1 signals, scheduling between the input ODU2[3:0], and scheduling between the input ODU3[15 :0], that is, the scheduling function of ODU1/ODU2/ODU3 particles is completed. The output signals after scheduling are reversely processed according to different mapping and multiplexing requirements.

The reverse process is described as follows:

For the situation where OTU1 (1×ODU1) output is required after scheduling, according to the mapping relationship specified in ITU-T G.709 and Figure 7, it can be seen that the corresponding signal output from the asynchronous crossover network chip should be 1×ODU1 .1×ODU1 performs simple ODU framing in the reverse adaptation device (if it is an OTU1 signal output with multiple optical ports, ODU1 frame alignment is required) and descrambling, enters the Map unit to convert to OTU1 (1×ODU1) , which is converted into an optical signal by the E/O unit and output.

For the situation where OTU2 (4×ODU1) output is required after scheduling, according to the mapping relationship specified in ITU-T G.709 and Figure 7, it can be seen that the corresponding signal output from the asynchronous crossover network chip should be 4×ODU1 The 4×ODU1 first enters the reverse adaptation device. First, the 4×ODU1 signal needs to be frame-aligned and descrambled, and then converted into a 1×ODU2 signal in the time division multiplexing unit 617, and then enters the Map unit to be converted into an OTU2 (4× ODU1), which is converted into an optical signal by the E/O unit and output.

For the situation where OTU3 (16×ODU1) output is required after scheduling, according to the mapping relationship specified in ITU-T G.709 and Figure 7, it can be seen that the corresponding signal output from the asynchronous crossover network chip should be 16×ODU1 The 16×ODU1 first enters the inverse adaptation device, first performs frame alignment and descrambling on the 16×ODU1 signal, then converts it into a 1×ODU3 signal in the time division multiplexing unit 618, and then enters the Map unit to convert it into an OTU3 (16×ODU1 ), which is converted into an optical signal by the E/O unit and output.

For the situation where OTU2 (1×ODU2) output is required after scheduling, according to the mapping relationship specified in ITU-T G.709 and Figure 7, it can be seen that the corresponding signal output from the asynchronous crossover network chip should be 1×ODU2 [3:0]. 1×ODU2[3:0] first enters the inverse adaptation device, and after being processed by the ODU2[3:0] frame alignment unit 603 for frame alignment, it is combined into a 1×ODU2 signal in the ODU2FIFO merging unit 611, and then The ODU2 signal recovery unit 605 performs descrambling processing; then enters the Map unit to convert it into OTU2 (1×ODU2), converts it into an optical signal through the E/O unit, and outputs it.

For the situation where OTU3 (1×ODU3) output is required after scheduling, according to the mapping relationship specified in ITU-T G.709 and Figure 7, it can be seen that the corresponding signal output from the asynchronous crossover network chip should be 1×ODU3 [15:0]. 1×ODU3[15:0] first enters the inverse adaptation device, and after the frame alignment processing of the ODU3[15:0] frame alignment unit, it is combined into a 1×ODU3 signal in the ODU3FIFO merging unit 613, and the signal The recovery unit performs descrambling processing; then enters the Map unit and converts it into an OTU3 signal (1×ODU3), and then outputs it after being converted into an optical signal by the E/O unit.

For the situation where OTU3 (4×ODU2) output is required after scheduling, according to the mapping relationship specified in ITU-T G.709 and Figure 7, it can be seen that the corresponding signal output from the asynchronous crossover network chip should be 4 channels ODU2[3:0]. The 4×ODU2[3:0] signals first enter the reverse adaptation device respectively, and after being processed by the ODU2[3:0] frame alignment unit 603 for frame alignment, they are combined into 4×ODU2 signals in the ODU2FIFO merging unit 611, And the ODU2 signal recovery unit 605 performs descrambling processing, and then enters the time division multiplexing unit to convert into 1×ODU3 signal; then enters the Map unit to convert into OTU3 (4×ODU2), and converts it into an optical signal through the E/O unit before outputting.

In addition, control information bits and FEC error correction functions can be added to the ODU1 or ODU2/ODU3 backplane signals, which is more conducive to the transmission of asynchronous cross-mesh backplane signals.

A specific method may be to set a corresponding OTUk signal generation/restoration unit 701 in the adaptation/inverse adaptation device, where k=1,2,3. .

The OTUk signal generating unit sequentially completes the functions of ODUk mapping, OTUk framing, FEC encoding and scrambling; the OTUk signal recovery unit sequentially completes the functions of OTUk descrambling, FEC decoding and ODUk demapping.

The above ODUk mapping/demapping, OTUk framing, FEC encoding and decoding, and OTUk scrambling and descrambling are all existing mature technologies, so their internal specific structures will not be repeated here.

The mapping structure from ODUk to OTUk can be seen in Figure 8. Compared with ODUk, OTUk adds frame delimitation overhead (FA OH) and OTUk overhead (OTUk OH) in columns 1 to 14 of the first row, adding 3825 to 4080 columns, and filled with OTUk FEC coding (OTUk FECRS).

In this way, the OTUk signal on the side of the asynchronous crossover network chip is a signal with FEC encoding, so that the transmission performance of the backplane can be greatly improved, and a certain amount of bit errors can be corrected.

At this time, the input and output signals of the asynchronous crossover network chip are all OTU type signals, and cross scheduling is performed on OTU1 or OTU2[3:0] and OTU3[15:0] parallel signals of the same level as OTU1.

For the sake of clarity, the following takes the OTU3 (4×ODU2) signal scheduling process as an example to illustrate. The input OTU3 (4×ODU2) is converted into an electrical signal by the O/E unit, and then enters the Demap unit to be converted into 1×ODU3 When the 1×ODU3 signal enters, the demultiplexing unit converts it into a 4×ODU2 signal. Afterwards, ODU2 mapping is performed, and 4×OTU2 is formed through OTU framing, FEC coding and scrambling. Each 4×OTU2 signal is then separately Enter 4 OTU2 splitting units 506, respectively split into OTU2[3:0] parallel signal form, the single-wire rate of the parallel signal is reduced to 2.5Gbps level; the split 4×OTU2[3:0] parallel signal finally enters the asynchronous The cross-connect unit performs asynchronous cross-connect scheduling.

Among the signals output after being dispatched by the asynchronous cross network chip, there are 4 channels of OTU2[3:0] parallel signals, which are processed by 4×OTU[3:0] frame alignment and enter the OTU2FIFO merging unit 612 to be combined into 4×OTU2 signals , and then through descrambling, FEC decoding and ODU2 demapping to form 4×ODU2, and then enter the time division multiplexing unit to convert into 1×ODU3 signal, and then enter the Map unit to convert into OTU3 (4×ODU2), and convert it to E/O unit After the optical signal is output.

The scheduling process of other signals can be deduced by analogy, and will not be repeated here.

In the input and output direction of the signal to the asynchronous cross network chip, the O/E, E/O unit, Demap/Map unit, time-division multiplexing/time-division multiplexing unit, ODU mapping, OTU framing, and FEC coding mentioned above The scrambling code/OTU descrambling, FEC decoding, and ODU demapping units all adopt existing technologies and can be realized by using existing devices. But for above-mentioned splitting process, what used in the present invention is a kind of method of channelization framing, and existing channelization framing method is to split the frame of each OTU or ODU into 4 ways with 16 byte blocks Channel transmission, but this method is only applicable to ODU2/OTU2 signals, and this method can be used for ODU2/OTU2 signals in the scheduling process of the present invention. However, in order to facilitate unified scheduling of signals of different rates, the present invention proposes a new splitting method that is generally applicable to various OTN signals.

This method takes the frame as the unit, buffers the signal in the order of the frame, and sends out the data of the n frame in parallel every time the n frame is full, and repeats the above process; where n is the current signal to be split into road number.

Of course, the splitting method applicable to the present invention is not limited thereto, any other splitting method that can complete the channelization of high-speed signals above the level of ODU1 into frames is allowed.

According to the above splitting method, the structure of the ODU splitting unit of the ODU2 signal in the signal dispatching system of the present invention is shown in Figure 9, including: a framing module, a write address generation module, a read address generation module, a 4-frequency division module, and 8 first-in-first-out memories FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, FIFO_6, FIFO_7, FIFO_8. Among them, the 4 frequency division module is used to reduce the frequency of the input signal to 1/4 of the original frequency; the write address generation module is used to control the writing frequency of each FIFO write pointer; the read address generation module is used to control each FIFO The readout frequency of the read pointer; the 8 FIFOs are divided into two groups, each of which is a group of 4, and each FIFO can store the data of one ODU2 frame.

The signal splitting process specifically includes:

The input ODU2 signal has an accompanying synchronous clock, and the frame signal FP is obtained after frame search and processing by the framing module. This process is a mature existing technology and will not be described again. The synchronous clock and the frame signal enter the write address generation module together to generate the write address W_Addr and the write permission WE1, WE2,..., WE8, respectively enter the W_Addr and WE terminals of each FIFO, and control the writing of the FIFO. The generation rules of the write address and write permission are: the FIFO write address changes cyclically, so that the ODU2 data is serially written into each FIFO in turn; the write permission signal is valid in turn, so that the first group of 4 FIFOs is filled and then jumps to Another set of FIFOs. Among them, in Figure 9, the corresponding FIFOs in the two groups share a set of write address lines W_Addr to receive write address signals, that is, FIFO_1 and FIFO_5, FIFO_2 and FIFO_6, FIFO_3 and FIFO_7, FIFO_4 and FIFO_8 share a set of two pairs, so that the Wiring, of course, also allows a set of write address lines W_Addr to be provided for each FIFO.

The clock Clk is also input to the frequency division module by 4, and the output signal after frequency division by the frequency division module by 4 and the frame signal FP are respectively input to the Clk and FP terminals of the read address generation module, and the read address generation module generates the read address R_Addr and the read permission RE1, RE2, the read address R_Addr enters the R_Addr of each FIFO respectively; read allows RE1 to enter the first group of FIFO_1, FIFO_2, FIFO_3, FIFO_4, and RE2 to enter the second group of FIFO_5, FIFO_6, FIFO_7, FIFO_8 , respectively control the readout of each FIFO. The generation rule of the read address and the read permission is: the read address changes cyclically, and the read permission signals RE1 and RE2 are alternately valid, so that the data in the two groups of FIFOs are alternately read in parallel, wherein the corresponding FIFOs in the two groups in Fig. 9 share one Group read address lines, that is, FIFO_1 and FIFO_5, FIFO_2 and FIFO_6, FIFO_3 and FIFO_7, FIFO_4 and FIFO_8 share a group of two, of course, it can also be set not to share. In addition, the generated read address signal needs to ensure that the set of FIFOs currently performing read operations is staggered from the set of FIFOs currently performing write operations, and read and write in a ping-pong manner, that is, during the period of writing FIFO_1 to FIFO_4, read FIFO_5 to FIFO_8; When writing FIFO_5 to FIFO_8, read FIFO_1 to FIFO_4. Wherein, it can be seen that the reading frequency of the FIFO is 1/4 of the writing frequency.

ODU2 data is sequentially written into FIFO_1, FIFO_2, FIFO_3 and FIFO_4, and each FIFO stores one frame of data; after FIFO_1 to FIFO_4 are written into one frame, jump to FIFO_5, FIFO_6, FIFO_7 and FIFO_8 to write in the same order, and at the same time , the read pointer starts to read data from FIFO_1, FIFO_2, FIFO_3 and FIFO_4 in parallel at the same time, forming low-speed parallel data ODU2[0], ODU2[1], ODU2[2] and ODU2[3] output, and the reading rate is ODU2 rate 1/4 of that, so that the read and write actions are alternated, that is, the conversion from ODU2 signal to parallel signal ODU2[3:0] (ODU1 rate level signal) is completed.

In this way, the ODU2[3:0] signal obtained after splitting is still a framed signal, including the FA area; the data delay is 4×T _ODU2 =4×12.191 μs=48.764 μs.

The situation of the OTU2 signal is basically the same as that of the ODU2, except that each FIFO_x of the OTU splitting unit needs to store one frame of OTU2 data.

In the output direction of the signal from the asynchronous cross network chip to the optical port, the above-mentioned E/O unit, Map unit, time division multiplexing unit, and ODUk/OTUk signal recovery unit all adopt the existing technology at present, and the existing technology can be used device implementation. However, since n×ODUk[m:0] is received from the cross network, the ODUk/OTUk framing alignment unit and ODUk/OTUk FIFO merging unit, k=1, 2, 3, must adopt a new technology. The following is an implementation scheme provided by the present invention:

Since the ODUk/OTUk frame alignment unit described here is closely related to the ODUk/OTUk FIFO merging unit, the two will be described together below, as shown in Figure 10, taking the processing of the ODU2 signal as an example, including: The board interface module, the frame alignment module and the ODU2FIFO merging unit 611 , wherein the backplane interface module and the frame alignment module belong to the ODU frame alignment unit 1001 .

The ODU2[3:0] after cross-scheduling enters the backplane interface module, recovers the clock data of the input 4-way parallel signals, inputs the restored n-way clock and data signals to the frame alignment module, and selects one of them One clock is sent to the frame alignment module and the ODU2FIFO merging unit 611 respectively as a reference clock.

The fixed frame alignment module performs a frame search on each signal, finds the frame start positions of the 4 signals, aligns the frame start positions of the 4 signals to the same frame phase, and outputs the 4-way aligned data and reference The frame signal is sent to the ODU2FIFO merging unit 611.

The ODU2FIFO merging unit 611 is internally provided with two sets of FIFOs, 4 in each set, and each FIFO stores one frame of data. The aligned ODU2[3:0] parallel data and the reference frame are written into a set of FIFOs in parallel using a low-speed clock frame by frame for alignment processing; The other group of FIFOs reads data and sends it out, and the two groups of FIFOs use ping-pong reading and writing to prevent read and write conflicts. Finally, the ODU2 data is obtained; the data delay is 4×T _ODU2 =4×12.191 μs=48.764 μs.

Wherein, the structure of the backplane interface module is shown in Figure 11, including: 4 clock data recovery modules (CDR) and a selector 1101 for selecting one of four, each parallel signal ODU2[0] of ODU2[3:0], ODU2[1], ODU2[2] and ODU2[3] respectively enter 4 CDRs to recover the data ODU2[n] and the corresponding clock signal ODU2[n]Clk and output them, where n=0, 1, 2, 3; The recovered 4 clock signals ODU2[n]Clk enter into the one-of-four selector 1101 at the same time, and select one clock output as the reference clock according to the clock selection control signal. Among them, since the ODU2[3:0] signal is split from the same ODU2 signal, the CDR clock signal is the same as the clock source, and one of the CDR clocks can be selected as the read clock of the frame-aligned FIFO to complete ODU2[3: 0] The frame alignment of the data makes up for the delay difference caused by the cross-scheduling and transmission of the 4-way signals.

The frame alignment module structure is shown in Figure 12, including: 4 frame search modules, 4 FIFOs and corresponding write address generation modules, as well as a frame phase alignment module and a read address generation module.

The data ODU2[n] (n=0, 1, 2, 3) and the clock ODU2[n]Clk (n=0, 1, 2, 3) of each channel recovered by CDR first enter the frame search module for frame search , search out the frame phase of each signal and output to the frame phase alignment module and the write address generation module of each FIFO; the write address generation module also receives the corresponding clock signal, generates the write address and outputs it to the corresponding FIFO respectively; the frame phase alignment module Align the frame phase of each signal to an appropriate position according to the received reference clock, generate a reference frame signal and output it to the read address generation module and the subsequent ODU2FIFO merging unit 611; the read address generation module receives the reference frame signal and reference clock generation The read address is output to each FIFO; each FIFO performs read and write operations cyclically under the action of the read and write address, and aligns the 4-way signals to the same frame phase. Among them, the frame phase is the frame signal obtained from the frame search of one of the 4 channels, that is, the internal automatic frame alignment operation. Since the clock frequency of the read and write addresses is the same, the FIFO will not overflow or be empty under the appropriate read and write address differences. The read-write address difference is determined by the frame phase alignment module and is related to the size of the FIFO.

Referring to FIG. 13 , it is a timing diagram of the frame alignment process. Since the size of each FIFO is limited, the maximum deviation of each frame signal cannot exceed the size range of the FIFO, and the aligned reference frame signal phase should be located at a certain amount of delay after the most backward frame phase, but cannot exceed the FIFO The range of , that is, the phase of the reference frame signal should fall within the solid-line frame area shown in FIG. 13 .

The structure of the ODU2FIFO merging unit 611 is shown in Figure 14, including: a write address generation module, a read address generation module, a 4 frequency multiplier module, and 8 first-in-first-out memories FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, FIFO_6, FIFO_7 and FIFO_8. Among them, 8 FIFOs are divided into two groups, and each FIFO stores a frame of data.

The reference clock and reference frame signals enter the write address generation module to generate the write address W_Addr and write enable signals WE1 and WE2 of each FIFO. The generation rule is: the FIFO write address changes cyclically, WE1 and WE2 are valid alternately, and the aligned ODU2[3:0 ] Parallel data ODU2[0] to ODU2[3] are written in parallel to the first group of FIFOs, where the corresponding FIFOs in the two groups can share a group of write address lines, namely FIFO_1 and FIFO_5, FIFO_2 and FIFO_6, FIFO_3 and FIFO_7, FIFO_4 Share a group with FIFO_8 two by two, the write rate is the reference clock rate, and then jump to another group of FIFOs. The quadrupled frequency clock signal output by the reference clock after passing through the quadrupling frequency module enters the read address generation module together with the reference frame signal to generate the read address of each FIFO and read enable signals RE1, RE2, RE3, RE4, RE5, RE6, RE7, RE8, the generation rule is: the FIFO read address changes cyclically, and the read enable signal is valid in turn, so that after reading the first group of 4 FIFOs, it jumps to another group of FIFOs. Wherein, the corresponding FIFOs in the two groups can share a set of read address lines, that is, FIFO_1 and FIFO_5, FIFO_2 and FIFO_6, FIFO_3 and FIFO_7, and FIFO_4 and FIFO_8 share a set of two pairs. The data in the FIFOs are read out serially, and the set of FIFOs currently being read is staggered from the set of FIFOs currently being written. That is, the write pointer of FIFO is written into FIFO_1, FIFO_2, FIFO_3 and FIFO_4 in parallel, and then written into FIFO_5, FIFO_6, FIFO_7 and FIFO_8 in parallel, and the write rate is the reference clock rate; at this time, the read pointer starts from FIFO_1, FIFO_2, FIFO_3 and FIFO_4 reads data sequentially. The read rate is 4 times the reference clock. Thus, the conversion of four ODU2 parallel signals ODU2[3:0] (2.5Gbps level signal) to one ODU2 signal is completed.

The merging process of OTU2 signals can be realized by the same method, except that FIFO_x of the OTU2FIFO merging unit 612 needs to store one frame of OTU2 data.

The structure of the ODU/OTU splitting unit of the ODU3/OTU3 signal in the signal dispatching system of the present invention is similar to the splitting unit of the ODU2/OTU2 signal, including: fixed frame module, write address generation module, read address generation module, 16 frequency division module and 32 first-in-first-out memories (FIFOs) FIFO_1, FIFO_2, ..., FIFO_32.

The splitting process of ODU3/OTU3 is basically the same as the splitting process of ODU2/OTU2 above, except that 16 FIFOs are used as a group to read and write in ping-pong mode, and the clock frequency of the FIFO read pointer is 1/16 of the clock frequency of the write pointer .

The structure of the ODU3/OTU3 frame alignment unit and the ODU3/OTU3FIFO merging unit of the ODU3/OTU3 signal is also similar to that of the ODU2/OTU2 signal. The backplane interface module includes 16 CDRs and 16 selectors; the ODU3/OTU3 The frame alignment module includes 16 frame search modules, 16 FIFOs and corresponding write address generation modules, as well as a frame phase alignment module and a read address generation module; the ODU3/OTU3FIFO merging unit includes a write address generation module, a read address A generation module, a 16-multiplier module, and 32 first-in-first-out memories FIFO_1, FIFO_2, . . . , FIFO_32.

Similarly, the merging process of ODU3/OTU3 is basically the same as the merging process of ODU2/OTU2 above, except that 16 FIFOs are used as a group to read and write in a ping-pong manner, and the clock of the FIFO read pointer is 16 times that of the write pointer clock.

The splitting/combining unit described above is just an example, and other ways can also be used to realize the conversion between the high-level signal and the ODU1/OTU1 rate level signal, which is not limited in the present invention.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims (15)

1, the signal dispatching method in a kind of optical transport network is characterized in that, comprising:

The light signal that is received is treated as the signal of telecommunication through opto-electronic conversion, separates again after mapping handles, signal rate is fitted to a unified particle rank, in based on other asynchronous cross matrix of this particle level, carry out asynchronous cross scheduling and handle;

The adaptive process of described signal rate comprises:

For the speed of current demand signal greater than described other situation of particle level,

If received signal is multiplexing the forming of other low speed signal mapping of described particle level by multichannel speed, then demultiplexed into the described low speed signal of multichannel the current demand signal time-division;

If received signal is formed greater than other high speed signal mapping of described particle level by one tunnel speed, then current demand signal being split into multichannel speed is described other parallel signal of particle level;

If received signal shines upon multiplexing forming by speed more than one tunnel greater than other high speed signal of described particle level, then demultiplexed into the described high speed signal of multichannel the current demand signal time-division, it is described other parallel signal of particle level that the every road high speed signal that obtains is split into multichannel speed.

2, method according to claim 1 is characterized in that, the adaptive process of described signal rate also comprises:

After separating the mapping processing,, then current demand signal is directly sent into described asynchronous cross matrix and carried out asynchronous cross scheduling if the speed of current demand signal equals described particle rank;

If the speed of current demand signal is less than described particle rank, then the signal of multichannel and current demand signal same kind being merged into one tunnel speed is described other signal of particle level.

3, method according to claim 1 and 2 is characterized in that, the light signal of described reception is the G.709 light signal under the agreement of ITU-T.

4, method according to claim 3 is characterized in that, described unified particle rank is an ODU1 speed rank;

If the OTU1 of the light signal that is received for being formed by 1 road ODU1 mapping, the adaptive process of then described signal rate is carried out after ODU framing, scrambler handle for the ODU1 that will separate the mapping back and form, and sending into described asynchronous cross matrix carries out asynchronous cross scheduling;

If the light signal that is received is for shining upon the multiplexing OTU2 that forms by 4 road ODU1, the adaptive process of then described signal rate is after decomposition multiplex will be 4 road ODU1 in the time of will separating the ODU2 that forms after the mapping, to carry out ODU framing, scrambler processing;

If the light signal that is received is for shining upon the multiplexing OTU3 that forms by 16 road ODU1, the adaptive process of then described signal rate is after decomposition multiplex will be 16 road ODU1 in the time of will separating the ODU3 that forms after the mapping, to carry out ODU framing, scrambler processing;

If the OTU2 of the light signal that is received for forming by 1 road ODU2 mapping, the adaptive process of then described signal rate is carried out after ODU framing, scrambler handle for the ODU2 that will separate the mapping back and form, and uses the method for channelizing framing to be split as 4 tunnel speed and is other parallel signal of ODU1 speed level;

If the OTU3 of the light signal that is received for forming by 1 road ODU3 mapping, the adaptive process of then described signal rate is carried out after ODU framing, scrambler handle for the ODU3 that will separate the mapping back and form, and uses the method for channelizing framing to be split as 16 tunnel speed and is other parallel signal of ODU1 speed level;

If the light signal that is received is for shining upon the multiplexing OTU3 that forms by 4 road ODU2, the adaptive process of then described signal rate is after decomposition multiplex will be 4 road ODU2 in the time of will separating the ODU3 of mapping back formation, carry out ODU framing, scrambler processing, use the method for channelizing framing to be split as 4 tunnel speed respectively the every road ODU2 that obtains and be other parallel signal of ODU1 speed level.

5, method according to claim 4 is characterized in that, described processing procedure of separating mapping comprises: OTU decides frame, descrambling, fec decoder, OTU expense termination, ODU separates mapping.

6, according to any described method in the claim 2,4,5, it is characterized in that the process of described fractionation is: after signal is carried out deciding the frame processing, order is frame by frame carried out buffer memory, after being filled with the n frame, the data parallel of this n frame being sent, and repeat the process of above-mentioned fractionation; Wherein n is the way that current demand signal is desired to split into.

7, method according to claim 3 is characterized in that, described processing procedure of separating mapping further comprises after ODU separates mapping executing: ODU mapping, OTU framing, FEC coding increase FEC zone, scrambler; Described unified particle rank is an OTU1 speed rank;

If the OTU1 of the light signal that is received for forming by 1 road ODU1 mapping, the adaptive process of then described signal rate will be for after will separating the ODU1 signal that forms after the mapping processing procedure and carrying out ODU1 mapping, OTU1 framing, FEC coding, scrambler processing, form OTU1, send into described asynchronous cross matrix and carry out asynchronous cross scheduling;

If the light signal that is received is for shining upon the multiplexing OTU2 that forms by 4 road ODU1, decomposition multiplex was 4 road ODU1 signals when adaptive process of then described signal rate was shone upon the ODU2 that forms after the processing procedure for separating, after carrying out ODU1 mapping, OTU1 framing, FEC coding, scrambler processing, form 4 road OTU1, enter asynchronous cross scheduling;

If the light signal that is received is for shining upon the multiplexing OTU3 that forms by 16 road ODU1, decomposition multiplex was 16 road ODU1 signals when adaptive process of then described signal rate was shone upon the ODU3 that forms after the processing procedure for separating, after carrying out ODU1 mapping, OTU1 framing, FEC coding, scrambler processing, form 16 road OTU1, enter asynchronous cross scheduling;

If the OTU2 of the light signal that is received for forming by 1 road ODU2 mapping, the adaptive process of then described signal rate will be for after will separating the ODU2 that forms after the mapping processing procedure and carrying out ODU2 mapping, OTU2 framing, FEC coding, scrambler processing, form OTU2, use the method for channelizing framing to be split as 4 tunnel speed, enter asynchronous cross scheduling as other parallel signal of OTU1 speed level;

If the OTU3 of the light signal that is received for forming by 1 road ODU3 mapping, the adaptive process of then described signal rate will be for after will separating the ODU3 that forms after the mapping processing procedure and carrying out ODU3 mapping, OTU3 framing, FEC coding, scrambler processing, form OTU3, use the method for channelizing framing to be split as 16 tunnel speed, enter asynchronous cross scheduling as other parallel signal of OTU1 speed level;

If the light signal that is received is for shining upon the multiplexing OTU3 that forms by 4 road ODU2, decomposition multiplex was 4 road ODU2 signals when adaptive process of then described signal rate was shone upon the ODU3 that forms after the processing procedure for separating, after carrying out ODU2 mapping, OTU2 framing, FEC coding, scrambler processing, form 4 road OTU2, use the method for channelizing framing to be split as 4 tunnel speed respectively the every road OTU2 that obtains, enter asynchronous cross scheduling as other parallel signal of OTU1 speed level.

8, method according to claim 7 is characterized in that, the process of described fractionation is: signal order is frame by frame carried out buffer memory, after being filled with the n frame, the data parallel of this n frame being sent, and repeat the process of above-mentioned fractionation; Wherein n is the way of desiring to split into of current demand signal.

9, according to any described method in the claim 1,2,4,5,7,8, it is characterized in that, after described asynchronous cross scheduling is handled, further comprise: carry out the inverse process of the adaptive process of described signal rate, shine upon and export after processing and electric light are converted into light signal.

10, the signal dispatching system in a kind of optical transport network is characterized in that, comprising:

At least one photoelectric conversion unit, the light signal that is used for receiving is converted to the signal of telecommunication;

At least one separates map unit, is used for that signal is separated mapping and handles;

At least one adaptive device is used for input signal is adapted for unified other signal of particle level; And

Asynchronous cross matrix is used for unified other signal of particle level is carried out asynchronous cross scheduling;

The light signal that receives is after photoelectric conversion unit is converted to the signal of telecommunication, input to and separate map unit, through separating after mapping handles output, enter adaptive device, be adapted to speed and meet and input to asynchronous cross matrix behind described unified other signal of particle level and carry out asynchronous cross scheduling;

If described input signal is multiplexing the forming of other low speed signal mapping of described particle level by multichannel speed, comprise in the described adaptive device: signal generation unit and time-division demultiplexing unit, the time-division demultiplexing unit is used for that decomposition multiplex is described unified other low speed signal of particle level for multichannel speed with by the multiplexing high speed signal that forms of multi-path low speed signal map the time, and exports described signal generation unit to;

If received signal is formed greater than other high speed signal mapping of described particle level by one tunnel speed, comprise in the described adaptive device: it is described unified other parallel signal of particle level that signal generation unit and split cells, split cells are used for the signal that export described signal generation unit processing back is split as multichannel speed;

If received signal shines upon multiplexing forming by speed more than one tunnel greater than other high speed signal of described particle level, comprise in the described adaptive device: signal generation unit, time-division demultiplexing unit and split cells, the time-division demultiplexing unit will be that the described low speed signal of multichannel inputs to described signal generation unit and split cells by the multiplexing high speed signal demultiplexing that forms of multi-path low speed signal map, and the low speed signal that split cells is handled back output with the signal generation unit further is split as described unified other parallel signal of particle level.

11, system according to claim 10 is characterized in that, if the speed of described input signal is described unified particle rank, described adaptive device is the signal generation unit that is used for signal framing, scrambler.

12, system according to claim 10, it is characterized in that, described split cells comprises: decide frame module, write address generation module, read address generating module, n frequency division module and 2n pushup storage FIFO, wherein, n is the signal way of signal output after this split cells splits;

Input signal has with the road synchronised clock, after handling, frame obtains frame signal through deciding searching of frame module, synchronised clock is imported the write address generation module with frame signal, produce write address and write and allow to enter respectively each pushup storage FIFO, control pushup storage FIFO writes, the synchronous signal clock also inputs to the n frequency division module, output behind n frequency division module frequency division inputs to frame signal and reads address generating module, generation is read the address and is read to allow to enter respectively each pushup storage FIFO, and control pushup storage FIFO reads;

The data of input signal order frame by frame writes n pushup storage FIFO successively, write the data parallel output among full n pushup storage FIFO in back, the data of back write other n pushup storage FIFO successively simultaneously, write the data parallel output among the full back described other n pushup storage FIFO.

13, system according to claim 10 is characterized in that, this system further comprises: at least one electrooptic switching element, and the electrical signal conversion that is used for receiving is a light signal;

At least one map unit is used for signal is shone upon processing;

At least one is used for unified other signals reverse of particle level of described asynchronous cross matrix output is adapted for the signal of desired rate against adaptive device;

Asynchronous cross matrix carries out the signal exported behind the asynchronous cross scheduling, enters contrary adaptive device and carries out opposite adaptation and handle, and inputs to map unit, after mapping is handled, enters electrooptic switching element and is converted to light signal.

14, system according to claim 13, it is characterized in that, if the speed of required output signal is described unified particle rank, described contrary adaptive device comprises: decide frame alignment unit and signal recovery unit, describedly decide the frame alignment unit and unified other signal of particle level of asynchronous cross matrix output is carried out deciding to input to the signal recovery unit after the frame registration process carry out exporting after the descrambling code processing;

If required output for by multichannel speed being the multiplexing signal that forms of other low speed signal of described particle level mapping, described contrary adaptive device comprises: decide frame alignment unit, signal recovery unit and time-division multiplexing unit, time-division multiplexing unit is used for exporting after being one road other high speed signal of desired rate level through described multi-path low speed signal time division multiplexing of deciding frame alignment unit and the output of signal recovery unit;

If the signal for forming greater than other high speed signal mapping of described particle level of required output by one tunnel speed, described contrary adaptive device comprises: decide frame alignment unit, signal recovery unit and merge cells, describedly decide the frame alignment unit and every group of described asynchronous cross matrix output unified other parallel signal of particle level carry out deciding to input to merge cells after the frame registration process, merge cells is merged into multi-path parallel signal and is inputed to signal recovery unit descrambling code behind one road other high speed signal of desired rate level and handle back output;

If required output is greater than the multiplexing signal that forms of other high speed signal mapping of described particle level by speed more than one tunnel, described contrary adaptive device comprises: decide the frame alignment unit, the signal recovery unit, time-division multiplexing unit and merge cells, describedly decide the frame alignment unit and every group of described asynchronous cross matrix output unified other parallel signal of particle level carry out deciding to input to merge cells after the frame registration process, merge cells is merged into multi-path parallel signal and is inputed to that to export the time-division multiplexing unit time division multiplexing after signal recovery unit descrambling code is handled to be to export behind one road other high speed signal of desired rate level behind one road signal.

15, system according to claim 14 is characterized in that,

Described merge cells, inside is provided with 2n pushup storage FIFO, each pushup storage FIFO stores frame data, data and frame signals write n pushup storage FIFO successively and carry out registration process, meanwhile, with n times of speed reading of data and output from other n described pushup storage FIFO successively to write operation; Wherein, n is the signal way of signal output after this split cells splits;

Describedly decide the frame alignment unit and comprise:

The backplane interface module, be used for the n road signal of input is carried out clock and data recovery, n road clock after recovering and data-signal inputed to decide the frame alignment module, select wherein one road clock to be sent to respectively and decide frame alignment module and described merge cells as the reference clock;

Decide the frame alignment module, be used for every road signal is carried out frame search respectively, find n road signal frame start position separately, the frame start position of n road signal is all snapped on the identical frame phase place, the data of output n road alignment and frame signals are to described merge cells.

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