CN101090077A - Semiconductor package and its manufacturing method - Google Patents

Abstract

The invention discloses a semiconductor package and a manufacturing method thereof, wherein the semiconductor package comprises: a chip carrier having a plurality of electrical connection points; at least one semiconductor chip mounted on and electrically connected to the chip carrier; a plurality of conductive members disposed and electrically connected to the electrical connection points; and a packaging colloid formed on the chip carrier, covering the semiconductor chip and the conductive member, and at least exposing the side surface of the conductive member out of the packaging colloid. The semiconductor package and the manufacturing method thereof can additionally provide a plurality of electrical contacts, thereby strengthening the electrical function and the application range of electronic products.

Description

Semiconductor package and its manufacturing method

technical field

The present invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package capable of providing additional electrical contacts and its manufacturing method.

Background technique

Due to the substantial growth of various portable products such as communication, network and computer, ball grid array (BGA) package, which can reduce the area of integrated circuit (IC) and has high density and multi-pin characteristics, has gradually become the packaging market. It is the mainstream of the Internet, and is often matched with high-performance chips such as microprocessors, chipsets, and graphics chips to perform higher-speed computing functions. Among them, ball grid array (BGA) is an advanced semiconductor chip packaging technology, which is characterized in that a semiconductor chip is placed on a substrate, and a plurality of solder balls (Solder Ball) arranged in a grid array are arranged on the back of the substrate. , so that more input/output connection terminals (I/O Connection) can be accommodated on the semiconductor chip carrier of the same unit area, which meets the requirements of highly integrated semiconductor chips. The entire package unit is welded and electrically connected through these solder balls connection to external devices.

Furthermore, in order to increase the production capacity of semiconductor packages and save process costs, today’s miniature semiconductor packages are mostly produced in batches, that is, on the surface of a whole chip carrier (chip carrier) through multiple grid-like staggered package boundaries, A plurality of packaging units arranged in a matrix are pre-defined, and after procedures such as die bond, wire bond, and encapsulation, the connection between any adjacent semiconductor packaging units is removed by cutting operation (Singulation). , forming multiple independent semiconductor packages. For example, in order to meet the design requirements of thin, light and small electronic products, the industry has developed a thin ball grid array (TFBGA) package or a land grid array (Land Grid Array; LGA) package that can provide a smaller overall size. The batch method is established on the same substrate. The substrate is pre-divided into multiple packaging areas, and the positions of individual TFBGA packaging units are defined respectively. After the steps of wafer mounting, wire bonding, and molding, the Singulation process is finally carried out. Divide each packaging area and the semiconductor chip placed on it to form multiple LGA packages, or set solder balls on the substrate to form a TFBGA package. Related technologies can refer to US Patent Nos. 5,776,798, 6,593,658, 6,281,047 and other cases.

In addition, the industry has also developed a quad flat no-pin (QFN) package similar to the above-mentioned TFBGA package, which uses a lead frame as a chip carrier. It also arranges the lead frame in a matrix, and the semiconductor chip is placed on the lead frame. After the steps of wire bonding, package molding and other steps are carried out, the cutting process is carried out to form multiple QFN packages. Related technologies can refer to US Patent No. 6,143,981, 6,399,415, 6,424,024 and other cases.

The above-mentioned various thin and light semiconductor packages can be applied in portable electronic products. For example, the "Sensing Semiconductor Device and Its Manufacturing Method" of Taiwan Patent No. I242820 discloses the use of a TFGBA structure to integrate a control chip and a The sensing chip constitutes a (compact camera module, CCM) package structure.

However, in the above-mentioned various semiconductor packages or the applied CCM package structure, the carrier (such as the substrate or the lead frame) of the semiconductor package or the package structure can only provide electrical contacts electrically connected to the outside below, It is impossible to provide additional electrical contacts on the side of the package or the package structure, or on the upper surface (encapsulation gel part), which will not only fail to provide good electrical functions for electronic products, but will also limit the use of electronic products, such as the inability to carry out packaging. Stacks may not utilize sockets to electrically connect the package to external devices.

Therefore, how to provide a semiconductor package and its manufacturing method that can provide multiple electrical contacts, avoid problems such as restricting the use of electronic products, and provide electronic products with good electrical functions has become an urgent problem to be solved.

Contents of the invention

In order to overcome the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide a semiconductor package and its manufacturing method, which can additionally provide a plurality of electrical contacts, thereby enhancing the electrical function and application range of electronic products.

Another object of the present invention is to provide a semiconductor package and its manufacturing method, which can form electrical contacts on the side of the package.

Another object of the present invention is to provide a semiconductor package and its manufacturing method, which can form electrical contacts on the side and top surface of the package.

Another object of the present invention is to provide a semiconductor package and its manufacturing method, which can be used for direct electrical stacking of semiconductor packages.

Another object of the present invention is to provide a semiconductor package and its manufacturing method, which can be electrically connected to a socket.

In order to achieve the above and other objects, the manufacturing method of the semiconductor package of the present invention includes: providing a chip carrier module sheet with a plurality of chip carriers, each of which is provided with a plurality of electrical connection points; Conductive parts are arranged on the chip corresponding to each chip carrier, and the conductive parts are electrically connected to the electrical connection points of adjacent chip carriers, and the semiconductor chips are connected and electrically connected to each chip carrier; packaging and molding operations are performed. An encapsulant encapsulating the semiconductor chip and the conductive elements is formed on the chip carrier module sheet; and cutting along the encapsulant and the conductive elements between the chip carriers separates the conductive elements disposed on the adjacent chip carriers, and makes the Part of the surface of the conductive member exposes the encapsulant, thereby separating each of the chip carriers.

The upper surface of the conductive member can also directly expose the encapsulating gel after packaging and molding, or the encapsulating gel can be thinned to expose the upper surface of the conductive member, and then the encapsulating gel and the conductive member are cut to make the conductive member side The encapsulation compound is exposed on the surface, so that the upper surface and the side surface of the conductive member can be used as electrical contacts for electrical connection with the outside.

Through the above manufacturing method, the present invention also provides a semiconductor package, which includes: a chip carrier with a plurality of electrical connection points; at least one semiconductor chip connected and electrically connected to The chip carrier; a plurality of conductive elements connected and electrically connected to the electrical connection point; and an encapsulant formed on the chip carrier, covering the semiconductor chip and the conductive elements, and making at least one side of the conductive elements The packaging colloid is exposed on the surface.

Therefore, the semiconductor package of the present invention and its manufacturing method are to arrange conductive parts between corresponding chip carriers on a chip carrier module sheet with multiple chip carriers, and make the conductive parts electrically connect the electrical properties of adjacent chip carriers. connection points, and connect and electrically connect semiconductor chips on each chip carrier, and then carry out molding operation to form an encapsulant covering the semiconductor chip and conductive parts, and then cut along each chip carrier to separate them The conductive element on the adjacent chip carrier exposes part of the surface of the conductive element to the encapsulant, wherein the upper surface of the conductive element can directly expose the encapsulant after molding, or the encapsulant can be thinned. Exposing the upper surface of the conductive member, and then forming a nickel/gold plating layer on the surface of the conductive member exposing the packaging colloid, providing subsequent electrical connection with the outside world, and then separating each chip carrier, utilizing the conductive material of the packaging colloid exposed The components provide additional electrical contacts for subsequent stacking of the packages, or use sockets to electrically connect the packages to external devices, avoiding problems such as limiting the use of electronic products, and can also provide good electrical power for electronic products sexual function.

Description of drawings

1A to 1H are schematic diagrams of Embodiment 1 of a semiconductor package and its manufacturing method of the present invention;

2A to 2E are schematic diagrams of Embodiment 2 of the semiconductor package and its manufacturing method of the present invention;

Fig. 2B' is a schematic diagram of removing part of the encapsulation colloid by grinding;

Fig. 3 is a schematic diagram of the substrate module used in the semiconductor package of the present invention and Embodiment 3 of its manufacturing method;

4A to 4E are schematic diagrams of Embodiment 4 of the semiconductor package and its manufacturing method of the present invention;

5A to 5C are schematic views of the application of the semiconductor package of the present invention.

Detailed ways

Example 1

1A to 1H are schematic diagrams of Embodiment 1 of the semiconductor package and its manufacturing method of the present invention.

As shown in Figure 1A, at first, provide a chip carrier module sheet with a plurality of chip carriers, each chip carrier is provided with a plurality of electrical connection points, refer to Figure 1B at the same time, it is the chip carrier module sheet corresponding to Figure 1A The cross-sectional schematic diagram, in this embodiment, the chip carrier module is a substrate module 100, each of the chip carriers is a thin ball grid array (TFBGA) or land grid array (LGA) substrate 10, each of the substrate 10 Divided by a plurality of transverse and vertical cutting lines (as shown by dotted lines), at the same time at the transverse and vertical cutting lines, electroplating bus lines 11 are formed on the upper and lower surfaces of the corresponding substrate module sheet 100, so that the electroplating bus lines 11 The ring is arranged between the upper surface and the lower surface of the substrate 10, and the electroplating bus 11 is a circuit structure extending and electrically connected to the surface of the substrate 10, wherein, on each upper surface of the substrate 10, there are a plurality of An electrical connection pad (pad) 101 and a second electrical connection pad 102, and an electrical connection point such as a third electrical connection pad 103 are provided on the lower surface of the substrate 10, wherein the first electrical connection pad 101 It can be electrically connected to the third electrical connection pad 103 through a conductive via (via) 104, and the first, second and third electrical connection pads 101, 102, 103 can be electrically connected to the third electrical connection pad through a conductive line. Plating bus11. The third electrical connection pad 103 corresponds to a thin ball grid array (TFBGA) or a land grid array (LGA) substrate is a solder ball pad (ball pad) or an electrical connection terminal (terminal), and the first electrical connection pad 101 can be, for example, a welding finger (bonding finger), and the second electrical connection pad can be, for example, a contact pad 102, but it is not limited thereto. For example, the first electrical connection pad 101 can be a flip chip welding pad (bumppad )wait.

As shown in FIG. 1C , on the substrate module sheet 100, conductive elements 12 are arranged between corresponding substrates 10, and the conductive elements 12 are electrically connected to the second electrical connection pads 102 of adjacent substrates 10, and Each of the substrates 10 is placed and electrically connected to a semiconductor chip 13; please refer to FIG. 1D, which is a schematic cross-sectional view corresponding to FIG. The conductive material is electrically connected to the second electrical connection pad 102 of the adjacent substrate 10, or the conductive member 12 can directly use solder materials such as solder balls. In addition, the semiconductor chip 13 is electrically connected to the substrate by wire bonding. The first electrical connection pad 101 of the chip 10 . Of course, the flip-chip method can also be used to electrically connect the semiconductor chip to the substrate, and the connection operation of the conductive member can be carried out before and after the crystal placement step in conjunction with the crystal placement method.

As shown in FIG. 1E , an encapsulant 14 covering the semiconductor chip 13 and the conductive element 12 is formed on the substrate module 100 .

As shown in FIG. 1F , cut the encapsulant 14 and the conductive member 12 along each of the substrates 10, separate the conductive members 12 arranged on the adjacent substrates 10, and expose the encapsulant 14 on the side surface of the conductive member 12. , wherein the cutting depth at least makes the conductive member 12 and the electroplating bus 11 still maintain an electrical connection relationship, so that in the subsequent electroplating process, nickel/gold is deposited on the conductive member 12 exposing the encapsulant through the electroplating bus 11 .

As shown in FIG. 1G, after cutting and separating the conductive elements 12 on each of the substrates 10, the remaining conductive elements 12 on each of the substrates 10 can still pass through the second electrical connection pad 102 and the conductive through hole 104. It is electrically connected to the electroplating bus 11 , so a metal layer 15 such as nickel/gold can be formed on the side surface of the conductive member 12 exposing the encapsulant 14 by electroplating.

As shown in FIG. 1H , a dicing operation is then performed to separate each of the substrates 10 to form a semiconductor package that can provide multiple additional electrical contacts on the side of the encapsulant.

Therefore, through the above manufacturing method, the present invention provides a semiconductor package, which includes: a chip carrier such as a substrate 10, on which a plurality of first, second and third electrodes are arranged. The electrical connection points of the connection pads 101, 102, 103; at least one semiconductor chip 13 is electrically connected to the substrate 10 by wire bonding or flip-chip; a plurality of conductive members 12 are connected and electrically connected to The electrical connection point such as the second electrical connection pad 102; and an encapsulant 14, formed on the substrate 10, used to cover the semiconductor chip 13 and the conductive member 12, and at least make the conductive member 12 side The packaging colloid 14 is exposed on the surface.

Example 2

2A to 2E are schematic diagrams of Embodiment 2 of the semiconductor package and its manufacturing method of the present invention. This embodiment is substantially the same as the above embodiment, so the same components will not be described again.

As shown in FIG. 2A , first provide a substrate module sheet 200 with a plurality of substrates 20, each of the substrates 20 is provided with an electroplating bus 21 between the upper and lower surfaces, and the electroplating bus 21 is extended and electrically connected to the substrate. The surface circuit structure of the sheet 20, wherein a plurality of electrical connection points such as first electrical connection pads 201 and second electrical connection pads 202 are provided on the upper surface of each of the substrates 20, and on the upper surface of the substrate 20 The lower surface is provided with a third electrical connection pad 203, the first electrical connection pad 201 can be electrically connected to the third electrical connection pad 203 through a conductive via (via) 204, and the first, second and The third electrical connection pads 201 , 202 , 203 can be electrically connected to the electroplating bus 21 through conductive lines.

Next, on the substrate module sheet 200, conductive members 22 are arranged between corresponding substrates 20, and the conductive members 22 are electrically connected to the second electrical connection pads 202 of adjacent substrates 20, and each of the substrates The semiconductor chip 23 is placed on and electrically connected to the substrate 20, and the semiconductor chip 23 can be electrically connected to the substrate by bonding wires.

As shown in FIGS. 2B and 2C, the encapsulation and molding operation is performed to form an encapsulation compound 24 covering the semiconductor chip 23 and the conductive member 22 on the substrate module sheet 200, wherein the height of the conductive member 22 is greater than that of the semiconductor chip 23. And the height of the welding wire on it, when performing the package molding operation, make the conductive member 22 abut against the top of the mold cavity of the packaging mold (not marked), after the package molding operation is completed, directly make the upper part of the conductive member 22 The surface exposes the encapsulant 24; as shown in FIG. 2B', the conductive member 22 is not against the top of the mold cavity of the encapsulation mold, so that the encapsulant 24 first covers the conductive member 22, and then the encapsulant 24 is processed as follows The grinding and thinning operation makes the upper surface of the encapsulant 24 flush with the upper surface of the conductive element 22 , so that the upper surface of the conductive element 22 exposes the encapsulant 24 . Simultaneously cut along each of the substrates 20, cut the encapsulant 24 and the conductive member 22, separate the conductive member 22 arranged on the adjacent substrate 20, and expose the encapsulant 24 on the side surface of the conductive member 22, wherein The cutting depth at least keeps the conductive member 22 electrically connected to the electroplating bus 21 . In the subsequent electroplating process, nickel/gold is deposited on the conductive member 22 exposing the encapsulant through the electroplating bus 21 .

As shown in FIG. 2D , a metal layer 25 such as nickel/gold is formed on the side surface and the upper surface of the conductive member 22 exposing the encapsulant 24 through the electroplating bus 21 by electroplating.

As shown in FIG. 2E , a dicing operation is then performed to separate each of the substrates 20 to form a semiconductor package that can provide multiple additional electrical contacts on the side and top surfaces of the encapsulant.

Example 3

FIG. 3 is a schematic diagram of a substrate module used in Embodiment 3 of the semiconductor package and its manufacturing method of the present invention.

As shown in the figure, this embodiment is substantially the same as the above-mentioned embodiment, the main difference is that the substrate module sheet 300 has a plurality of substrates 30, and the upper and lower surfaces of each substrate 30 are provided with an electroplating bus 31, and The upper surface of each of the substrates 30 is provided with a plurality of electrical connection points such as first electrical connection pads 301 and second electrical connection pads 302, wherein the second electrical connection pads 302 between the adjacent substrates 30 connected together, and the first and second electrical connection pads 301 , 302 are electrically connected to the electroplating bus 31 .

Subsequent methods such as the above-mentioned embodiments can be used to connect and electrically connect the conductive elements to the second electrical connection pads between adjacent substrates, and carry out chip placement, formation of encapsulant covering the chip and the conductive elements, and cutting and separation. The encapsulation compound and conductive parts between the substrates, the electroplating metal layer on the conductive parts exposing the encapsulation colloid, and the separation of the substrates form a semiconductor package that can provide multiple electrical contacts exposed to the encapsulation colloid.

Example 4

4A to 4E are schematic diagrams of Embodiment 4 of the semiconductor package and its manufacturing method of the present invention. The semiconductor package and the manufacturing method of this embodiment are substantially the same as those of the above embodiments, the main difference is that the lead frame is used as the chip carrier in this embodiment.

As shown in FIG. 4A , at first, a lead frame module sheet 400 with a plurality of lead frames 40 is provided, each of which has a chip holder 401 and a plurality of electrical components such as pins 402 surrounding the chip holder 401. The connection point, wherein the lead frame 40 can be, for example, a QFN lead frame, and each lead frame 40 is connected with a connecting bus 41 .

As shown in FIG. 4B, a conductive member 42 is arranged between the pins 402 corresponding to adjacent lead frames 40 on the lead frame module, and the conductive member 42 is electrically connected to the pins 402 of adjacent lead frames 40, and the A semiconductor chip 43 is mounted on the chip holder 401 of each lead frame 40 , and the semiconductor chip 43 is electrically connected to the pin 402 through a plurality of bonding wires. Next, a layer covering the semiconductor chip 43 and the conductive element 42 can be formed on the lead frame module, and the encapsulant 44 is exposed on the upper surface of the conductive element 42 .

As shown in FIG. 4C, the encapsulant 44 and the conductive member 42 on the adjacent lead frame 40 are cut and separated, so that the side surface of the conductive member 42 exposes the encapsulant 44; wherein, when cutting the encapsulant 44 and the conductive member 42, The cutting depth at least keeps the conductive member 42 and the connecting bus 41 still electrically connected.

As shown in FIG. 4D , through the connection bus 41 connecting the pins 402 of the lead frame 40 , a metal layer 45 such as nickel/gold is formed on the side surface and the upper surface of the conductive member 42 exposing the encapsulant 44 by electroplating.

As shown in FIG. 4E , dicing is then performed to separate the lead frames 40 to form a semiconductor package that can provide multiple additional electrical contacts on the side surface and the upper surface of the encapsulant.

5A to 5C are schematic diagrams of the application of the semiconductor package of the present invention; as shown in FIG. 5A, the semiconductor package 5a of the present invention can use the surface of the conductive member 52 exposed from the packaging compound 54 as an electrical contact to contact with the socket (socket) Terminal 56 is electrically connected to provide a CCM package structure that can be loaded on the socket; as shown in Figure 5B and Figure 5C, the semiconductor packages 5b and 5c of the present invention can also use the surface of the conductive member 52 that exposes the packaging compound 54 as an electrical contact , on which a second semiconductor package 57, 58 is electrically stacked, wherein the second semiconductor package 57, 58 may be a ball grid array semiconductor package (as shown in FIG. 5B ) or a lead frame semiconductor package (as shown in FIG. 5C).

To sum up, the semiconductor package of the present invention and its manufacturing method are to arrange conductive parts between corresponding chip carriers on the chip carrier module sheet with multiple chip carriers, and make the conductive parts electrically connect adjacent chip carriers. electrical connection points, and place and electrically connect semiconductor chips on each of the chip carriers, and then carry out molding operations to form an encapsulation compound covering the semiconductor chips and conductive parts, and then cut along each of the chip carriers, Separating the conductive element arranged on the adjacent chip carrier, so that part of the surface of the conductive element exposes the encapsulation compound, wherein, the upper surface of the conductive element can directly expose the encapsulation compound after molding, or the encapsulation compound can be thinned operation, exposing the upper surface of the conductive member, and then forming a nickel/gold plating layer on the surface of the conductive member exposing the packaging colloid, providing subsequent electrical connection with the outside world, and then separating the chip carriers, using the exposed package The conductive parts of the colloid provide additional electrical contacts for subsequent stacking of packages, or use sockets (sockets) to electrically connect the packages to external devices, avoiding problems such as limiting the use of electronic products, and at the same time enabling electronic The product has good electrical function.

Claims (21)

1. A method for making a semiconductor package, characterized in that the method for making the semiconductor package comprises: Provide a chip carrier module with a plurality of chip carriers, each of the chip carriers is provided with a plurality of electrical connection points; On the chip carrier module sheet, a conductive member is arranged between corresponding chip carriers, and the conductive member is electrically connected to an electrical connection point of an adjacent chip carrier, and a semiconductor chip is connected and electrically connected to each chip carrier; Carrying out encapsulation and molding operations to form an encapsulant encapsulating the semiconductor chip and conductive parts on the chip carrier module; and cutting along the encapsulant and the conductive elements between the chip carriers, separating the conductive elements disposed on the adjacent chip carriers, and exposing part of the surface of the conductive elements to the encapsulant, thereby separating the chip carriers. 2. The method for manufacturing a semiconductor package as claimed in claim 1, further comprising: making the conductive member abut against the top of the mold cavity of the packaging mold during packaging and molding operations, After the encapsulation and molding operation is completed, the encapsulation compound is directly exposed on the upper surface of the conductive element. 3. The method for manufacturing a semiconductor package as claimed in claim 1, further comprising making the encapsulant cover the conductive member first, and then thinning the encapsulant to expose the conductive member. the upper surface of the piece. 4 . The method for manufacturing a semiconductor package as claimed in claim 1 , 2 or 3 , further comprising forming a metal layer on the surface of the conductive member exposing the encapsulant. 4 . 5. The method for making a semiconductor package as claimed in claim 1, wherein the chip carrier module is a substrate module, and the chip carrier is a thin ball grid array or planar grid array substrate, each of the substrates The sheet is divided by a plurality of transverse and vertical cutting lines. At the same time, electroplating bus lines are formed on the upper and lower surfaces of each substrate corresponding to the transverse and vertical cutting lines, so that the electroplating bus ring is arranged between the upper and lower surfaces of the substrate. , and the electroplating bus is extended and electrically connected to the surface circuit structure of the substrate. 6. The method of manufacturing a semiconductor package as claimed in claim 5, wherein a plurality of first electrical connection pads and second electrical connection pads are provided on the upper surface of the substrate, and a second electrical connection pad is provided on the lower surface of the substrate. Three electrical connection pads, the first electrical connection pad can be electrically connected to the third electrical connection pad through a conductive through hole, and the first, second and third electrical connection pads are electrically connected to the electroplating bus. 7. The method of manufacturing a semiconductor package as claimed in claim 6, wherein the conductive member is a second electrical connection pad electrically connected to an adjacent substrate, and the semiconductor chip is electrically connected to the second electrical connection pad. The first electrical connection pad of the substrate. 8. The method for manufacturing a semiconductor package as claimed in claim 6, wherein the second electrical connection pads between the adjacent substrates are connected together. 9 . The method for manufacturing a semiconductor package as claimed in claim 5 , wherein the conductive member is electrically connected to an electroplating bus, and a metal layer is formed on the surface of the conductive member exposing the encapsulant by electroplating. 10. The method for manufacturing a semiconductor package as claimed in claim 1, wherein the chip carrier module is a lead frame module, the chip carrier is a lead frame, and each lead frame has a chip holder and a ring set on the lead frame. A plurality of pins around the chip base, and each lead frame is connected with a connection bus. 11 . The method for manufacturing a semiconductor package as claimed in claim 1 , wherein the semiconductor package can use the surface of the conductive member exposed from the encapsulant as an electrical contact to be electrically connected to the contact terminal of the socket. 12. The method of manufacturing a semiconductor package according to claim 2 or 3, wherein the semiconductor package can use the surface of the conductive member exposed to the encapsulant as an electrical contact, and another semiconductor package can be electrically stacked on it pieces. 13. A semiconductor package, characterized in that the semiconductor package comprises: A chip carrier, the chip carrier is provided with a plurality of electrical connection points; at least one semiconductor chip mounted and electrically connected to the chip carrier; a plurality of conductive elements connected and electrically connected to the electrical connection point; and An encapsulation compound is formed on the chip carrier, covers the semiconductor chip and the conductive element, and at least exposes the encapsulation compound on the side surface of the conductive element. 14 . The semiconductor package as claimed in claim 13 , wherein the upper surface of the encapsulant of the semiconductor package is flush with the upper surface of the conductive element, so that the upper surface of the conductive element exposes the encapsulant. 15 . The semiconductor package according to claim 13 or 14 , further comprising a metal layer formed on the surface of the conductive element exposing the encapsulant. 16 . 16. The semiconductor package of claim 13, wherein the chip carrier is a ball grid array or land grid array substrate. 17. The semiconductor package according to claim 16, wherein a plurality of first electrical connection pads and second electrical connection pads are provided on the upper surface of the substrate, and a third electrical connection pad is provided on the lower surface of the substrate. A connection pad, the first electrical connection pad can be electrically connected to the third electrical connection pad through a conductive via. 18. The semiconductor package of claim 17, wherein the conductive member is electrically connected to the second electrical connection pad, and the semiconductor chip is electrically connected to the first electrical connection pad. 19 . The semiconductor package as claimed in claim 13 , wherein the chip carrier is a lead frame, and each lead frame has a chip holder and a plurality of pins surrounding the chip holder. 20 . The semiconductor package as claimed in claim 13 , wherein the semiconductor package can use the surface of the conductive member exposed from the encapsulant as an electrical contact to be electrically connected to the contact terminal of the socket. 21 . 21 . The semiconductor package as claimed in claim 14 , wherein the semiconductor package can use the surface of the conductive member exposed from the encapsulant as an electrical contact, and another semiconductor package can be electrically stacked thereon.

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