CN101242539B - T-DMB system receiver frame synchronization device and method - Google Patents

Abstract

The invention discloses a T-DMB system receiver frame synchronization device and method, the device comprises: adder 1, delayer 1, adder 2, delayer 2, adder 3, a comparator, a symbol Counter and a decision control state machine, wherein: adders 1 and 2, delayers 1 and 2 are used to receive the input signal for differential operation at intervals and then send it to adder 3; adder 3 sends the processing result to the comparator for comparison Afterwards, it is sent to the symbol counter, and the symbol counter sends the count value to the decision control state machine and receives feedback from the decision control state machine. The frame synchronization method counts the sign of the difference between the received signal amplitude and the set threshold, and then determines the null interval. This method is fast and efficient; and because no filter is used, only some control state machines and simple addition units can be used. Realization can reduce the overhead of hardware implementation and effectively overcome the interference of time-domain pulses.

Description

T-DMB system receiver frame synchronization device and method

technical field

The invention relates to a frame synchronization device in a T-DMB standard digital television broadcasting receiving system; the invention also relates to a frame synchronization method of a T-DMB system receiver.

Background technique

T-DMB is a terrestrial digital multimedia broadcasting standard launched by South Korea. This standard is based on the European digital broadcasting standard DAB with some modifications, in order to transmit wireless digital TV programs to handheld devices such as mobile phones, PDAs and portable TVs.

The transmission frame structure of the T-DMB digital TV standard is shown in Figure 1. Each frame is divided into three parts: Synchronization Channel, Fast Information Channel and Main Service Channel. The synchronization channel is located at the beginning of each frame, occupies two symbol lengths, and plays the role of frame synchronization at the receiving end. Among the two symbols of the synchronous channel, the first one is a null symbol, that is, an empty symbol, and its symbol length is specified as Tnull. In four different transmission modes, the Tnull length is also different, as shown in Table 1 (Note: in the table T=1/fs, which is the system sampling period, T=1/2048000 seconds), in this symbol time, the sending end does not send any signal, so the signal received by the receiving end in this symbol time is lower than the normal signal amplitude Many, you can use this feature for synchronization; the second is the PRS (PhaseReference Symbol) symbol, that is, the phase reference symbol, this symbol is used as the phase reference of DQPSK (differential quadrature phase shift keying modulation), and the correlation Properties can also be used for initial synchronization.

Transmission mode I II III IV Tnull length 2656T (1297μs) 664T (324μs) 345T (168μs) 1328T (648μs)

Table 1 Tnull length in four transmission modes

Therefore, in the current T-DMB frame synchronization technology, it can be roughly divided into two types. One is to use PRS symbols for synchronization, that is, to perform sliding correlation on the received signal to find the correlation peak. The advantage of this method is that it uses correlation gain. It can effectively resist signal fading and improve the detection success rate, but the calculation amount is relatively large and consumes a lot of resources. Another relatively simple method is to detect the null symbol, and find the boundary of the null symbol through the set threshold value. This method usually needs to perform low-pass filtering on the signal, and then detect the filtered waveform, but a suitable gate It is difficult to choose the limit value. In different channel environments, different threshold values need to be replaced. On the other hand, if you want to resist the random fading of the signal, you need to increase the order of the low-pass filter, so the storage resources consumed are also Then get bigger.

Contents of the invention

The technical problem to be solved by the present invention is to provide a T-DMB system receiver frame synchronization device, which is stable and reliable, has a high detection success rate and saves resources; for this reason, the present invention will also provide a T-DMB system receiver frame synchronization device synchronous method.

For solving the problems of the technologies described above, the T-DMB system receiver frame synchronization device of the present invention comprises: adder one, delayer one, adder two, delayer two, adder three, a comparator, a symbol counter and A decision control state machine, wherein: the two-way input data I (i) and Q (i) after the tuner and the AD sampling are correspondingly input to the delayer one and the delayer two respectively for two beat delays, The delayed data I(i-2) and Q(i-2) are respectively obtained, and then the two input data and the delayed data are respectively input to the adder 1 and the adder 2 to find the difference, and two channels are obtained Data I'(i) and Q'(i), I'(i)=I(i)-I(i-2), Q'(i)=Q(i)-Q(i-2), and then The absolute value of I'(i) and Q'(i) is obtained; the absolute value of the three pairs of I'(i) and Q'(i) is summed by the adder to obtain the signal amplitude y(i); the comparison The device compares y(i) with the set threshold, and sends the comparison result to the symbol counter. If y(i) is greater than the set threshold, the value of the symbol counter is increased by 1, otherwise, it is decreased by 1; the symbol The counter sends the count value to the decision control state machine and receives feedback from the decision control state machine;

The judgment control state machine judges whether the count value of the symbol counter is less than the last count value, if not less than, then continue to repeat the judgment, if less, then judge whether the situation of less than passes through continuous constant times, if so, take the first A point less than the maximum point of the symbol counter; start the accumulator from the maximum point to accumulate the difference between the signal amplitude y(i) and the set threshold value, when the accumulated value is greater than zero, the exit point condition is reached, and the symbol is found The minimum value point of the counter before reaching the exit point condition; the difference between the maximum value point and the minimum value point of the symbol counter is compared with the standard length, and the transmission mode is discriminated; and the minimum value point of the symbol counter is used as The starting point of the next symbol, that is, the position of the frame header; repeat the above process, if the results obtained twice are consistent, it means that the synchronization is correct, that is, the position of the frame header and the transmission mode are correct, otherwise take the maximum value point and the minimum value point of the symbol counter The result judged once with a large difference is regarded as the correct result.

T-DMB system receiver frame synchronization method of the present invention comprises the steps:

Step 1. For the two-way input data I(i) and Q(i) sampled by the tuner and AD, respectively perform point-by-point difference, that is, delay the input data I(i) and Q(i) by two beats When I(i-2) and Q(i-2) are obtained, then the difference is obtained to obtain the data I'(i) and Q'(i):

I'(i)=I(i)-I(i-2), Q'(i)=Q(i)-Q(i-2);

Step 2, represent the signal amplitude by seeking the absolute value sum of the two-way data I'(i) and Q'(i), i.e. y(i)=|I'(i)|+|Q'(i) |;

Step 3, start the symbol counter; compare step 2 gained y(i) with the threshold value of setting, if y(i) is greater than the threshold value of setting, then the value of symbol counter adds 1, otherwise just subtracts 1;

Step 4. Determine whether the value of the symbol counter obtained in step 3 is smaller than the value of the last symbol counter. If not, continue to repeat the judgment. If it is less, then judge whether the value of the smaller value has passed a continuous constant number of times. If so, take the first A point less than is the maximum point of the symbol counter;

Step 5, start the accumulator from the maximum value point to accumulate the difference between y(i) and the set threshold, when the accumulated value is greater than zero, then reach the exit point condition, and find the symbol counter at the same time when reaching the exit point the minimum value point before the condition;

Step 6, comparing the difference between the maximum value point and the minimum value point of the symbol counter with the standard length to determine the transmission mode; and the minimum value point of the symbol counter is the starting point of the next symbol;

Step 7. Repeat step 1 to step 6. If the result is consistent with the last time, it means that the synchronization is correct. Otherwise, take the frame header position and transmission mode determined by the difference between the maximum value point and the minimum value point of the symbol counter as the result. correct result.

The present invention counts by using the sign of the difference between the received signal amplitude and the set threshold to determine the null interval. The average synchronization time only needs 1.5 frames, and the slowest will not exceed 3 frames; that is to say, in the table In the case of transmission mode 2 shown in 1, it only takes about 24ms*1.5=36ms on average to determine the position of the frame header. In the transmission mode 1 with the longest frame length, it only needs about 96ms*1.5=144ms, and the slowest is no more than 288ms; after field testing, when the signal sensitivity is ≥-100dbm, the detection success rate can reach a reliable 99.99 More than %, it is quite fast and efficient for the boot time of general mobile phones calculated in seconds. On the other hand, in terms of resource consumption and complexity, since no filter is used, most of the storage resources are reduced, and it can be realized with only some control state machines and simple addition units, which greatly reduces the hardware implementation overhead, and can Effectively overcome the interference of time-domain pulses.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

Fig. 1 is a schematic diagram of the transmission frame structure of the existing T-DMB digital television standard;

Fig. 2 is a schematic diagram of symbol count value changes in the method of the present invention;

Fig. 3 is a schematic structural diagram of a frame synchronization device of the present invention;

Fig. 4 is a control flow chart of the decision control state machine in the frame synchronization device of the present invention.

Detailed ways

For the null symbol of the synchronous channel, although the signal at the sending end is 0, there is still relatively large noise after passing through the channel interference; therefore, the simple threshold value setting often fails in the detection, in order to detect the null symbol , the present invention introduces a symbol counter. The basic idea is to find the difference between the signal amplitude M and the fixed threshold T, and count the sign bit S of the difference. In non-null symbols, S should be mostly 1, and in null symbols, S is -1, so the count value of this symbol counter will show a change trend similar to a zigzag (its shape can be referred to in Figure 2), as long as the two turning points of this count value change are determined, the starting point of the null symbol is found and the end point, thus determining the position of the frame header.

The synchronization process that the present invention specifically realizes is as follows:

1. For the two-way input data I(i) and Q(i) sampled by the tuner and AD, perform point-by-point difference respectively, namely: I'(i)=I(i)-I(i-2) and Q'(i)=Q(i)-Q(i-2).

2. Represent the signal amplitude by calculating the absolute value sum of the two-way data I'(i) and Q'(i), that is, y(i)=|I'(i)|+|Q'(i)| .

The difference between points means that the input data I(i) and Q(i) are delayed by two beats to obtain I(i-2 and Q(i-2), and then the difference is obtained to obtain the data I'(i ) and Q'(i) to eliminate the DC component mixed in the signal.

3. Select a threshold th_val, and compare the y(i) value obtained in each step 2 with it. When the selected threshold is in an appropriate range, it can make the data during the Tnull period except Most of the y(i) values of are greater than this threshold. Therefore, a symbol counter is set again. If the accepted y(i) is greater than the threshold th_val, the value of the symbol counter is increased by 1, otherwise, it is decreased by 1. The change trend of the symbol counter is shown in Figure 2.

4. Find the maximum point of the symbol counter, as shown in Figure 2, at a point before entering the Tnull interval, the value of the symbol counter will rise to a maximum point. Here, in order to ensure that this maximum point is not caused by other reasons such as fading, in a period Compare within range. If this point is the largest within a certain range, then it is determined to be the maximum point caused by Tnull.

5. Find the exit point and minimum point. After finding the maximum point, find the exit point, where an accumulator needs to be started, Tnull_acc=∑(y(i)-th_val). This accumulator starts to accumulate from the maximum value point. In the Tnull interval, the value of this accumulator is negative, and when exiting the Tnull interval, the value of y(i) is far greater than th_val, so the accumulator is also Will return to positive value soon. The point at which the accumulator returns to a positive value is the exit point. At the same time, in this interval, the minimum value point of the symbol counter can also be found (while looking for the maximum value, the search for the minimum value is also carried out).

6. Identify the transmission mode and determine the synchronization point. After finding the minimum and maximum points, the difference between them can be obtained, that is, the searched Tnull length, which can be compared with the standard Tnull length (refer to Attached Table 1) to identify the transmission mode. A judgment range Tnull_range is specified here. When the difference between the searched Tnull length and the standard Tnull length is smaller than this judgment range, it is judged that the search is correct. The minimum value point is the end of Tnull and the starting point of the next symbol.

7. Repeat steps 1 to 6 above, find the position of the frame header and determine the transmission mode again as a confirmation. If the results found twice are consistent, it means that the frame header and transmission mode are correct. Otherwise, take the one with the larger Tnull length as the correct result.

As shown in Figure 3, the frame synchronization device of the present invention comprises an adder one, a delayer one, an adder two, a delayer two, an adder three, a comparator, a symbol counter and a decision control state machine, wherein : The input data is the two-way data I(i) and Q(i) after the front-end is sampled by the tuner and AD, and after delayers 1 and 2 respectively, two-beat delays are performed to obtain I(i-2) and Q( i-2), the adder one and the second calculate the difference between the two respectively to obtain the sequence I'(i) and Q'(i), and then the adder three calculates the sum of the absolute values of the two sequences to obtain y(i ) sequence, compare y(i) with the set threshold th_val through a comparator, and count the obtained symbols to obtain the waveform shown in Figure 2. The symbol counter sends the count value to the decision control state machine and receives feedback from the decision control state machine.

The internal process of the decision control state machine is shown in Figure 4. After the synchronization process starts, first clear the symbol counter and let it start counting again, and then judge whether the counter value is less than the previous count value; if it is less than the situation, then Continue to judge, if it is less than n times in a row (n can be configured, and can be set as a constant here), then the first less than point is considered to be the maximum point. At this time, start the accumulator and accumulate (y(i)-th_val). When the accumulated value of the accumulator is greater than zero, it is considered that the exit point condition is reached, and a synchronization process ends, and the minimum and maximum points are calculated. The difference between them determines the transmission mode. Finally, repeat the above process as a confirmation, after two synchronizations, you can exit the control state machine.

Claims (3)

1. a kind of T-DMB system receiver frame synchronization device is characterized in that, comprises: adder one, adder two, adder three, delayer one, delayer two, a comparator, a symbol counter and A decision control state machine, wherein: the two-way input data I (i) and Q (i) after the tuner and the AD sampling are correspondingly input to the delayer one and the delayer two respectively for two beat delays, The delayed data I(i-2) and Q(i-2) are respectively obtained, and then the two input data and the delayed data are respectively input to the adder 1 and the adder 2 to find the difference, and two channels are obtained Data I'(i) and Q'(i), I'(i)=I(i)-I(i-2), Q'(i)=Q(i)-Q(i-2), and then The absolute value of I'(i) and Q'(i) is obtained; the absolute value of the three pairs of I'(i) and Q'(i) is summed by the adder to obtain the signal amplitude y(i); the comparison The device compares y(i) with the set threshold, and sends the compared result to the symbol counter for counting. If y(i) is greater than the set threshold, the value of the symbol counter is increased by 1, otherwise, it is decreased by 1; The symbol counter sends the count value to the decision control state machine and receives feedback from the decision control state machine; The judgment control state machine judges whether the count value of the symbol counter is less than the last count value, if not less than, then continue to repeat the judgment, if less, then judge whether the situation of less than passes through continuous constant times, if so, take the first A point less than the maximum point of the symbol counter; start the accumulator from the maximum point to accumulate the difference between the signal amplitude y(i) and the set threshold value, when the accumulated value is greater than zero, the exit point condition is reached, and the symbol is found The minimum value point of the counter before reaching the exit point condition; the symbol counter has determined the maximum value point and the minimum value point, and the starting point and the end point of the null symbol have just been found, and the position of the frame header has also been determined; the described Compare the difference between the maximum value point and the minimum value point of the symbol counter with the standard length to determine the transmission mode, and use the minimum value point of the symbol counter as the starting point of the next nul1 symbol; repeat the above process, if twice If the obtained results are consistent, it means that the synchronization is correct, that is, the position of the frame header and the transmission mode are correct. Otherwise, the result of the frame header position and transmission mode judged once with a large difference between the maximum value point and the minimum value point of the symbol counter is taken as the correct result. . 2. a T-DMB system receiver frame synchronization method, is characterized in that, comprises the steps: Step 1. For the two-way input data I(i) and Q(i) sampled by the tuner and AD, respectively perform point-by-point difference, that is, delay the input data I(i) and Q(i) by two beats When I(i-2) and Q(i-2) are obtained, then the difference is obtained to obtain the data I'(i) and Q'(i): I'(i)=I(i)-I(i-2), Q'(i)=Q(i)-Q(i-2); Step 2, represent the signal amplitude by seeking the absolute value sum of the two-way data I'(i) and Q'(i), i.e. y(i)=|I'(i)|+|Q'(i) |; Step 3, start the symbol counter; compare step 2 gained y(i) with the threshold value of setting, if y(i) is greater than the threshold value of setting, then the value of symbol counter adds 1, otherwise just subtracts 1; Step 4. Determine whether the value of the symbol counter obtained in step 3 is smaller than the value of the last symbol counter. If not, continue to repeat the judgment. If it is less, then judge whether the value of the smaller value has passed a continuous constant number of times. If so, take the first A point less than is the maximum point of the symbol counter; Step 5, start the accumulator from the maximum value point to accumulate the difference between y(i) and the set threshold, when the accumulated value is greater than zero, then reach the exit point condition, and find the symbol counter at the same time when reaching the exit point The minimum value point before the condition; the symbol counter has determined the maximum value point and the minimum value point, and the start point and the end point of the null symbol have just been found, and the position of the frame header has also been determined; Step 6, comparing the difference between the maximum value point and the minimum value point of the symbol counter with the standard length to determine the transmission mode; and the minimum value point of the symbol counter is the starting point of the next null symbol; Step 7. Repeat steps 1 to 6. If the result is consistent with the last time, it means that the synchronization is correct, that is, the frame header position and transmission mode are correct. Otherwise, the difference between the maximum value point and the minimum value point of the symbol counter is judged once. The result of frame header position and transmission mode is taken as the correct result. 3. T-DMB system receiver frame synchronization method according to claim 2, is characterized in that: in the step 6 when the difference between the difference of symbol counter maximum value point and minimum value point and standard length is in the judgment of regulation If it is within the range, it is determined that the difference between the searched maximum value point and the minimum value point is correct.

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