CN101465647A - Filter of phase-locked loop apparatus and phase-locked loop apparatus - Google Patents

Abstract

The invention discloses a filter in a phase-locked loop device. The present invention utilizes an equivalent capacitor as the first capacitor. Since the capacitance values of the three capacitors forming the equivalent capacitor are much smaller than the expected value C _z , the equivalent capacitor in the present invention takes the expected value compared to the original filter circuit The first capacitance of C _z , the volume is greatly reduced. Moreover, since the capacitance value of the equivalent capacitance is smaller than the expected value C _z , the present invention also adds an additional current in the equivalent capacitance, so that the voltage at both ends of the equivalent capacitance is equal to the expected value C in the original filter circuit The voltage at both ends of the first capacitor of _z is the same, so that U _f (t) can be kept unchanged without adjusting the size of the loop current _ip , so that the output voltage of the second filter capacitor can be reduced under the premise of keeping the output voltage constant. size to miniaturize the filter without requiring loop current regulation. The invention also discloses a phase-locked loop device.

Description

Filter in phase-locked loop device and phase-locked loop device

technical field

The invention relates to a filter circuit, in particular to a filter and a phase-locked loop device in a phase-locked loop (Phase-Locked Loop) device.

Background technique

In integrated circuit (IC, Integrated Circuit) design, the size of electronic devices is a very important consideration. The miniaturization and integration of electronic devices is the development trend of electronic devices. Moreover, with the development of system-on-chip (SOC, System-On-Chip) technology, the frequency of electronic device applications is getting higher and higher, and the required bandwidth is also increasing. The wider, therefore, puts forward higher requirements on the performance of electronic components, such as reducing parasitic inductance, parasitic capacitance, improving self-resonant frequency, strict synchronization between electronic components, etc. Therefore, the phase-locked loop technology used in synchronization and the miniaturization of devices using the phase-locked loop technology have also received more and more attention.

PLL technology is widely used. For example, PLL technology applied in space can realize target tracking, telemetry and remote control; PLL technology applied in the field of digital communication can extract reference carrier for coherent demodulation, Establish bit synchronization and frequency synthesis, etc.

Phase-locked loop technology is a technology that synchronizes the output signal generated by a voltage-controlled oscillator (VCO, Voltage Controlled Oscillator) with an input reference signal in phase and frequency. In the synchronous state, which is commonly referred to as locked, the phase difference between the output signal of the VCO and the input reference signal is 0 or a certain fixed constant. If the phase between the two changes, there is a feedback control mechanism in the phase-locked loop, which adjusts the output signal of the VCO through feedback, so that the phase difference between the output signal and the input reference signal decreases, and finally reaches the locked state, and also It is to lock the output signal of the VCO to the phase of the input reference signal.

FIG. 1 is a schematic structural diagram of an existing phase-locked loop device. Referring to Fig. 1, this device comprises phase detector (PD, Phase Detector), filter and VCO, wherein,

PD is used to compare the phase of the input reference signal U _in (t) and the feedback signal U _feed (t) output by the VCO, and output the output signal U _d (t) corresponding to the phase difference of the two signals;

The filter is used to filter U _d (t), and filter out the high-frequency components and noise in U _d (t), so as to ensure the performance required by the loop, increase the stability of the system, and output the control voltage signal U _f (t);

VCO is used to make the frequency of the output signal U _out (t) approach the frequency of U in (t) according to the U _f (t) output by the loop filter until it is equal to the frequency of _{U in (} t) and enter locked state.

In the above, U _out (t) and U _feed (t) are the same signal.

In practical applications, the phase-locked loop can also include a charge pump (CP, Charge Pump), which is used to receive U _d (t), charge and discharge the filter (filter control), and the loop filter is controlled according to the CP output The signal is charged and discharged and outputs the corresponding U _f (t), controls U _out (t), outputs U _out (t) and U _feed (t), and outputs U _feed (t) to the PD to form feedback, and finally reaches the phase locking. In the locked state, U _in (t) and U _out (t) have the same frequency and phase.

U _feed (t) can also be output to PD after frequency division by a frequency divider, and the angular frequency of U _out (t) can be adjusted.

The filter may also be a loop low-pass filter (LPF, Lowpass Filter).

Fig. 2 is a structural schematic diagram of a filter in a conventional PLL device. Referring to FIG. 2 , it includes a first capacitor with an expected value C _z , a second capacitor with an expected value C _p , and a resistor with an expected value R.

Wherein, the expected value described herein refers to: based on the circuit structure shown in FIG. 2 , the capacitance value or resistance value that produces the filtering effect required by the application environment where the circuit is located.

After the first capacitor is connected in series with the resistor, it is connected in parallel with the second capacitor.

The end of the resistor connected to the second capacitor is the input end of the loop current, and the end connected to the first capacitor and the second capacitor is the output end of the loop current. The loop current is provided by CP, and its value is i _p .

U _f (t) is output through both ends of the first filter capacitor.

Among them, the main function of the first capacitor is to combine the resistance to form a low-pass filter, and at the same time provide a zero point in the frequency domain required for the stability of the entire PLL system; the main function of the second capacitor is to filter out relatively high The noise component of the frequency; usually, the expected value C _z of the first capacitor is dozens of times of the expected value C _p of the second capacitor.

The current value of the loop current is i _p , then from Figure 2, it can be concluded that:

${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; sC</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}}{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Wherein, U _f (s) is the voltage value of U _f (t) in the s domain.

Since the expected value C _z of the first capacitance is dozens of times of the expected value C _p of the second capacitance, the expected value C _p of the second capacitance in formula (2-1) can be ignored, thus:

${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; Z</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Wherein, U _f (s) is the voltage value of U _f (t) in the s domain.

In existing filter designs, the expected value C _z of the first capacitor is relatively large, and correspondingly, its size is also relatively large, which needs to occupy a certain space, which is not conducive to the miniaturization of the filter. However, if the size of the first capacitor is to be reduced, its capacitance value will also decrease accordingly. It can also be seen from formula (2-2) that the capacitance value of the first capacitor is smaller than the expected value C _z , which will inevitably lead to U _f ( t), thus affecting the VCO output signal U _out (t).

Therefore, if the capacitance value of the first capacitor is reduced, in order to keep U _f (t) unchanged, it is necessary to adjust the magnitude of the loop current i _p to change a corresponding value. However, adjusting the loop current will affect other devices in the phase-locked loop device, so it is difficult to achieve reasonable adjustment in practical applications.

It can be seen that in the prior art, it is difficult to ensure the normal operation of the phase-locked loop device by adjusting the loop current, so it is difficult to reduce the size of the second filter capacitor to realize the filter on the premise that the output voltage remains unchanged. miniaturization.

Contents of the invention

An embodiment of the present invention provides a filter in a phase-locked loop device, which can reduce the size of the second filter capacitor to realize the miniaturization of the filter without changing the loop current Make adjustments.

The embodiment of the present invention also provides a phase-locked loop device, which can reduce the size of the second filter capacitor to realize the miniaturization of the filter under the premise of keeping the output voltage constant, and does not need to adjust the loop current.

In order to achieve the above purpose, the technical solutions of the embodiments of the present invention are specifically implemented as follows:

A filter in a phase-locked loop device, the filter comprising: a first capacitor, a second capacitor and a resistor, wherein the first capacitor is connected in parallel with the second capacitor after being connected in series with the resistor;

The first capacitor is composed of a third capacitor, a fourth capacitor, and a fifth capacitor connected in series; wherein, the capacitance values of the third capacitor, the fourth capacitor, and the fifth capacitor are all much smaller than the capacitance values of the fifth capacitor. The expected value C _z of the first capacitor;

The fifth capacitor is connected in parallel with the second capacitor after being connected in series with the resistor;

The end of the resistor connected to the second capacitor is the input end of the loop current, and the end of the resistor connected to the fifth capacitor is the output end of the loop current;

An additional current is input from the end of the third capacitor connected to the fourth capacitor and output from the end of the fifth capacitor connected to the third capacitor, the additional current is used to ensure that the fifth capacitor The terminal voltage is close to the voltage generated by the first capacitor whose capacitance value is expected value _Cz .

The capacitance value of the third capacitor is

The capacitance value of the fourth capacitor is

The capacitance value of the fifth capacitor is

Wherein, n is a positive integer far greater than 1; the magnitude of the additional current is the same as that of the loop current.

The additional current comes from a charge pump.

A phase-locked loop device comprising: a phase detector, a filter and a voltage-controlled oscillator, wherein the filter comprises a first capacitor, a second capacitor and a resistor, and the first capacitor is connected in series with the resistor connected in parallel with the second capacitor;

The first capacitor is composed of a third capacitor, a fourth capacitor, and a fifth capacitor connected in series; wherein, the capacitance values of the third capacitor, the fourth capacitor, and the fifth capacitor are all much smaller than the capacitance values of the fifth capacitor. The expected value C _z of the first capacitor;

The fifth capacitor is connected in parallel with the second capacitor after being connected in series with the resistor;

The end of the resistor connected to the second capacitor is the input end of the loop current, and the end of the resistor connected to the fifth capacitor is the output end of the loop current;

An additional current is input from the end of the third capacitor connected to the fourth capacitor and output from the end of the fifth capacitor connected to the third capacitor, the additional current is used to ensure that the fifth capacitor The terminal voltage is close to the voltage generated by the first capacitor whose capacitance value is expected value _Cz .

The capacitance value of the third capacitor is

The capacitance value of the fourth capacitor is

The capacitance value of the fifth capacitor is

Wherein, n is a positive integer far greater than 1; the magnitude of the additional current is the same as that of the loop current.

The device includes a first charge pump for outputting the loop current.

The first charge pump is located in the phase detector.

The device also includes a second charge pump for outputting the additional current.

The device further includes a frequency divider, which is used to divide the frequency of the signal output by the voltage-controlled oscillator, and output the frequency-divided signal to the phase detector.

It can be seen from the above technical solution that the present invention utilizes an equivalent capacitor as the first capacitor. Since the capacitance values of the three capacitors constituting the equivalent capacitor are much smaller than the expected value C _z , the equivalent capacitor in the present invention is compared to the original filter The volume of the first capacitor whose value is the expected value C _z in the circuit is greatly reduced. Moreover, since the capacitance value of the equivalent capacitance is smaller than the expected value C _z , the present invention also adds an additional current in the equivalent capacitance, so that the voltage at both ends of the equivalent capacitance approaches the value in the original filter circuit The voltage across the first capacitor of the expected value C _z , so that U _f (t) can be kept unchanged without adjusting the size of the loop current i _p , so that the second filter capacitor can be reduced under the premise of keeping the output voltage constant The size of the filter can be miniaturized without requiring regulation of the loop current.

Description of drawings

Fig. 1 is the structural representation of existing PLL device;

Fig. 2 is the structural representation of the filter in the existing PLL device;

FIG. 3 is a schematic structural diagram of a filter in a phase-locked loop device according to an embodiment of the present invention;

FIG. 4 is a schematic structural view of an equivalent capacitance in a filter according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a preferred embodiment of a PLL device based on FIG. 3 .

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples.

The present invention utilizes three capacitors whose capacitance values are much smaller than the expected value C _z to form an equivalent capacitor, and uses the equivalent capacitor as the first capacitor in the existing filter circuit. Since the capacitance values of the three capacitors constituting the equivalent capacitor are much smaller than the expected value C _z , the volume of the equivalent capacitor is greatly reduced compared with the first capacitor whose value is the expected value C _z in the original filter circuit.

Moreover, since the capacitance value of the equivalent capacitor is smaller than the expected value C _z , the present invention also adds an additional current in the equivalent capacitor, so that the voltage at both ends of the equivalent capacitor is infinitely close to the value in the original filter circuit The voltage across the first capacitor is the expected value C _z , so that U _f (t) can be kept unchanged without adjusting the size of the loop current i _p , so that the second filter can be reduced under the premise of keeping the output voltage constant. Capacitors are sized to miniaturize the filter without requiring loop current regulation.

Of course, the optimal state of approach is: the voltage across the equivalent capacitor is the same as the voltage across the first capacitor whose value is the expected value C _z in the original filter circuit.

In order to achieve the above object, an embodiment of the present invention provides a filter in a phase locked loop device.

FIG. 3 is a schematic structural diagram of a filter in a phase-locked loop device according to an embodiment of the present invention. Referring to FIG. 3 , the filter circuit includes a first capacitor, a second capacitor, and a resistor. The first capacitor is connected in series with the resistor and then connected in parallel with the second capacitor.

Wherein, the capacitance value of the second capacitor is still C _p , the resistance value of the resistor is still R, and the loop current in the filter circuit is still i _p .

。The first capacitor in the present invention is formed by ring-connected series connection of the third capacitor, the fourth capacitor and the fifth capacitor, and its equivalent capacitance value is

.

Wherein, the capacitance values of the third capacitor, the fourth capacitor and the fifth capacitor are all much smaller than the expected value C _z of the first capacitor.

The fifth capacitor is connected in parallel with the second capacitor after being connected in series with the resistor.

After the third capacitor is connected in series with the fourth capacitor, it is connected in parallel with the fifth capacitor.

The end of the resistor connected to the second capacitor is the input end of the loop current, and the end of the resistor connected to the fifth capacitor is the output end of the loop current. The loop current can be provided by CP, and its current value is still i _p .

An additional current is input from the end connected to the third capacitor and the fourth capacitor, and output from the end connected to the fifth capacitor and the third capacitor. The additional current is used to ensure the voltage across the equivalent capacitor, that is, the voltage U across the fifth capacitor. _z ′ approaches infinitely to the voltage U _z across the first capacitor whose expected value is C _z in the existing filter circuit.

第四电容的电容值为

第五电容的电容值为较佳地，取n为大于10的整数，则附加电流的大小可以为环路电流的电流取值i_p。Among them, it is assumed that the capacitance value of the third capacitor is

The capacitance value of the fourth capacitor is

The capacitance value of the fifth capacitor is Preferably, if n is an integer greater than 10, the magnitude of the additional current can be the value _ip of the loop current.

Both ends of the second capacitor still output U _f (t).

In the above filter circuit, the additional current can ensure that the voltage U _z across the equivalent capacitor is the same as the voltage U _z across the first capacitor whose expected value is C _z in the existing filter circuit, and the voltage across the resistor is also the same as that of the existing filter circuit The voltage at both ends of the resistor in is the same, therefore, when the magnitude of the loop current is the same as the current value i _p , the output voltage U _f (t) at both ends of the second capacitor can be guaranteed to remain unchanged.

Next, why the additional current can ensure that the voltage U _z across the equivalent capacitor is the same as the voltage U _z across the first capacitor whose expected value is C _z in the existing filter circuit, so as to ensure the output voltage U _f across the second capacitor (t) remains unchanged for detailed derivation.

FIG. 4 is a schematic structural diagram of an equivalent capacitor in a filter according to an embodiment of the present invention. Referring to FIG. 4, the series-parallel relationship among the third capacitor, the fourth capacitor, and the fifth capacitor constituting the equivalent capacitor can be seen in FIG. 4: the fourth capacitor is connected in series with the fifth capacitor and then connected in parallel with the third capacitor.

第四电容的电容值为

第五电容的电容值为可以得出：Suppose the capacitance value of the third capacitor is

The capacitance value of the fourth capacitor is

The capacitance value of the fifth capacitor is It can be concluded that:

$\mathrm{<span\; class="notranslate">\; Uz</span>}<span\; class="notranslate">\; \&prime;</span><span\; class="notranslate">\; =</span>\frac{\frac{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}}{\frac{{\mathrm{<span\; class="notranslate">\; no</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; sC</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Wherein, U ₃ is the voltage across the third capacitor.

The equivalent capacitance value _C45 of the fourth capacitor and the fifth capacitor is:

${\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 45</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

The voltage _U3 across the third capacitor is:

${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 45</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Substituting formula (4-3) into formula (4-1), we can get:

${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}<span\; class="notranslate">\; \&prime;</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

If in formula (4-4), i _p '= _ip , n>>1, then formula (4-4) can be simplified as:

${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}<span\; class="notranslate">\; \&prime;</span><span\; class="notranslate">\; \&ap;</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

It can be seen that U _z ′ obtained by formula (4-5) is basically the same as U _z in the existing filter circuit when n>>1 is satisfied, and it can be completely equal to U _z in the existing filter circuit in the best state. same.

In this way, since the expected value of the second capacitance C _p is extremely small, the influence of the second capacitance on U _z ' is negligible, therefore, U _f (t) in Fig. 3 can be obtained as:

${\mathrm{<span\; class="notranslate">\; u</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&ap;</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; \&times;</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; z</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

Wherein, U _f (s) is the voltage value of U _f (t) in the s domain.

It can be seen that U _f (s) obtained by formula (4-6) is almost the same as U _f (s) obtained by formula (2-2) in the existing filter circuit when n>>1 is satisfied, and the best In the state, it can be exactly the same as U _f (s) obtained by formula (2-2) in the existing filter circuit.

In practical applications, as long as the capacitance values of the third capacitor, the fourth capacitor, and the fifth capacitor constituting the equivalent capacitor are small, and the additional current can make the voltage U _z ' at both ends of the equivalent capacitor equal to the expected value in the existing filter circuit The voltage U _z across the first capacitor of C _z is the same, then the capacitance values of the third capacitor, the fourth capacitor, the fifth capacitor, and the magnitude of the additional current can also be set to other values.

FIG. 5 is a schematic structural diagram of a preferred embodiment of a PLL device based on FIG. 3 . Referring to FIG. 5, the phase-locked loop device includes: a PD, a filter, and a VCO, wherein,

PD is used for phase comparison between U _in (t) and the frequency divider output signal U _feed (t), and outputs a PD output signal U _d (t) proportional to the signal phase difference to the filter.

The filter includes a first capacitor, a second capacitor, and a resistor, and the first capacitor and the resistor are connected in parallel to the second capacitor after being connected in series.

Wherein, the capacitance value of the second capacitor is still C _p , the resistance value of the resistor is still R, and the loop current in the filter circuit is still i _p .

The first capacitor in the present invention is formed by ring-connected series connection of the third capacitor, the fourth capacitor and the fifth capacitor, and its equivalent capacitance value is

Wherein, the capacitance values of the third capacitor, the fourth capacitor and the fifth capacitor are all much smaller than the expected value C _z of the first capacitor.

The fifth capacitor is connected in parallel with the second capacitor after being connected in series with the resistor.

After the third capacitor is connected in series with the fourth capacitor, it is connected in parallel with the fifth capacitor.

The end of the resistor connected to the second capacitor is the input end of the loop current, and the end of the resistor connected to the fifth capacitor is the output end of the loop current. The loop current can be provided by the CP of the phase-locked loop device, and its current value is still for i _p .

An additional current is input from the end connected to the third capacitor and the fourth capacitor, and output from the end connected to the fifth capacitor and the third capacitor. The additional current is used to ensure the voltage across the equivalent capacitor, that is, the voltage U across the fifth capacitor. _z ′ approaches infinitely to the voltage U _z across the first capacitor whose expected value is C _z in the existing filter circuit.

Of course, the optimal state of approach is: the voltage across the equivalent capacitor is the same as the voltage across the first capacitor whose value is the expected value C _z in the original filter circuit.

第四电容的电容值为

第五电容的电容值为

较佳地，取n为大于10的整数，则附加电流的大小可以为环路电流的电流取值i_p。Among them, it is assumed that the capacitance value of the third capacitor is

The capacitance value of the fourth capacitor is

The capacitance value of the fifth capacitor is

Preferably, if n is an integer greater than 10, the magnitude of the additional current can be the value _ip of the loop current.

Both ends of the second capacitor still output U _f (t).

In practical applications, the phase-locked loop device shown in Figure 5 also includes:

The first CP is used to provide the loop current i _p ;

。2nd CP for supplying additional current

.

Wherein, in FIG. 5, the first CP is an independent device. However, in practical applications, the first CP may be located in the PD, that is, the present invention can be realized by using an existing PD.

In the PLL device as shown in FIG. 5 , a frequency divider is further included, which is used to divide the frequency of the signal U _f (t) output by the VCO, and output the frequency-divided signal to the PD as a feedback.

In practical applications, a frequency divider may also be provided in the input reference signal circuit to divide the frequency of the input reference signal.

Certainly, the frequency divider provided in the present invention is optional, but not necessary.

The preferred embodiments above are used to further describe the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included within the protection scope of the present invention.

Claims (9)

1. A filter in a phase-locked loop device, comprising: a first capacitor, a second capacitor and a resistor, and the first capacitor is connected in parallel with the second capacitor after being connected in series with the resistor; It is characterized in that, The first capacitor is composed of a third capacitor, a fourth capacitor, and a fifth capacitor connected in series; wherein, the capacitance values of the third capacitor, the fourth capacitor, and the fifth capacitor are all much smaller than the capacitance values of the fifth capacitor. The expected value C _z of the first capacitor; The fifth capacitor is connected in parallel with the second capacitor after being connected in series with the resistor; The end of the resistor connected to the second capacitor is the input end of the loop current, and the end of the resistor connected to the fifth capacitor is the output end of the loop current; An additional current is input from the end of the third capacitor connected to the fourth capacitor and output from the end of the fifth capacitor connected to the third capacitor, the additional current is used to ensure that the fifth capacitor The terminal voltage is close to the voltage generated by the first capacitor whose capacitance value is expected value _Cz . 2. The filter of claim 1, wherein The capacitance value of the third capacitor is

The capacitance value of the fourth capacitor is

The capacitance value of the fifth capacitor is

Wherein, n is a positive integer far greater than 1; the magnitude of the additional current is the same as that of the loop current. 3. The filter of claim 2, wherein the additional current comes from a charge pump. 4. A phase-locked loop device, characterized in that, the phase-locked loop device comprises: a phase detector, a filter and a voltage-controlled oscillator, wherein the filter comprises: a first capacitor, a second capacitor and a resistor, The first capacitor is connected in parallel with the second capacitor after being connected in series with the resistor; It is characterized in that, The first capacitor is composed of a third capacitor, a fourth capacitor, and a fifth capacitor connected in series; wherein, the capacitance values of the third capacitor, the fourth capacitor, and the fifth capacitor are all much smaller than the capacitance values of the fifth capacitor. The expected value C _z of the first capacitor; The fifth capacitor is connected in parallel with the second capacitor after being connected in series with the resistor; The end of the resistor connected to the second capacitor is the input end of the loop current, and the end of the resistor connected to the fifth capacitor is the output end of the loop current; An additional current is input from the end of the third capacitor connected to the fourth capacitor and output from the end of the fifth capacitor connected to the third capacitor, the additional current is used to ensure that the fifth capacitor The terminal voltage is close to the voltage generated by the first capacitor whose capacitance value is expected value _Cz . 5. phase locked loop device as claimed in claim 4, is characterized in that, The capacitance value of the third capacitor is

The capacitance value of the fourth capacitor is

The capacitance value of the fifth capacitor is

Wherein, n is a positive integer far greater than 1; the magnitude of the additional current is the same as that of the loop current. 6. The phase-locked loop device according to claim 4 or 5, characterized in that the device comprises a first charge pump for outputting the loop current. 7. The phase locked loop device according to claim 6, wherein the first charge pump is located in the phase detector. 8. The phase locked loop device according to claim 6, further comprising a second charge pump for outputting the additional current. 9. The phase-locked loop device as claimed in claim 4 or 5, characterized in that, the device further comprises a frequency divider, which is used to receive the signal U _out (t) output by the voltage-controlled oscillator. divide the frequency, and output the divided signal to the phase detector.

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