CN101666830A - Capacitance value measuring circuit and electronic device using same - Google Patents

Abstract

The invention relates to a capacitance value measuring circuit, comprising: the device comprises a capacitive voltage division circuit, an analog-to-digital converter (ADC) and a processing module. The capacitive voltage-dividing circuit includes: a switch circuit, a known capacitor and a capacitor to be measured. The switch circuit is controlled by the first and second clock signals. The conducting state of the switch circuit enables the voltage variation of the first end of the known capacitor to be coupled to the first end of the capacitor to be measured. The analog-digital converter converts the voltage of the first end of the capacitor to be measured into a digital signal. The processing module detects the capacitance value and the variable quantity of the capacitor to be detected according to the digital signal of the analog-digital converter and the parameters of the analog-digital converter. The invention also relates to an electronic device applying the capacitance value measuring circuit, which is used for measuring the capacitance value of the capacitor to be measured.

Description

Capacitance value measuring circuit and electronic device using it

technical field

The invention relates to a capacitance value measuring circuit and an electronic device using the same, which are used for measuring the capacitance value of a capacitor to be measured.

Background technique

Traditionally, mechanical switches are mostly used to realize the user control interface. Since the user needs to directly touch the traditional mechanical switch, the traditional mechanical switch can operate in response to the user's control command, and the traditional mechanical device is easy to be damaged during the user's operation. At present, a touch switch has been developed. The touch switch is, for example, a capacitive switch or the like.

In order to improve the convenience of use, a touch panel (touch panel) or a display touch panel (having both display and touch functions) has been developed. The touch panel or display touch panel can accept user's input, click and other operations. The touch panel or display touch panel can be applied in various electronic devices, such as mobile phones. In this way, the user can directly click on the screen on the touch panel or the display touch panel to perform operations, thereby providing a more convenient and humanized operation mode. There are many types of touch panels or display touch panels, and capacitive touch panels or display touch panels are one of them.

When the user operates the capacitive touch panel, the capacitive display touch panel, or the capacitive switch, the capacitance value of the internal capacitor to be measured will change according to the user's operation. Thereby, the user's operation can be detected. However, how to design a capacitance measurement circuit that can effectively detect the capacitance change of the capacitor to be measured, so as to improve the performance of capacitive touch panels, capacitive display touch panels, or capacitive switches is a direction that is constantly being worked on in this field. one.

Contents of the invention

The invention relates to a capacitance value measuring circuit. Compared with the traditional capacitance value measuring circuit, the capacitance value measuring circuit can more accurately measure the capacitance value and the variation of the capacitance value of the capacitor to be measured.

The invention relates to an electronic device, in which a touch screen and a sensor can share the same analog-to-digital converter (ADC), so as to reduce the circuit area and cost of the electronic device.

The present invention provides a capacitance measurement circuit, comprising: a capacitive voltage divider circuit, which includes: a switch circuit, a first capacitor and a second capacitor, the switch circuit is coupled to the first capacitor and the second capacitor, and the switch circuit is controlled by the first capacitor A clock signal and a second clock signal, the second clock signal is an inversion signal of the first clock signal, and the conduction state of the switch circuit makes the voltage change at the first end of the first capacitor coupled to the first end of the second capacitor An analog-to-digital converter, coupled to the capacitive voltage divider circuit, the analog-to-digital converter converts the voltage at the first end of the second capacitor into a first digital signal; and a processing module, coupled to the analog-to-digital converter, the processing module According to the first digital signal of the analog-to-digital converter and the parameters of the analog-to-digital converter, the capacitance value of the second capacitor and its variation are detected.

In the capacitance measuring circuit of the present invention, in one embodiment, the switch circuit of the capacitive voltage divider circuit includes: a first switch, the first end of which is coupled to the first voltage source, and the second end of which is coupled to To the first end of the second capacitor, the conduction of the first switch is controlled by the first clock signal; the first end of the second switch is coupled to the first voltage source, and the second end is coupled to the first a first terminal of a capacitor, the conduction of the second switch is controlled by the first clock signal; and a third switch, the first terminal of which is coupled to the second voltage source, and the second terminal of which is coupled to the first capacitor The first end of the third switch is controlled by the second clock signal; wherein, the second end of the first capacitor is coupled to the first end of the second capacitor, and the second end of the second capacitor The terminal is coupled to a third voltage source.

In the capacitance measuring circuit of the present invention, in one embodiment, the parameters of the analog-to-digital converter include the resolution and conversion voltage range of the analog-to-digital converter; and the processing module is further based on the voltage value of the first voltage source , the voltage value of the second voltage source and the capacitance value of the first capacitor, the resolution of the analog-to-digital converter, the converted voltage range of the analog-to-digital converter and the first digital signal of the analog-to-digital converter, to The capacitance value of the second capacitor and its variation are detected.

In one embodiment, the capacitance measurement circuit of the present invention further includes a bias circuit coupled to the capacitive voltage divider circuit and the analog-to-digital converter, and the bias circuit is used to apply a bias voltage to the first node , so that the voltage of the first node is related to the bias voltage and the voltage of the first terminal of the second capacitor.

The capacitance measuring circuit of the present invention, in one embodiment, the analog-to-digital converter includes: a switch-sampling-capacitance circuit, an operational amplifier, a comparator, a latch (latch, latch), an inverter, A counter and a switch-capacitor circuit, wherein the switch-sampling-capacitance circuit has a first input terminal and an output terminal coupled to the first terminal of the second capacitor of the capacitive voltage divider circuit, and the switch-sampling-capacitance circuit controlled by the first clock signal and the second clock signal to sample the voltage at the first terminal of the second capacitor of the capacitive voltage divider circuit; the operational amplifier has an output coupled to the switch-sampling capacitor circuit A first input terminal, a second input terminal, a first output terminal and a second output terminal of the terminal; the comparator has a first input terminal coupled to the first output terminal of the operational amplifier, a second output terminal coupled to the operational amplifier The second input end of the terminal, and the output end of the second digital signal; the latch receives the second digital signal output by the comparator, and under the trigger of the first clock signal, the latch converts the second digital signal to output as a third digital signal; an inverter that inverts the third digital signal; a counter that counts the third digital signal to generate a first digital signal; and a switch-capacitor circuit that is coupled to the first digital signal of the operational amplifier. The two input terminals are controlled by the first clock signal, the second clock signal, the third digital signal and the inversion signal of the third digital signal.

The present invention also provides an electronic device, including: a capacitor to be measured, used to output a voltage to be measured; a sensor, used to output a sensing signal; a multiplexer, coupled to the capacitor to be measured and the sensor, to output the voltage to be measured and the sensor. One of the sensing signals; and an analog-to-digital converter coupled to the multiplexer for converting the voltage to be measured or the sensing signal into a digital output signal, the digital output signal representing the capacitance value of the capacitor to be measured and its variation, or Represents the sensing result of the sensor.

In one embodiment, the electronic device of the present invention further includes a touch screen, wherein the capacitance to be measured is located in the touch screen.

In order to make the above-mentioned contents of the present invention more obvious and understandable, the embodiments are specifically listed below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Description of drawings

FIG. 1 shows a schematic circuit diagram of a capacitance measurement circuit according to a first embodiment of the present invention.

FIG. 2 shows the relevant waveform diagram of FIG. 1 .

FIG. 3 shows a schematic circuit diagram of a capacitance measurement circuit according to a second embodiment of the present invention.

FIG. 4 shows the relevant waveform diagram of FIG. 3 .

Fig. 5 shows a schematic diagram of functional modules of an electronic device according to a third embodiment of the present invention.

Detailed ways

The capacitance value measuring circuit according to the embodiment of the present invention can be used to measure the capacitance value of the capacitor to be measured, and convert the capacitance value into a digital output signal. In this way, it can be detected whether the capacitance value of the capacitor to be tested changes. In addition, according to the electronic device of the embodiment of the present invention, the internal touch screen and the sensor can share the same ADC, so as to reduce the circuit area and cost of the electronic device.

[first embodiment]

FIG. 1 shows a schematic circuit diagram of a capacitance measurement circuit according to a first embodiment of the present invention. FIG. 2 shows the relevant waveform diagram of FIG. 1 .

As shown in FIG. 1 , the capacitance measurement circuit includes: an analog-to-digital converter 110 , a capacitive voltage divider circuit 120 and a processing module 130 . The analog-to-digital converter 110 is, for example, a delta-sigma-delta analog-to-digital converter (sigma-deltaADC) with a sample-and-hold (S/H) function. The capacitive voltage divider circuit 120 includes: switches 121 - 123 , capacitors Cs and Cx. In this embodiment, V1, V2, and Vc are voltage sources, and it is assumed that V1<V2, and the clock signals ph1 and ph2 are mutually inverse.

One terminal of the switch 121 is coupled to the voltage source V2, and the other terminal is coupled to the node nx. The voltage of node nx is Vx. The conduction state of the switch 121 is controlled by the clock signal ph1. For example, when the clock signal ph1 is at a high potential, the switch 121 is turned on; and vice versa. When the switch 121 is turned on, the node voltage Vx is equal to V2.

One terminal of the switch 122 is coupled to the voltage source V2, and the other terminal is coupled to the node ns. The voltage of node ns is Vs. The conduction state of the switch 122 is controlled by the clock signal ph1. For example, when the clock signal ph1 is high, the switch 122 is turned on; and vice versa. When the switch 122 is turned on, the node voltage Vs is equal to V2.

One terminal of the switch 123 is coupled to the voltage source V1, and the other terminal is coupled to the node ns. The conduction state of the switch 123 is controlled by the clock signal ph2. For example, when the clock signal ph2 is high, the switch 123 is turned on; and vice versa. When the switch 123 is turned on, the node voltage Vs is equal to V1.

The capacitor Cs is coupled between the nodes ns and nx. The capacitance value of the capacitor Cs is known. The capacitor Cx is coupled between the node nx and the voltage source Vc. The capacitance value of the capacitor Cx is unknown, and the capacitance measuring circuit can be used to measure the capacitance value of the capacitor Cx.

Now please refer to FIG. 1 and FIG. 2 simultaneously to understand the operation of the capacitance measurement circuit of the first embodiment.

When the clock signal ph1 is at a high potential (that is, the clock signal ph2 is at a low potential), the switches 121 and 122 are both turned on, so that the node voltages Vx and Vs are both equal to V2.

When the clock signal ph1 changes from high to low (that is, the clock signal ph2 changes from low to high), the switch 123 is turned on, so that the node voltage Vs is equal to V1. In this way, the voltage at one end of the capacitor Cs (also the node voltage Vs) will change to (V1-V2). The voltage change (V1-V2) will be coupled to the node nx through the capacitor Cs, so that the node voltage Vx will change. The voltage variation of the node voltage Vx is shown in the following formula (1):

$<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; Cs</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Cs</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; Cx</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

The moment before the clock signal ph1 transitions, the node voltage Vx is V2. Immediately after the transition of the clock signal ph1, the node voltage Vx is as shown in the following formula (2):

$\mathrm{<span\; class="notranslate">\; Vx</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V"\; filenames="A2008102139730024H1.png"\; state="\{\{state\}\}">V</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; Cs</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Cs</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; Cx</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

After the node voltage Vx is sampled and held by the ADC 120, it is converted into a digital output value BOUT[N:1]. The decimal value of the digital output value BOUT[N:1] is represented as DOUT.

According to DOUT, the capacitance of the capacitor Cs, V1, V2, the conversion voltage range (Full Scale) and resolution of the ADC 120, the processing module 130 can calculate the capacitance of the capacitor Cx and its variation.

For example, if the conversion voltage range of ADC 120 is V2 to V1, and its resolution (resolution) is n bits (n is a positive integer), then the relationship between Cx, V1, V2, Cs, DOUT and n is as formula (3) Shown:

$\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V"\; filenames="A2008102139730024H1.png"\; state="\{\{state\}\}">V</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; Cs</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Cs</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; Cx</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&cong;</span>\frac{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="DOUT"\; filenames="A2008102139730024H1.png"\; state="\{\{state\}\}">DOUT</figure-callout></span>}}{{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

After simplifying formula (3), Cx can be obtained as shown in formula (4):

$\mathrm{<span\; class="notranslate">\; Cx</span>}<span\; class="notranslate">\; \&cong;</span>\frac{\frac{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="DOUT"\; filenames="A2008102139730024H1.png"\; state="\{\{state\}\}">DOUT</figure-callout></span>}}{{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="DOUT"\; filenames="A2008102139730024H1.png"\; state="\{\{state\}\}">DOUT</figure-callout></span>}}{{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; Cs</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

In this way, the capacitance value of the capacitor Cx can be obtained.

The capacitance measuring circuit of the first embodiment can be applied to capacitive switches, capacitive touch panels, capacitive display touch panels, and the like. When the user operates the capacitive switch, the capacitance value of the internal capacitor Cx to be measured will change with the user's operation; by measuring the capacitance value of the capacitance Cx and its variation through the capacitance value measurement circuit, the user can know or whether the capacitive switch is pressed. In addition, when the user operates the capacitive touch panel or the capacitive display touch panel, the capacitance value of the internal capacitance Cx to be measured will change as the user presses down; the capacitance Cx is measured by the capacitance measurement circuit The capacitance value and its change amount can be used to know the pressing position of the user.

[Second embodiment]

FIG. 3 shows a schematic circuit diagram of a capacitance measurement circuit according to a second embodiment of the present invention. FIG. 4 shows the relevant waveform diagram of FIG. 3 .

As shown in FIG. 1 , the capacitance measurement circuit includes: an analog-to-digital converter (ADC) 305 , a capacitive voltage divider circuit 380 and a bias circuit 390 . The analog-to-digital converter (ADC) 305 is, for example, a delta-sigma-delta analog-to-digital converter (sigma-delta ADC) with a sample-and-hold (S/H) function.

The ADC 305 includes: an operational amplifier (OP) 310, a comparator (CMP) 320, a latch 330, an inverter 340, a counter 350, switches 361-370, and capacitors 371-375.

The operational amplifier 310 has: a positive input terminal inp coupled to the switch 368 and the capacitor 374; a negative input terminal inn coupled to the switch 370 and the capacitor 373; a positive output terminal outp coupled to the positive input terminal of the comparator 320 and the capacitor 373 ; and the negative output terminal outn, coupled to the negative input terminal of the comparator 320 and the capacitor 374 .

The comparator 320 has: a positive input terminal coupled to the positive output terminal outp of the operational amplifier 310 ; a negative input terminal coupled to the negative output terminal outn of the operational amplifier 310 ; and an output terminal coupled to the latch 330 . The output signal C_OUT of the comparator 320 is input to the latch 330 .

The latch 330 receives the output signal C_OUT of the comparator 320 to output the digital signal D1. The latch 330 is controlled by the clock signal ph1.

The inverter 340 inverts the digital signal D1 into another digital signal D1B. That is, the digital signals D1 and D1B are inverse phases of each other.

The counter 350 counts the digital signal D1 to generate a counting result BOUT[N:1].

One terminal of the switch 361 is coupled to the voltage source ( V1 +V2 )/2 , and the other terminal is coupled to the capacitor 371 and the switch 362 . The conduction state of the switch 361 is controlled by the clock signal ph1.

One terminal of the switch 362 is coupled to the voltage source V2 , and the other terminal is coupled to the capacitor 371 and the switch 361 . The conduction state of the switch 362 is controlled by the clock signal ph2.

One terminal of the switch 363 is coupled to the voltage source ( V1 +V2 )/2 , and the other terminal is coupled to the capacitor 372 and the switch 366 . The conduction state of the switch 363 is controlled by the clock signal ph1.

One terminal of the switch 364 is coupled to the voltage source V1 , and the other terminal is coupled to the switches 365 and 366 . The conduction state of the switch 364 is controlled by the digital signal D1B.

One terminal of the switch 365 is coupled to the voltage source V2 , and the other terminal is coupled to the switches 364 and 366 . The conduction state of the switch 365 is controlled by the digital signal D1.

One terminal of the switch 366 is coupled to the capacitor 372 and the switch 363 , and the other terminal is coupled to the switches 364 and 365 . The conduction state of the switch 366 is controlled by the clock signal ph2. The switches 364 - 366 are used to transmit one of the voltage sources V1 and V2 to the capacitor 372 .

One terminal of the switch 367 is coupled to the voltage source V3 , and the other terminal is coupled to the switch 368 and capacitors 371 and 372 . The conduction state of the switch 367 is controlled by the clock signal ph1.

One terminal of the switch 368 is coupled to the switch 367 and capacitors 371 and 372 , and the other terminal is coupled to the positive input terminal inp of the operational amplifier 310 and the capacitor 374 . The conduction state of the switch 368 is controlled by the clock signal ph2. In addition, the switches 361 - 368 and the capacitors 371 - 372 can also be referred to as switch-capacitor circuits, which are coupled to the input terminal inp of the operational amplifier 310 . The switch-capacitor circuit is controlled by a clock signal ph1, a clock signal ph2, and digital signals D1 and D1B.

One terminal of the switch 369 is coupled to the voltage source V3, and the other terminal is coupled to the node nr. The conduction state of the switch 369 is controlled by the clock signal ph1.

One terminal of the switch 370 is coupled to the node nr, and the other terminal is coupled to the negative input terminal inn of the operational amplifier 310 and the capacitor 373 . The conduction state of the switch 370 is controlled by the clock signal ph2.

One terminal of the capacitor 371 is coupled to the switches 361 and 362 , and the other terminal is coupled to the switches 367 , 368 and the capacitor 372 .

One terminal of the capacitor 372 is coupled to the switches 363 and 366 , and the other terminal is coupled to the switches 367 , 368 and the capacitor 371 .

The capacitor 373 is coupled between the negative input terminal inn and the positive output terminal outp of the operational amplifier 310 to serve as a feedback circuit.

The capacitor 374 is coupled between the positive input terminal inp and the negative output terminal outn of the operational amplifier 310 to serve as a feedback circuit.

One terminal of the capacitor 375 is coupled to the node nx, and the other terminal is coupled to the switches 369 and 370 .

The capacitance values of the capacitors 371, 372 and 375 are C1; and the capacitance values of the capacitors 373 and 374 are C2.

In addition, the capacitor 375 and the switches 369-370 can also be referred to as a switch-sampling-capacitor circuit, which has: an input terminal coupled to one terminal nx of the Cs capacitor of the capacitive voltage divider circuit 380; and an output terminal coupled to the operation Amplifier input inn. The switch-sampling-capacitor circuit is controlled by the clock signals ph1 and ph2 to sample the terminal voltage Vx of the capacitor Cx.

The capacitive voltage divider circuit 380 includes: switches 381 - 383 and capacitors Cs and Cx. The capacitive voltage dividing circuit 380 is the same or similar to the capacitive voltage dividing circuit 120 of the first embodiment, and thus its details are omitted herein.

The bias circuit 390 is used to generate a charge variation (V2-V1) C1 to couple the charge variation to the node nr. That is, after a complete clock cycle time, the capacitive voltage divider circuit 380 and the bias circuit 390 will couple the charge variation of (Vx-V1)C1 to the node nr. The bias circuit 390 includes: switches 391 - 392 , and a capacitor 393 . The capacitance value of the capacitor 393 is C1.

One terminal of the switch 391 is coupled to the voltage source V1 , and the other terminal is coupled to the capacitor 393 . The conduction state of the switch 391 is controlled by the clock signal ph1.

One terminal of the switch 392 is coupled to the voltage source V2 , and the other terminal is coupled to the capacitor 393 . The conduction state of the switch 392 is controlled by the clock signal ph2.

One terminal of the capacitor 393 is coupled to the switches 391 and 392, and the other terminal is coupled to the node voltage Vr.

Now please refer to FIG. 3 and FIG. 4 simultaneously to understand the operation of the capacitance measurement circuit of this embodiment.

In this embodiment, the switching of the switch will cause the voltage Vx to change. The voltage Vx is input to the ADC 305 to obtain the digital value BOUT[N:1]. Thus, the capacitance value of the capacitor Cx to be measured is obtained.

How to know the voltage value Vx input to the ADC 305 will now be described.

Before and after the transition of the clock signal ph1 (that is, before and after the transition of the clock signal ph2), the charge of the node nx should be equal. Therefore, the charge of node nx satisfies formula (5):

(V2-V3)C1+(V2-V2)Cs+(V2-Vc)Cx＝(Vx(s)-V3)C1+(Vx(s)-V1)Cs+(Vx(s)-Vc)Cx (5)

In formula (5), the left side of the equation represents the charge at the node nx before the clock signal ph1 transitions, and the right side of the equation represents the charge at the node nx after the clock signal ph1 transitions. Wherein, Vx(s) represents the voltage Vx when the clock signal ph2 is enabled. That is, when the clock signal ph2 is enabled, in this embodiment, the ADC 305 samples and holds the voltage Vx to obtain the voltage Vx(s). Vx(s) is represented by formula (6):

$\mathrm{<span\; class="notranslate">\; Vx</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Cx</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V"\; filenames="A2008102139730023H1.png,A2008102139730023H2.png"\; state="\{\{state\}\}">V</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; Cs</span>}}{\mathrm{<span\; class="notranslate">\; Cx</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; Cs</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

When the output signal C_OUT of the comparator 320 is 0, the digital signal D1 is disabled (low potential), and the digital signal D1B is enabled (high potential). When the output signal C_OUT of the comparator 320 is 0, the charge at the input terminal inn of the operational amplifier 310 should be equal before and after the transition of the clock signal ph1 (that is, before and after the transition of the clock signal ph2 ). Therefore, the charge at the input terminal inn can be expressed as formula (7):

[V3-voutp((i-0.5))]C2+(V3-V1)C1+(V3-V2)C1

(7)

=[V3-voutp(i)]C2+(V3-V2)C1+[V3-Vx(s)]C1

Wherein, voutp(i-0.5) and voutp(i) respectively represent the node voltage voutp of the (i-0.5)th clock and the i-th clock.

Similarly, when the output signal C_OUT of the comparator 320 is 0, the charge at the input terminal inp of the operational amplifier 310 should be equal before and after the transition of the clock signal ph1 (that is, before and after the transition of the clock signal ph2 ). Therefore, the charge at the input terminal inp can be expressed as formula (8):

$<span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; voutn</span>}<span\; class="notranslate">\; (</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 0.5</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="C"\; filenames="A2008102139730024H1.png"\; state="\{\{state\}\}">C</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V"\; filenames="A2008102139730023H1.png,A2008102139730023H2.png"\; state="\{\{state\}\}">V</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; ]</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="C"\; filenames="A2008102139730023H1.png,A2008102139730023H2.png"\; state="\{\{state\}\}">C</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V"\; filenames="A2008102139730023H1.png,A2008102139730023H2.png"\; state="\{\{state\}\}">V</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; ]</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="C"\; filenames="A2008102139730023H1.png,A2008102139730023H2.png"\; state="\{\{state\}\}">C</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}$

$<span\; class="notranslate">\; =</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; voutn</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="C"\; filenames="A2008102139730024H1.png"\; state="\{\{state\}\}">C</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="C"\; filenames="A2008102139730023H1.png,A2008102139730023H2.png"\; state="\{\{state\}\}">C</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

Wherein, voutn(i-0.5) and voutn(i) respectively represent the node voltage voutn of the (i-0.5)th clock and the i-th clock.

After subtracting the two formulas (7) and (8), the formula (9) is obtained:

$<span\; class="notranslate">\; \{</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; voutp</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; voutn</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; voutp</span>}<span\; class="notranslate">\; (</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 0.5</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; voutn</span>}<span\; class="notranslate">\; (</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 0.5</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; \}</span><span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vx</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9</span>}<span\; class="notranslate">\; )</span>$

Because the differential output voltage vout of the operational amplifier 310 is the difference between the positive output voltage voutp and the negative output voltage voutn, formula (9) can be rewritten as formula (10):

$\mathrm{<span\; class="notranslate">\; \&Delta;vout</span>}<span\; class="notranslate">\; (</span><span\; class="notranslate">\; +</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; [</span>\mathrm{<span\; class="notranslate">\; vout</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; vout</span>}<span\; class="notranslate">\; (</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 0.5</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vx</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 10</span>}<span\; class="notranslate">\; )</span>$

Wherein, Δvout(+) represents the voltage variation of the output voltage vout of the operational amplifier 310 when D1 =0. It can be seen from formula (10) that Δvout(+) is a positive value (because V1>Vx(s)). That is, when D1=0, the output voltage vout will become high.

Similarly, it can be deduced that the voltage variation Δvout(-) of the output voltage vout of the operational amplifier 310 when D1=1 is shown in formula (11):

$\mathrm{<span\; class="notranslate">\; \&Delta;vout</span>}<span\; class="notranslate">\; (</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Vx</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>$

It can be seen from formula (11) that Δvout(-) is a negative value (because V2<Vx(s)). That is, when D1=1, the output voltage vout will become lower.

Within k clock cycles (k is a positive integer), if the digital signal D1 is 1, the number of clock cycles is m and the number of D1 is 0 clock cycles is n (m+n=k, m and n are both positive integers) , then the differential output voltage vout of the operational amplifier 310 can be expressed as formula (12):

vout(k)＝n·Δvout(+)+mΔvout(-)+vout(0) (12)

At this time, the differential output voltage vout(k) of the operational amplifier 310 can also be expressed as the original voltage vout(0) plus the difference voltage verr, as shown in formula (13):

vout(k)=vout(0)+verr (13)

Substituting formulas (10) and (11) into formula (12), and solving formulas (12) and (13), we can get:

$\mathrm{<span\; class="notranslate">\; Vx</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="nV"\; filenames="A2008102139730023H1.png,A2008102139730023H2.png"\; state="\{\{state\}\}">nV</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="mV"\; filenames="A2008102139730024H1.png"\; state="\{\{state\}\}">mV</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; verrC</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 14</span>}<span\; class="notranslate">\; )</span>$

则Vx(s)可近似于like

Then Vx(s) can be approximated as

$\mathrm{<span\; class="notranslate">\; Vx</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&cong;</span>\frac{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="nV"\; filenames="A2008102139730023H1.png,A2008102139730023H2.png"\; state="\{\{state\}\}">nV</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="mV"\; filenames="A2008102139730024H1.png"\; state="\{\{state\}\}">mV</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 15</span>}<span\; class="notranslate">\; )</span>$

Substituting formula (6) into formula (15), the relationship between the measured capacitance Cx, known capacitance Cs, n, m and C1 can be obtained as follows:

$\mathrm{<span\; class="notranslate">\; Cx</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; no</span>}}\mathrm{<span\; class="notranslate">\; Cs</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 16</span>}<span\; class="notranslate">\; )</span>$

In this way, the capacitance measurement circuit of this embodiment can measure the capacitance Cx to be measured and its variation according to the values m, n and the known capacitances Cs, C1.

In FIG. 4 , Tclk represents the period of the clock signal, and (i-0.5)Tclk and (i)Tclk represent the (i-0.5)th clock period and the (i)th clock period, respectively. When the clock signal ph2 is enabled, the voltage Vx is sampled. The sampling result will affect the output voltage vout of the operational amplifier 310 . When the clock signal ph2 is enabled, the voltage Vx will increase, and the charge change (Vx-V2) C1 will be coupled to the node nr, and the bias circuit 390 will also couple the charge change (V2-V1) C1 to the node on nr. That is, the change amount of charge coupled to node nr after a complete clock cycle time is (Vx-V1)C1. Since V1>Vx, the amount of change in the node charge of the node nr is a negative value, and the voltage Vr will become smaller. Therefore, when the clock signal ph2 is enabled, the output voltage vout has a positive integral effect (that is, increases) to maintain the charge conservation of the node nr, as shown in timing points 410 and 420 in FIG. 4 . The timing point 410 represents sampling the voltage Vx, and the timing point 420 represents the output voltage vout being boosted (the voltage variation is Δvout(+)).

When the output voltage vout of the operational amplifier 310 is higher than the critical value (0V), the output signal C_OUT of the comparator 320 becomes 1, as shown at timing point 430 . Since the output signal C_OUT of the comparator 320 becomes 1, the output signal D1 of the latch also becomes 1, as shown at timing point 440 . Since the output signal D1 is 1 (the output signal D1B is 0), as mentioned above, the output voltage vout will decrease (the voltage variation is Δvout(−)), and will be less than 0, as shown at timing point 450 .

Since the output voltage vout is less than 0 at the timing point 450 , subsequently, the output signal C_OUT of the comparator 320 turns to 0 and the digital signal D1 also turns to 0, so that the output voltage vout is positively integrated again. In this way, the number of clock cycles in which the digital signal D1 is 1 and the number of clock cycles in which the digital signal D1 is 0 can be known, and thus the capacitance value of the capacitor Cx can be deduced.

The capacitance measurement circuit of the second embodiment can be applied to capacitive switches, capacitive touch panels, capacitive display touch panels, and the like. When the user operates the capacitive switch, the capacitance value of the internal capacitor Cx to be tested will change with the operation of the user; by measuring the capacitance value change of the capacitor Cx through the capacitance value measuring circuit, it can be known whether the user is Press the capacitive switch. In addition, when the user operates the capacitive touch panel or the capacitive display touch panel, the capacitance value of the internal capacitance Cx to be measured will change as the user presses down; the capacitance Cx is measured by the capacitance value measurement circuit The capacitance value changes, and the user's pressing position can be known.

In addition, in the first and second embodiments of the present invention, since the delta-sigma ADC has a sample-hold function, therefore, in the capacitance value measuring circuits of the first and second embodiments of the present invention, there is no need for sample-hold circuit. However, the present invention is not limited thereto. If the ADC used in the capacitance value measurement circuit does not have a sample-hold function, a sample-hold circuit is required in the capacitance value measurement circuit. The sample-hold circuit samples-holds the voltage Vx (or the voltage V1-Vx), and then sends the sample-hold result to the ADC.

In addition, in the first and second embodiments of the present invention, since the operational amplifier is a differential amplifier, common noise can be suppressed.

[Third embodiment]

Fig. 5 shows a schematic diagram of functional modules of an electronic device according to a third embodiment of the present invention. The electronic device is, for example but not limited to, a digital camera with a touch screen. The electronic device includes: a sensor 510, a multiplexer 520 and an ADC 530.

The sensor 510 is, for example but not limited to, a light sensor, a tilt sensor, a temperature sensor and a humidity sensor. The sensor 510 can sense the external environment and convert it into an analog voltage. The analog voltage is converted into a digital signal by the ADC 530, and then the back-end processing module determines how to control the electronic device according to the output signal of the ADC.

For example, sensor 510 includes a light sensor. If the light sensor detects that the external light source is dark, the back-end processing module can make the electronic device enter a low power consumption mode. However, when the light sensor detects that the external light source is bright, the output voltage of the light sensor changes. Therefore, the back-end processing module can make the electronic device enter a normal operation mode.

For another example, the sensor 510 includes a tilt sensor. If the tilt sensor senses that the electronic device is tilted/rotated by a certain angle (for example, the user tilts/rotates the electronic device by 90 degrees), the output voltage will change, and the back-end processing module can make the electronic device The on-screen display picture matches the tilt/rotation angle so that the user can watch the on-screen display picture conveniently.

For another example, the sensor 510 includes a temperature sensor or a humidity sensor. According to the sensing result of the external environment by the temperature sensor or the humidity sensor, the back-end processing module can optimize the adjustment of the electronic device.

The required sensors can be incorporated into the electronic device as required. In this way, the electronic device has the advantage of smart operation.

The multiplexer 520 is used to selectively output the voltage Vx or the output signal of the sensor to the ADC 530.

The ADC 530 may be the same or similar to the ADC of the first embodiment or the second embodiment, and thus details thereof will not be repeated here. In the third embodiment, Vx is the voltage of the capacitor Cx to be tested in the first or second embodiment, which can be used to detect the position of the user's touch point. In the third embodiment of the present invention, since the touch screen and the sensor share the ADC, the electronic device has the advantage of reducing the circuit area.

In addition, the internal components of the capacitance measuring circuit of the first embodiment or the second embodiment can be added to the electronic device of the third embodiment according to the situation, and these are all within the scope of the present invention.

To sum up, although the present invention has been disclosed by the embodiments above, they are not intended to limit the present invention. Those skilled in the art to which the present invention belongs should be able to make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the appended claims.

Explanation of main component symbols

110: Analog-to-digital converter 120: Capacitive voltage divider circuit

121～123: switch 130: processing module

Cs, Cx: capacitance 305: analog-to-digital converter

310: Operational Amplifier 320: Comparator

330: Latch 340: Inverter

350: Counter 361～370: Switch

371～375: capacitor 380: capacitive voltage divider circuit

381～383: switch 390: bias circuit

391～392: switch 393: capacitor

410～450: timing point 510: sensor

520: Multiplexer 530: ADC.

Claims (7)

1. A capacitance measurement circuit, comprising: A capacitive voltage divider circuit, comprising: a switch circuit, a first capacitor and a second capacitor, the switch circuit is coupled to the first capacitor and the second capacitor, the switch circuit is controlled by the first clock signal and the second capacitor A second clock signal, the second clock signal is an inversion signal of the first clock signal, and the conduction state of the switch circuit makes the voltage variation of the first terminal of the first capacitor coupled to the first the first terminal of the second capacitor; an analog-to-digital converter coupled to the capacitive voltage divider circuit, the analog-to-digital converter converts the voltage at the first terminal of the second capacitor into a first digital signal; and a processing module, coupled to the analog-to-digital converter, the processing module detects the capacitance value of the second capacitor according to the first digital signal of the analog-to-digital converter and the parameters of the analog-to-digital converter and its variation. 2. The capacitance measuring circuit according to claim 1, wherein the switch circuit of the capacitive voltage divider circuit comprises: A first switch, the first end of which is coupled to the first voltage source, and the second end of which is coupled to the first end of the second capacitor, the conduction of the first switch is controlled by the first clock signal ; The first end of the second switch is coupled to the first voltage source, the second end is coupled to the first end of the first capacitor, and the conduction of the second switch is controlled by the first clock signal; and A third switch, the first end of which is coupled to the second voltage source, the second end of which is coupled to the first end of the first capacitor, and the conduction of the third switch is controlled by the second clock signal ; Wherein, the second terminal of the first capacitor is coupled to the first terminal of the second capacitor, and the second terminal of the second capacitor is coupled to a third voltage source. 3. The capacitance measuring circuit according to claim 2, wherein: The parameters of the analog-to-digital converter include: the resolution and conversion voltage range of the analog-to-digital converter; and The processing module is further based on the voltage value of the first voltage source, the voltage value of the second voltage source and the capacitance value of the first capacitor, the resolution of the analog-to-digital converter, the analog-to-digital conversion Converting the voltage range of the converter and the first digital signal of the analog-to-digital converter to detect the capacitance value of the second capacitor and its variation. 4. The capacitance measuring circuit according to claim 1, further comprising: a bias voltage circuit, coupled to the capacitive voltage divider circuit and the analog-to-digital converter, the bias voltage circuit is used to apply a bias voltage to the first node, so that the voltage of the first node is the same as the bias voltage The voltage is related to the voltage of the first terminal of the second capacitor. 5. The capacitance measuring circuit according to claim 1, wherein the analog-to-digital converter comprises: A switch-sampling-capacitor circuit has: a first input end coupled to the first end of the second capacitor of the capacitive voltage divider circuit; and an output end; the switch-sampling-capacitance circuit is controlled by The first clock signal and the second clock signal are used to sample the voltage at the first end of the second capacitor of the capacitive voltage divider circuit; The operational amplifier has: a first input terminal coupled to the output terminal of the switch-sampling capacitor circuit; a second input terminal; a first output terminal and a second output terminal; The comparator has: a first input terminal coupled to the first output terminal of the operational amplifier; a second input terminal coupled to the second output terminal of the operational amplifier; and an output terminal outputting a second digital signal ; a latch, configured to receive the second digital signal output by the comparator, and under the trigger of the first clock signal, the latch outputs the second digital signal into a third digital signal; an inverter, inverting the third digital signal; a counter counting the third digital signal to generate the first digital signal; and A switch-capacitor circuit, coupled to the second input terminal of the operational amplifier, controlled by the first clock signal, the second clock signal, the third digital signal and the inverse of the third digital signal phase signal. 6. An electronic device comprising: The capacitance to be measured is used to output the voltage to be measured; a sensor for outputting a sensing signal; a multiplexer, coupled to the capacitor under test and the sensor, to output one of the voltage under test and the sensing signal; and An analog-to-digital converter, coupled to the multiplexer, for converting the voltage to be measured or the sensing signal into a digital output signal, the digital output signal representing the capacitance value of the capacitor to be measured and its The variation, or represents the sensing result of the sensor. 7. The electronic device according to claim 6, further comprising: A touch screen, wherein the capacitance to be measured is located in the touch screen.

Images