CN102142425A - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device capable of miniaturization of electronic circuits. The MOS transistor (20) has a gate electrode (22) formed into a grid, a source region (23) and a drain region (24) surrounded by the gate electrode (22), along one direction of the grid of the gate electrode (22) A source metal wiring (27) and a drain metal wiring (28) are arranged and connected to the source region (23) and the drain region (24) through contact points. The source region (23) and the drain region (24) are each formed in a rectangular shape having a long side in the longitudinal direction of each metal wiring. The source metal wiring (27) and the drain metal wiring (28) are formed in a zigzag shape in their longitudinal direction, and are respectively connected to the source contact (25) and the drain contact (26).

Description

Semiconductor device

technical field

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a transistor in which a source region and a drain region are arranged adjacent to each other with a gate electrode formed in a grid shape interposed therebetween.

Background technique

Conventionally, there is known a MOS transistor in which the gate electrode is formed in a grid shape in order to improve the efficiency of the gate width (GW) per unit area (see, for example, Non-Patent Document 1). This MOS transistor is called a lattice (checkered) transistor.

FIG. 1 shows a schematic planar structure of a conventional grid transistor 1 . The grid-shaped transistor 1 includes a grid-shaped gate electrode 2 and a diffusion region surrounded by the gate electrode 2 . In order to improve the fine density of the circuit, the diffusion area adopts a square shape. The diffusion region constitutes the source region 3 or the drain region 4 , and the source region 3 and the drain region 4 are arranged adjacent to each other with the gate electrode 2 interposed therebetween. A source contact 5 and a drain contact 6 for connecting to a metal wiring are formed in the source region 3 and the drain region 4 , respectively.

Non-Patent Document 1: Alan Hastings (author), "The Art of ANALOG LAYOUT", pp416-417, Chapter12

In the grid transistor 1, all the source regions 3 and all the drain regions 4 are respectively connected to a common electrode. In the grid transistor 1, in the first metal layer above the back gate diffusion layer, each source contact point 5 is connected to the source metal wiring extending in one direction along the grid of the gate electrode 2, In addition, each drain contact 6 is connected to a drain metal wiring extending in the same direction along the grid of the gate electrode 2 . In the first metal layer, metal wiring for source and metal wiring for drain are alternately formed. In the second metal layer above the first metal layer, a plurality of source metal wirings are connected to a common source electrode, and similarly, a plurality of drain metal wirings are connected to a common drain electrode.

FIG. 2 shows an example of a schematic arrangement of metal wiring in the first metal layer. As shown in the figure, the metal wiring 7 for the source and the metal wiring 8 for the drain are formed extending in the same direction along the grid of the gate electrode 2, and they are respectively connected to the contact point 5 for the source and the contact point for the drain. 6 on. In addition, in FIG. 2 , the illustration of the drain metal wiring 8 connected to the drain contact 6 located on the upper side and the lower side is omitted in this plan view.

The metal wiring 7 for the source and the metal wiring 8 for the drain are formed so that they have an elongated rectangular region formed so as to cover the upper part of the gate electrode 2 extending in the longitudinal direction thereof, and a contact point for each diffusion region. Convex regions protruding widthwise from the elongated rectangular regions connected to each other. For this reason, as shown in the figure, the width of the metal wiring becomes thicker at the portion with the convex region, and narrower at the portion without the convex region. In particular, if the diffusion region is formed at the highest density, it may not be possible to lead out wiring in an oblique direction due to layout restrictions. In this way, since the width of the metal wiring varies in the longitudinal direction, the parasitic resistance in the narrow region increases. The metal resistance of the metal wiring is added to the input and output resistance of the MOS transistor. Since the increase in parasitic resistance increases the total on-resistance in which the parasitic resistance of the wiring is added to the on-resistance of the transistor, and the loss of driving capability is not preferable. In the past, grid-shaped transistors were purposefully introduced to reduce the circuit scale by improving the efficiency of the gate width (GW) per unit area, reduce the on-resistance of the transistor, and improve the driving capability. However, due to its metal wiring The increase of the resistance and the increase of the total on-resistance will have to lose the original advantages.

Contents of the invention

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device in which the resistance of metal wiring is reduced. Furthermore, an object of the present invention is to achieve miniaturization of electronic circuits.

In order to solve the above-mentioned problems, a semiconductor device according to a certain aspect of the present invention has a transistor including: a gate electrode formed in a grid shape, a source region and a drain region surrounded by the gate electrode, and one of the grids along the gate electrode. The metal wiring is arranged in a direction and connected to the source region and the drain region through a contact point; the source region and the drain region are arranged adjacent to each other with the gate electrode sandwiched; the source region and the drain region are respectively formed to have long sides in the length direction of the metal wiring of rectangular shape.

(invention effect)

According to the present invention, it is possible to provide a semiconductor device having a MOS transistor with reduced resistance of metal wiring. Furthermore, according to the present invention, miniaturization of electronic circuits can be achieved.

Description of drawings

FIG. 1 is a schematic plan view showing a conventional grid transistor.

FIG. 2 is a diagram showing an example of a schematic arrangement of metal wirings in a first metal layer.

FIG. 3 is a configuration diagram showing a switch circuit according to an embodiment of the present invention.

4 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention.

Fig. 5 is a plan view showing a diffusion region constituting a source region or a drain region.

FIG. 6 is a diagram showing an example of a schematic arrangement of metal wirings in a first metal layer of a MOS transistor.

FIG. 7 is a diagram showing a partial cross section of the MOS transistor of FIG. 6 taken along line A-A.

Fig. 8 is a circuit diagram of VBUS-SW.

9( a ) is a schematic plan view showing the first metal layer when 20 transistor cells are arranged, and FIG. 9( b ) is a schematic plan view showing the second metal layer.

Fig. 10 is a schematic plan view showing the third metal layer.

Fig. 11 is a circuit diagram of AUDIO-SW.

FIG. 12 is a diagram showing a modified example of the schematic planar structure of the semiconductor device according to the embodiment.

FIG. 13 is a diagram showing a modification example of the schematic arrangement of metal wirings in the first metal layer of the MOS transistor.

(Symbol Description)

20-MOS transistor, 22-gate electrode, 23-source region, 24-drain region, 25-contact point for source, 26-contact point for drain, 27-metal wiring for source, 28-metal for drain Wiring, 40 - first metal layer.

Detailed ways

FIG. 3 shows the configuration of the switch circuit 10 according to the embodiment of the present invention. The switch circuit 10 is mounted on an electronic device such as a mobile phone or a PDA (Personal Digital Assistant). The electronic device has a connector 16, and peripheral devices such as a PC (Personal Computer, Personal Computer) and earphones are connected to the connector 16 . In the switch circuit 10 , the common input and output unit 15 is connected to the connector 16 , and signals input and output to and from external devices or peripheral devices pass through the common input and output unit 15 . The structure of the switch circuit 10 includes at least: USB-SW11, AUDIO-SW12, UART-SW13 and VBUS-SW14.

If the electronic device is connected to the external device by USB (Universal Serial Bus) through the connector 16, then the USB-SW11 is turned on and can send and receive USB signals. At this time, the VBUS-SW 14 is also turned on, the VBUS power supplied via the USB is output as VBUSOUT, and the internal power generating circuit 17 generates the internal power intVCC. Also, when an earphone is connected to the connector 16, the AUDIO-SW12 is turned on, and sound is output from the earphone. In addition, when UART (Universal Asynchronous Receiver Transmitter) signal is sent and received, UART-SW13 is turned on. In this way, the switch circuit 10 controls the on and off of each switch according to the device connected to the connector 16 .

In order to pass high-frequency signals and low-level analog audio signals with low loss and low distortion, it is preferable that the switch circuit 10 reduce the total on-resistance (on-resistance of transistors + parasitic resistance of wiring) as much as possible. On the other hand, in order to increase the bandwidth of the USB-SW, it is preferable to reduce the capacity of the common input/output unit 15 . Although it is generally necessary to increase the gate width (GW) in order to reduce the on-resistance of a transistor, this leads to an increase in parasitic capacitance as a side effect. The inventors of the present invention contributed to miniaturization of the circuit scale by improving the efficiency of the gate width (GW) per unit area of the grid-like transistor, and focused on the reduction of compatible on-resistance and parasitic capacitance, and achieved reductions related to conventional grids. The layout of metal wiring resistors like transistors becomes problematic.

FIG. 4 shows a schematic planar structure of a semiconductor device according to an embodiment of the present invention. The semiconductor device of the present embodiment includes a MOS transistor 20 which is a lattice transistor. The grid-shaped transistor has an advantage of realizing downsizing of a circuit since the gate width (GW) per unit area is effectively increased.

The MOS transistor 20 has a grid-like gate electrode 22 formed of polysilicon or the like. Specifically, the gate electrode 22 is structured to have a plurality of rows extending in the first direction with a predetermined first interval a, and a plurality of rows extending in a direction orthogonal to the first direction with a predetermined second interval b (>a). A plurality of rows extending in the second direction. A plurality of diffusion regions surrounded by gate electrode 22 have the same rectangular shape and constitute source region 23 or drain region 24 . The source region 23 and the drain region 24 are arranged adjacent to each other with the gate electrode 22 interposed therebetween. Focusing on a certain source region 23, the drain region 24 is arranged in a region adjacent to each other in four directions (front, back, left, right, right) across the gate electrode 22 that divides this region. Similarly, focusing on a certain drain region 24, the source region 23 is arranged in a region adjacent to each other in four directions sandwiching the gate electrode 22 that divides this region. That is, the source region 23 and the drain region 24 are arranged in a grid shape on the substrate, and the source region 23 and the drain region 24 are respectively continuous in an oblique direction. In the source region 23 and the drain region 24 , a source contact 25 and a drain contact 26 for connecting to the metal wiring of the first metal layer are formed, respectively.

FIG. 5 shows the planar structure of the diffusion region constituting the source region 23 or the drain region 24 . In the MOS transistor 20 of the present embodiment, the diffusion region is formed in a rectangular shape. Preferably, the aspect ratio (b/a) when the length of the long side is b and the length of the short side is a is 1.2 or more. It is preferable to set the length a of the short side to be substantially equal to the length of one side of the diffusion region that can be realized when the fineness of the MOS transistor 20 is maximized. The source region 23 and the drain region 24 are each formed to have long sides in the length direction of the metal wiring of the first metal layer.

FIG. 6 shows an example of a schematic arrangement of metal wiring in the first metal layer of the MOS transistor 20 . FIG. 7 shows a partial cross section of MOS transistor 20 of FIG. 6 taken along line A-A. First, the structure of the MOS transistor 20 will be described with reference to FIG. 7 .

A back gate diffusion layer 32 is formed on the surface of the P-type silicon substrate 31 . On the surface portion of the back gate diffusion layer 32 , source regions 23 and drain regions 24 are alternately and repeatedly formed. On the channel region between source region 23 and drain region 24 , gate electrode 22 is formed via gate oxide film 33 . The source metal wiring 27 and the drain metal wiring 28 are formed in the first metal layer 40, and the source region 23 and the drain region 24 are respectively connected to the source metal wiring 25 and the drain contact point 26 through the source contact point 25 and the drain contact point 26. wiring 27 and metal wiring 28 for the drain. In addition, the illustration of the interlayer insulating film etc. between the gate electrode 22 and the 1st metal layer 40 is abbreviate|omitted.

Referring to FIG. 6, metal wiring 27 for the source and metal wiring 28 for the drain are arranged along one direction of the grid of the gate electrode 22, and they are respectively connected to a plurality of contact points 25 for the source and contact points 26 for the drain. . By arranging the metal wiring 27 for the source and the metal wiring 28 for the drain along one direction of the grid of the gate electrode 22, the lengths of the plurality of metal wirings in the MOS transistor 20 can be made substantially equal. The parasitic resistance distribution of the metal wiring in the MOS transistor 20 can be made constant compared to the case where the lengths of the MOS transistors 20 are different. In addition, although the drain metal wiring 28 is not connected to the upper and lower drain contact points 26 in plan view, the drain metal wiring 28 may be connected to them in practice.

The metal wiring 27 for a source and the metal wiring 28 for a drain are formed in the zigzag shape in the longitudinal direction, and are connected to the contact 25 for a source and the contact 26 for a drain, respectively. The source metal wiring 27 is arranged above one gate row extending in the longitudinal direction thereof, and is connected to the source contacts 25 formed on the source regions 23 located on both sides of the gate row. In this manner, by forming the source metal wiring 27 in a zigzag shape, it is possible to efficiently connect the source contacts 25 arranged in a zigzag manner across one gate row.

Similarly, the drain metal wiring 28 is disposed above one gate row extending in the longitudinal direction thereof, and is connected to the drain contact 26 formed on the drain region 24 on both sides of the gate row. In this way, by forming the drain metal wiring 28 in a zigzag shape, it is possible to efficiently connect the drain contacts 26 arranged in a zigzag manner with one gate row interposed therebetween.

Specifically, in the first metal layer 40 , the source metal wiring 27 is arranged to overlap on the gate row extending in the longitudinal direction thereof. By overlapping the source metal wiring 27 so as to cover the gate electrode 22 extending in one direction, the coverage of the source metal wiring 27 can be improved and parasitic resistance can be reduced. The plurality of source metal wirings 27 are connected to a common source electrode in the second metal layer formed above the first metal layer 40 via an interlayer insulating film. In addition, in the first metal layer 40 , the drain metal wiring 28 is arranged to overlap the gate row extending in the longitudinal direction thereof. By arranging the drain metal wiring 28 so as to cover the gate electrode 22 extending in one direction, the degree of coverage of the drain metal wiring 28 can be increased and parasitic resistance can be reduced. The plurality of drain metal wirings 28 are connected to a common drain electrode in the second metal layer formed above the first metal layer 40 via an interlayer insulating film.

The source metal wiring 27 has the same width in its longitudinal direction (the length in the direction perpendicular to the longitudinal direction). Compared with the source metal wiring 7 shown in FIG. 2 , since the source metal wiring 27 is formed with a uniform width, parasitic resistance can be reduced. Likewise, the drain metal wiring 28 also has the same width in its longitudinal direction. Compared with the drain metal wiring 28 shown in FIG. 2 , since the drain metal wiring 28 is formed with a uniform width, parasitic resistance can be reduced. The metal wiring 27 for a source and the metal wiring 28 for a drain may have the same shape, and both may be formed in the same width.

In addition, it is preferable that the metal wiring 27 for a source and the metal wiring 28 for a drain are arrange|positioned with predetermined space|interval between each other in the whole length direction. It is preferable that the metal wiring 27 for a source and the metal wiring 28 for a drain maintain predetermined space|interval in the longitudinal direction, and are formed in width as thick as possible. Thereby, the parasitic resistance of wiring can be further reduced.

In FIG. 6, the structure of a MOS transistor 20 having a total of 36 diffusion regions is shown. The source region 23 and the drain region 24 of the MOS transistor 20 are respectively short-circuited in the second metal layer. In addition, it is also possible to form a single transistor by combining a plurality of MOS transistors 20 which are grid-shaped transistors as a unit. If MOS transistors 20 of a predetermined size are modularized as one transistor unit, wiring and the like can be shortened by combining a plurality of transistor units two-dimensionally, and the capacity of the transistor can be reduced.

In this case, as described above, in one transistor cell (for example, MOS transistor 20 ), a plurality of source regions 23 and drain regions 24 are respectively connected by a common source electrode and drain electrode formed in the second metal layer. In the case of forming one transistor from a plurality of transistor cells, the source electrode and the drain electrode of each transistor cell are connected in the second metal layer, or the second metal layer is connected in the third metal layer formed above the second metal layer. The source electrode and the drain electrode of each transistor unit in the second metal layer. By adopting such a structure, one MOS transistor can be formed from a plurality of transistor cells.

Fig. 8 is a circuit diagram of VBUS-SW14. The VBUS-SW14 is composed of a transistor TR1 and a transistor TR2, and both drains are connected to each other. Each of the transistor TR1 and the transistor TR2 is composed of a plurality of transistor units.

FIG. 9( a ) shows a schematic planar structure of the first metal layer when 20 transistor units 100 to 119 are arranged. In this example, the transistor TR1 is composed of ten transistor units 100 , 101 , 102 , 103 , 104 , 105 , 106 , 107 , 108 , and 109 . Furthermore, the transistor TR2 is composed of ten transistor units 110 , 111 , 112 , 113 , 114 , 115 , 116 , 117 , 118 , and 119 . As shown in the figure, in the first metal layer, the wiring length direction of the transistor units constituting the transistor TR1 is perpendicular to the wiring length direction of the transistor units constituting the transistor TR2.

Figure 9(b) shows a schematic planar structure of the second metal layer. In the second metal layer, the drains of the transistor cells 100 to 119 are commonly connected to the drain electrode 130 by a metal wiring.

The sources of the transistor cells 100 to 109 constituting the transistor TR1 are connected to the source electrodes 120 , 121 , 122 , and 123 by metal wirings. Specifically, the sources of the transistor units 100-103 are connected to the source electrode 120 by metal wiring, the source electrodes of the transistor units 104-106 are connected to the source electrode 121 by metal wiring, and the source electrodes of the transistor units 107-108 are connected by metal wiring. It is connected to the source electrode 122, and the source of the transistor cell 109 is connected to the source electrode 123 by a metal wiring.

The sources of the transistor cells 110 to 119 constituting the transistor TR2 are connected to the source electrodes 124 , 125 , 126 , and 127 by metal wirings. Specifically, the sources of the transistor units 110-113 are connected to the source electrode 124 by metal wiring, the sources of the transistor units 114-116 are connected to the source electrode 125 by metal wiring, and the sources of the transistor units 117-118 are connected by metal wiring. It is connected to the source electrode 126, and the source of the transistor cell 119 is connected to the source electrode 127 by a metal wiring.

FIG. 10 shows a schematic planar structure of the third metal layer. The area demarcated by a dot-dash line shows the chip shape of VBUS-SW14. Source electrodes 120 to 123 are connected to VBUSOUT, and source electrodes 124 to 127 are connected to VBUS. In addition, the drain electrode 130 is connected to VBUSMID. By arranging VBUS as input to VBUS-SW14 and VBUSOUT as output at the corners of the chip, it is possible to reduce wiring resistance in input and output.

As described above, the VBUS-SW 14 is configured by combining and connecting a plurality of transistor cells 100 to 119 two-dimensionally. Specifically, ten transistor units 100 to 109 are connected in steps to form a transistor TR1, and ten transistor units 110 to 119 are connected in a step to form a transistor TR2. By combining the steps, one transistor switch is formed.

On the other hand, VBUS-SW 14 can also be configured by, for example, one-dimensionally arranging the transistor cells 100 to 119 in series (one column). In this case, the electrodes in the second metal layer become longer. For this reason, compared with the case where the transistor cells 100 to 119 are combined two-dimensionally, the parasitic capacitance at the time of one-dimensional connection increases. Therefore, as described above, by arranging the transistor cells 100 to 119 two-dimensionally, it is possible to configure the VBUS-SW 14 with reduced parasitic resistance.

Next, a configuration for further reducing the capacity of the common input/output section 15 in the switch circuit 10 will be described.

Since the switch circuit 10 passes high-frequency USB signals, the lower the parasitic capacitance of the common input/output section 15, the better. However, since a plurality of switches are connected to the common input-output unit 15 , the capacitance in each switch becomes an obstacle to reducing the capacity of the common input-output unit 15 . In particular, the parasitic capacitance of the AUDIO-SW 12 becomes large, and by reducing this, the parasitic capacitance of the common input/output section 15 can be significantly reduced.

FIG. 11 shows a circuit diagram of AUDIO-SW12. The AUDIO-SW 12 includes a transistor TR3 that is turned on when audio is output from the terminal 16 to the common input/output unit 15 .

In the existing AUDIO-SW, all circuit components can be configured to work with the maximum internal power supply voltage intVCC. In particular, in an electronic device that supplies VBUS as the internal power supply voltage intVCC when the USB connection is made to an external device, and supplies the battery voltage as the internal power supply voltage intVCC when the USB connection is not made, it is necessary to use a device that can withstand the supply of the maximum internal power supply voltage intVCC. circuit components. If VBUS (5V) is the maximum internal power supply voltage intVCC, circuit elements for 5V withstand voltage can be used as circuit elements. Based on such a situation, in the conventional AUDIO-SW, a transistor for withstand voltage of 5V is used as the transistor TR3, and therefore, there is a problem that the parasitic capacitance of the common input/output part 15 becomes large.

Therefore, in AUDIO-SW12 of this embodiment, the transistor for withstand voltages lower than the maximum internal power supply voltage intVCC (5V) is used as transistor TR3. For example, a 3V withstand voltage transistor is used for the transistor TR3. On the other hand, transistors for 5V withstand voltage are used as circuit elements for supplying voltage to transistor TR3 , specifically transistors TR4 and TR5 , and transistors constituting gate control circuit 18 and substrate voltage control circuit 19 . By setting the transistor TR5, the gate voltage of the transistor TR3 has been dropped below 3V. Thus, by forming a circuit element that lowers the gate voltage of the transistor TR3, the transistor TR3 can be formed of a transistor for low withstand voltage with a thin gate oxide film, and the capacity of the common input/output portion 15 can be reduced.

In the foregoing, the present invention has been explained based on the embodiments. This example is an illustration, and those skilled in the art will understand that various modifications can be made in the combination of these constituent elements and each treatment process, and these modifications are also within the scope of the present invention.

FIG. 12 shows a modified example of the schematic planar structure of the semiconductor device of the embodiment. Compared with FIG. 4 , in the MOS transistor 20 shown in FIG. 12 , the source region 23 and the drain region 24 have a plurality of source contacts 25 and drain contacts 26 , respectively. The gate electrode 22 is configured to have a plurality of rows extending in the first direction with a predetermined first interval a, and second rows extending in a direction orthogonal to the first direction with a predetermined second interval c (>b). A number of rows extending in the direction.

By forming a plurality of source contacts 25 and drain contacts 26 in one source region 23 and drain region 24, the respective contact resistances can be reduced. In addition, in the example shown in FIG. 12, although two contact points are formed with respect to one diffusion region, they are not limited to two, and may be three or four or more.

FIG. 13 shows a modification example of the schematic configuration of the metal wiring in the first metal layer of the MOS transistor 20 shown in FIG. 12 . Source metal wiring 27 and drain metal wiring 28 are arranged along one direction of the grid of gate electrode 22 , and are connected to a plurality of source contacts 25 and drain contacts 26 , respectively. In the MOS transistor 20 shown in FIG. 12, although a plurality of contacts are formed in one diffusion region, it is preferable to arrange the contacts in the diffusion region along the direction in which the metal wiring extends. By arranging the contact points in this way, the metal wiring can be efficiently connected to the contact points without increasing parasitic capacitance.

Claims (4)

1. semiconductor device, it is characterized in that, has transistor, this transistor comprises: the gate electrode that forms lattice-shaped, the source region and the drain region that are surrounded by above-mentioned gate electrode, and along a direction configuration of the grid of above-mentioned gate electrode and the metal line that is connected with above-mentioned source region and above-mentioned drain region by contact point; Above-mentioned source region and the above-mentioned gate electrode of above-mentioned drain region clamping are adjacent to configuration;

Above-mentioned source region and above-mentioned drain region are formed in the oblong-shaped that has long limit on the length direction of above-mentioned metal line respectively.

2. semiconductor device according to claim 1 is characterized in that,

Be formed with the source electrode metal line that is connected with contact point with the source electrode that forms in above-mentioned source region, with the drain electrode metal line that is connected with contact point with drain electrode in the formation of above-mentioned drain region;

Above-mentioned source electrode is formed zigzag fashion with metal line with metal line and above-mentioned drain electrode on its length direction, be connected with contact point with contact point and above-mentioned drain electrode with above-mentioned source electrode respectively.

3. semiconductor device according to claim 2 is characterized in that,

Above-mentioned source electrode is overlapping respectively with metal line with metal line and above-mentioned drain electrode, be configured on the above-mentioned gate electrode that its length direction extends.

4. according to claim 2 or 3 described semiconductor device, it is characterized in that,

Above-mentioned source electrode has identical width with metal line on its length direction, above-mentioned drain electrode has identical width with metal line on its length direction.

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