CN102403283B - Ball grid array packaging structure with basic islands and manufacturing method thereof - Google Patents

Ball grid array packaging structure with basic islands and manufacturing method thereof Download PDF

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Publication number
CN102403283B
CN102403283B CN2011103787975A CN201110378797A CN102403283B CN 102403283 B CN102403283 B CN 102403283B CN 2011103787975 A CN2011103787975 A CN 2011103787975A CN 201110378797 A CN201110378797 A CN 201110378797A CN 102403283 B CN102403283 B CN 102403283B
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metal substrate
pin
grid array
ball grid
basic island
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CN102403283A (en
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王新潮
梁志忠
谢洁人
吴昊
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to PCT/CN2012/000023 priority patent/WO2013075384A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/042—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/456—Materials
    • H10W70/457—Materials of metallic layers on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/475—Capacitors in combination with leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明涉及一种有基岛球栅阵列封装结构及其制造方法，所述结构包括外基岛（1）和外引脚（2），所述外基岛（1）正面设置有芯片（5），外引脚（2）正面通过多层电镀方式内引脚（4），所述内引脚（4）正面延伸到芯片（5）旁边，所述芯片（5）正面与内引脚（4）正面之间用金属线（6）连接，所述内引脚（4）、芯片（5）和金属线（6）外包封有塑封料（7），所述外基岛（1）和外引脚（2）的背面设置有锡球（9）。本发明的有益效果是：它省去了金属基板双面蚀刻的作业工序，降低了工序作业的成本，而且由于内引脚采用多层电镀方式形成，因此实现了内引脚的高密度能力。

Figure 201110378797

The invention relates to a ball grid array packaging structure with a base island and a manufacturing method thereof. The structure includes an outer base island (1) and outer pins (2), and a chip (5) is arranged on the front side of the outer base island (1) ), the front side of the outer pin (2) is multi-layer electroplated and the inner pin (4), the front side of the inner pin (4) extends to the side of the chip (5), and the front side of the chip (5) is connected to the inner pin ( 4) The fronts are connected by metal wires (6), the inner pins (4), chips (5) and metal wires (6) are encapsulated with plastic encapsulant (7), the outer base island (1) and Solder balls (9) are arranged on the back of the outer pins (2). The beneficial effect of the invention is that it omits the operation process of double-sided etching of the metal substrate, reduces the cost of the process operation, and realizes the high-density capability of the inner pins because the inner pins are formed by multi-layer electroplating.

Figure 201110378797

Description

Basic island ball grid array package structure and manufacture method thereof are arranged
Technical field
The present invention relates to a kind of have basic island ball grid array package structure and manufacture method thereof, belong to the semiconductor packaging field.
Background technology
Traditional lead frame structure mainly contains two kinds:
First kind: after adopting metal substrate to carry out chemical etching and plating, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in figure 49) that to carry out encapsulation process;
Second kind: adopt metal substrate at first to carry out chemistry at the back side of metal substrate and etch partially, again plastic packaging material being carried out in the aforementioned zone that has etched partially through chemistry seals, the chemistry of pin etches partially in afterwards the front of metal substrate being carried out, carry out the plating work on pin surface in the lead frame after finishing again, namely finish the making (shown in Figure 51) of lead frame.
And there has been following not enough point in above-mentioned two kinds of lead frames in encapsulation process:
First kind:
1) but, the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side, so directly increased high cost;
2) but, also because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, so the load technology in encapsulation process can only be used conduction or non-conductive bonding material, and the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation;
3) but, again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and in the metal wire bonding technology in encapsulation process, because but the glued membrane of this high temperature resistance is soft materials, so caused the instability of metal wire bonding parameter, seriously influenced the quality of metal wire bonding and the stability of production reliability;
4) but, again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and the plastic package process process in encapsulation process, infiltrate plastic packaging material because the injecting glue pressure during plastic packaging is easy to cause between lead frame and the glued membrane, and be that the kenel of conduction is because infiltrated plastic packaging material and become insulation pin (as shown in figure 50) on the contrary with the former metal leg that should belong to.
Second kind:
1), because carried out the etching operation of secondary respectively, so increased the cost of operation operation more;
2), the composition of lead frame be metallics add epoxy resin material (plastic packaging material) thus under the operational environment of high temperature and low temperature easily because the expansion of different material and shrinkage stress inequality, generation lead frame warpage issues;
3) thereby, also because the warpage of lead frame directly has influence on the precision of the device chip in the packaging process and the smooth and easy influence production yield of lead frame transport process;
4) thereby, also because the warpage of lead frame directly has influence on the aligning accuracy of the metal wire bonding in the packaging process and the smooth and easy influence production yield of lead frame transport process;
5), because the interior pin in lead frame front is to adopt etched technology, must be greater than 100 μ m so the pin of pin is wide in the etching, and the gap of interior pin and interior pin also must be greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
In order to address the above problem, the applicant in first to file name be called the patent of invention of " base island lead frame structure and production method thereof are arranged ", its application number is 20101027029.9, it has following beneficial effect:
1) but, the back side of this kind lead frame need not stick the glued membrane of the high temperature resistance of one deck costliness, so directly reduced high cost;
2) but, because the back side of this kind lead frame does not need to stick the glued membrane of one deck high temperature resistance yet, so the technology in encapsulation process is except using conduction or nonconducting resin technology, can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable kind is wider;
3) but, again because the back side of the lead frame of this kind does not need to stick the glued membrane of one deck high temperature resistance, guaranteed the stability of ball bonding bonding parameter, guaranteed the stability of the reliability of the quality of ball bonding and product;
4) but, again because the back side of the lead frame of this kind does not need to stick the glued membrane of one deck high temperature resistance, thereby in the technical process of encapsulation, can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material;
5), plastic packaging material is set in the zone between described metal leg (pin) and metal leg (pin), this plastic packaging material plastic packaging material in the plastic packaging process envelopes the height of whole metal leg, so the constraint ability of plastic-sealed body and metal leg just becomes big, do not have the problem that produces pin again;
6), owing to used plating mode and the back etched technology of positive interior pin, so the pin in lead frame front can be extended to as much as possible the next door of Ji Dao, impel chip and pin distance significantly to shorten, so the cost of metal wire also can significantly reduce (the especially metal wire of Ang Gui proof gold matter);
7), also because the shortening of metal wire makes the also speedup (especially the product of storage class and need the calculating of mass data more outstanding) significantly of signal output speed of chip, because the length of metal wire has shortened, so also significantly reduce in the interference to signal of the existing dead resistance of metal wire, parasitic capacitance and stray inductance;
8), because having used the plating elongation technology of interior pin, so can be easy to produce the distance between high pin number and highdensity pin and the pin, make volume and the area of encapsulation significantly to dwindle;
9), because volume after being encapsulated is significantly dwindled, the more direct material cost that embodies significantly descends, because the minimizing of material usage has also reduced environmental issue puzzlements such as discarded object significantly.
But, still have following deficiency: after at first metal substrate carries out two-sided etching operation, follow-uply also to carry out the etching operation second time, therefore increase the cost of operation operation, also more serious to the pollution of environment; What the interior pin in lead frame front adopted in addition is etching technique, must be greater than 100 μ m so the pin of pin is wide in the etching, and the gap between interior pin and the interior pin is also greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
Summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, a kind of have basic island ball grid array package structure and manufacture method thereof are provided, it has saved the two-sided etched flow chart of metal substrate, reduced the cost of operation operation, and because interior pin adopts the multilayer plating mode to form, therefore realized the high density ability of interior pin.
The object of the present invention is achieved like this: a kind of have a basic island ball grid array package structure, be characterized in: it comprises outer Ji Dao and outer pin, described outer front, basic island is provided with chip, described outer pin front forms interior pin by the multilayer plating mode, the pin front extends to the chip next door in described, be connected with metal wire between described chip front side and the interior pin front, pin in described, chip and metal wire are encapsulated with plastic packaging material outward, the zone of described outer Ji Dao and outer pin periphery, zone between outer Ji Dao and the outer pin and the zone between outer pin and the outer pin are equipped with gap filler, and expose outside the gap filler at the back side of outer Ji Dao and outer pin, the outer Ji Dao outside exposing gap filler with outside the back side of pin be provided with the tin ball.
The present invention has the manufacture method of basic island ball grid array package structure, and described method comprises following processing step:
Step 1, get metal substrate
Step 2, pad pasting operation
Utilize film sticking equipment to stick the photoresist film that can carry out exposure imaging respectively at front and the back side of metal substrate,
Step 3, the positive photoresist film of removing the part figure of metal substrate
The metal substrate front that utilizes exposure imaging equipment that step 2 is finished the pad pasting operation carry out figure exposure, develop and the photoresist film of removing the part figure, exposing the regional graphics that the follow-up needs in metal substrate front are electroplated,
Step 4, plating the first metal layer
Form the first metal layer by the multilayer plating mode in the zone to the photoresist film of metal substrate front removal part figure in the step 3,
Step 5, metal substrate front and back side striping operation
The photoresist film of metal substrate front and back side remainder is removed, pin in the positive formation relatively of metal substrate,
Step 6, load routing
The implantation of chip is carried out by conduction or non-conductive bonding material in metal substrate front between the interior pin that step 5 forms, and carries out the operation of bonding metal wire between chip front side and interior pin front,
Step 7, seal
Utilize the plastic packaging material injection device, chip is implanted and the metal substrate of bonding metal wire operation is sealed the plastic packaging material operation with finishing, and carries out the curing operation after plastic packaging material is sealed,
Step 8, pad pasting operation
Utilize film sticking equipment finish seal and the metal substrate of curing operation in the front and the back side stick the photoresist film that can carry out exposure imaging respectively,
The photoresist film of part figure is removed at step 9, the metal substrate back side
The exposure of figure, the photoresist film with removal part figure of developing are carried out in the metal substrate back side that utilizes exposure imaging equipment that step 8 is finished the pad pasting operation, carry out etched regional graphics to expose the follow-up needs in the metal substrate back side,
Step 10, the metal substrate back side are carried out total eclipse and are carved or etch partially
Total eclipse is carried out in the zone of metal substrate back side removal part photoresist film in the step 9 simultaneously carve or etch partially, form the etching area of depression at the metal substrate back side, relative outer Ji Dao and the outer pin of forming of while,
Step 11, metal substrate front and back side striping operation
The photoresist film of metal substrate front and back side remainder is removed,
Gap filler is filled in step 12, metal substrate back etched zone
In the etching area at the described metal substrate back side, fill gap filler, and carry out the curing operation after gap filler is sealed,
The microetch operation is carried out at step 13, outer Ji Dao and the outer pin back side
Externally microetch is carried out in Ji Dao and zone, the outer pin back side, forms the microetch zone of depression at the metal substrate back side,
Step 14, formation tin ball
Carry out Reflow Soldering again insert tin glue in microetch zone, the metal substrate back side after, Ji Dao and the outer pin back side form the tin ball outside,
Step 15, cutting finished product
Completing steps 14 is finished the semi-finished product that form the tin ball carry out cutting operation, make to integrate in array aggregate mode originally and to contain more than cuttings of plastic-sealed body module of chip independent, made basic island ball grid array package structure finished product.
Compared with prior art, the invention has the beneficial effects as follows:
1, it has saved the two-sided and etching flow chart of secondary respectively of metal substrate, has reduced cost, time, personnel, power, the material of operation operation, has also reduced in the etching work procedure issuable harmful substance simultaneously to the pollution of environment;
2, because the fine rule electric plating method has been adopted in the front, so positive pin widths minimum can reach 25 μ m, reach 25 μ m apart from minimum between interior pin and the interior pin, embody the high density ability of the interior pin of lead frame fully.
3, has only a kind of material of lead frame during the load routing, in using the processing procedure process of superhigh temperature 380 and 420 degrees centigrade, because the expansion that the difference that does not have the multiple material coefficient of expansion is brought is impacted with contraction, guarantee superhigh temperature resistant (generally being below the 200 ℃) performance of lead frame, can should not be out of shape the warpage issues that produces lead frame because of elevated temperature heat.
4, when the plastic-sealed body paster is to the pcb board, because implanting or be coated with the tin ball in the position at plastic-sealed body pin and Ji Dao, it is big that spacing between the plastic-sealed body back side and the pcb board becomes, and especially the problem that causes tin fusion difficulty can not blown because of hot blast in the inner ring pin of plastic-sealed body or zone, basic island.
When if 5 plastic-sealed body pasters are not fine to the pcb board, need do over again again and heavily paste, because there are enough height at the tin cream place, cleaning agent cleans easily, maintenance easily behind the tin ball of burn-oning does not weld to take away as the tin ball and welds a ball again again behind the tin ball and get final product.
Description of drawings
Each operation schematic diagram of Fig. 1 ~ Figure 16 basic island ball grid array package structure embodiment 1 manufacture method for the present invention has.
The structural representation of Figure 17 (A) basic island ball grid array package structure embodiment 1 for the present invention has.
Figure 17 (B) is the vertical view of Figure 17 (A).
The structural representation of Figure 18 (A) basic island ball grid array package structure embodiment 2 for the present invention has.
Figure 18 (B) is the vertical view of Figure 18 (A).
The structural representation of Figure 19 (A) basic island ball grid array package structure embodiment 3 for the present invention has.
Figure 19 (B) is the vertical view of Figure 19 (A).
The structural representation of Figure 20 (A) basic island ball grid array package structure embodiment 4 for the present invention has.
Figure 20 (B) is the vertical view of Figure 21 (A).
The structural representation of Figure 21 (A) basic island ball grid array package structure embodiment 5 for the present invention has.
Figure 21 (B) is the vertical view of Figure 21 (A).
The structural representation of Figure 22 (A) basic island ball grid array package structure embodiment 6 for the present invention has.
Figure 22 (B) is the vertical view of Figure 22 (A).
The structural representation of Figure 23 (A) basic island ball grid array package structure embodiment 7 for the present invention has.
Figure 23 (B) is the vertical view of Figure 23 (A).
The structural representation of Figure 24 (A) basic island ball grid array package structure embodiment 8 for the present invention has.
Figure 24 (B) is the vertical view of Figure 24 (A).
The structural representation of Figure 25 (A) basic island ball grid array package structure embodiment 9 for the present invention has.
Figure 25 (B) is the vertical view of Figure 25 (A).
The structural representation of Figure 26 (A) basic island ball grid array package structure embodiment 10 for the present invention has.
Figure 26 (B) is the vertical view of Figure 26 (A).
The structural representation of Figure 27 (A) basic island ball grid array package structure embodiment 11 for the present invention has.
Figure 27 (B) is the vertical view of Figure 27 (A).
The structural representation of Figure 28 (A) basic island ball grid array package structure embodiment 12 for the present invention has.
Figure 28 (B) is the vertical view of Figure 28 (A).
The structural representation of Figure 29 (A) basic island ball grid array package structure embodiment 13 for the present invention has.
Figure 29 (B) is the vertical view of Figure 29 (A).
The structural representation of Figure 30 (A) basic island ball grid array package structure embodiment 14 for the present invention has.
Figure 30 (B) is the vertical view of Figure 30 (A).
The structural representation of Figure 31 (A) basic island ball grid array package structure embodiment 15 for the present invention has.
Figure 31 (B) is the vertical view of Figure 31 (A).
The structural representation of Figure 32 (A) basic island ball grid array package structure embodiment 16 for the present invention has.
Figure 32 (B) is the vertical view of Figure 32 (A).
The structural representation of Figure 33 (A) basic island ball grid array package structure embodiment 17 for the present invention has.
Figure 33 (B) is the vertical view of Figure 33 (A).
The structural representation of Figure 34 (A) basic island ball grid array package structure embodiment 18 for the present invention has.
Figure 34 (B) is the vertical view of Figure 34 (A).
The structural representation of Figure 35 (A) basic island ball grid array package structure embodiment 19 for the present invention has.
Figure 35 (B) is the vertical view of Figure 35 (A).
The structural representation of Figure 36 (A) basic island ball grid array package structure embodiment 20 for the present invention has.
Figure 36 (B) is the vertical view of Figure 36 (A).
The structural representation of Figure 37 (A) basic island ball grid array package structure embodiment 21 for the present invention has.
Figure 37 (B) is the vertical view of Figure 37 (A).
The structural representation of Figure 38 (A) basic island ball grid array package structure embodiment 22 for the present invention has.
Figure 38 (B) is the vertical view of Figure 38 (A).
The structural representation of Figure 39 (A) basic island ball grid array package structure embodiment 23 for the present invention has.
Figure 39 (B) is the vertical view of Figure 39 (A).
The structural representation of Figure 40 (A) basic island ball grid array package structure embodiment 24 for the present invention has.
Figure 40 (B) is the vertical view of Figure 40 (A).
The structural representation of Figure 41 (A) basic island ball grid array package structure embodiment 25 for the present invention has.
Figure 41 (B) is the vertical view of Figure 41 (A).
The structural representation of Figure 42 (A) basic island ball grid array package structure embodiment 26 for the present invention has.
Figure 42 (B) is the vertical view of Figure 42 (A).
The structural representation of Figure 43 (A) basic island ball grid array package structure embodiment 27 for the present invention has.
Figure 43 (B) is the vertical view of Figure 43 (A).
The structural representation of Figure 44 (A) basic island ball grid array package structure embodiment 28 for the present invention has.
Figure 44 (B) is the vertical view of Figure 44 (A).
The structural representation of Figure 45 (A) basic island ball grid array package structure embodiment 29 for the present invention has.
Figure 45 (B) is the vertical view of Figure 45 (A).
The structural representation of Figure 46 (A) basic island ball grid array package structure embodiment 30 for the present invention has.
Figure 46 (B) is the vertical view of Figure 46 (A).
The structural representation of Figure 47 (A) basic island ball grid array package structure embodiment 31 for the present invention has.
Figure 47 (B) is the vertical view of Figure 47 (A).
The structural representation of Figure 48 (A) basic island ball grid array package structure embodiment 32 for the present invention has.
Figure 48 (B) is the vertical view of Figure 48 (A).
Figure 49 was not for there was the schematic diagram that high temperature resistant glued membrane is sticked at the pin lead frame back side on four sides in the past.
The schematic diagram of flash when the four sides that Figure 50 sticks high temperature resistant glued membrane for the back side does not in the past have the pin leadframe package.
Figure 51 was for sealed the structural representation of two-sided etched lead frame in advance in the past.
Wherein:
Outer basic island 1, outer pin 2, interior basic island 3, interior pin 4, chip 5, metal wire 6, plastic packaging material 7, conduction or non-conductive bonding material 8, tin ball 9, gap filler 10, metal substrate 11, photoresist film 12 or 13, the first metal layer 14, passive device 15, outer static release ring 16, interior static release ring 17.
Embodiment
The present invention has basic island ball grid array package structure and manufacture method thereof as follows:
Embodiment 1: single basic island individual pen pin (Ji Dao in not having)
Referring to Figure 17 (A) and 17(B), Figure 17 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 1.Figure 17 (B) is the vertical view of Figure 17 (A).By Figure 17 (A) and Figure 17 (B) as can be seen, the present invention has basic island ball grid array package structure, it comprises outer basic island 1 and outer pin 2, described outer 1 front, basic island is provided with chip 5 by conduction or non-conductive bonding material 8, pin 4 in described outer pin 2 fronts form by the multilayer plating mode, pin 4 is referred to as the first metal layer 14 in described, pin 4 fronts extend to chip 5 next doors in described, described chip 5 positive with interior pin 4 fronts between be connected with metal wire 6, pin 4 in described, chip 5 and the metal wire 6 outer plastic packaging materials 7 that are encapsulated with, the zone of described outer basic island 1 and outer pin 2 peripheries, zone between outer basic island 1 and the outer pin 2 and the zone between outer pin 2 and the outer pin 2 are equipped with gap filler 10, and expose outside the gap filler 10 at the back side of outer basic island 1 and outer pin 2, the outer basic island 1 outside exposing gap filler 10 with outside the back side of pin 2 be provided with tin ball 9.
Its manufacture method is as follows
Step 1, get metal substrate
Referring to Fig. 1, get the suitable metal substrate of a slice thickness 11, the material of metal substrate 11 can be carried out conversion according to function and the characteristic of chip, for example: copper, aluminium, iron, copper alloy, stainless steel or dilval etc.
Step 2, pad pasting operation
Referring to Fig. 2; utilize film sticking equipment to stick the photoresist film 12 and 13 that can carry out exposure imaging respectively at front and the back side of metal substrate 11; protecting follow-up electroplated metal layer process operation, so photoresist film can be that the dry lithography glued membrane also can be the wet type photoresist film.
Step 3, the positive part photoresist film of removing of metal substrate
Referring to Fig. 3, part figure photoresist film is carried out graph exposure, develops and removes in metal substrate 11 fronts that utilize exposure imaging equipment that step 2 is finished the pad pasting operation, to expose the figure that metal substrate 11 positive follow-up needs carry out the plating area.
Step 4, plating the first metal layer
Referring to Fig. 4, in step 3, form the first metal layer 14 by the multilayer plating mode in the zone of the photoresist film of metal substrate 11 positive removal part figures, described the first metal layer 14 can adopt and be followed successively by nickel, copper, nickel, palladium, five layers of metal level of gold or nickel, copper, silver-colored three-layer metal layer, perhaps other similar structures from bottom to top.Be example with nickel, copper, Nie, Palladium, five layers of metal level of gold, wherein the ground floor nickel dam mainly plays the effect on anti-etching barrier layer, and middle copper layer, nickel dam He Palladium layer mainly play a part in conjunction with increasing, and outermost gold layer mainly plays the effect with the metal wire bonding.
Step 5, metal substrate front and back side striping operation
Referring to Fig. 5, the photoresist film of metal substrate 11 fronts and back side remainder is removed pin 4 in metal substrate 11 positive formation relatively.
Step 6, load routing
Referring to Fig. 6 ~ Fig. 7, the implantation of chip 5 is carried out by conduction or non-conductive bonding material 8 in metal substrate 11 fronts between the interior pin 4 that step 5 forms, and carries out 6 operations of bonding metal wire between chip 5 fronts and interior pin 4 fronts.
Step 7, seal
Referring to Fig. 8, utilize the plastic packaging material injection device, chip is implanted and the metal substrate 11 of bonding metal wire operation is sealed the plastic packaging material operation with finishing, and carries out plastic packaging material and seal the back curing operation.
Step 8, pad pasting operation
Referring to Fig. 9; utilize film sticking equipment finish seal and curing operation after metal substrate 11 in the front and the back side stick the photoresist film 12 and 13 that can carry out exposure imaging respectively; protecting follow-up etch process operation, so photoresist film can be that the dry lithography glued membrane also can be the wet type photoresist film.
The photoresist film of part figure is removed at step 9, the metal substrate back side
Referring to Figure 10, the exposure of figure, the photoresist film with removal part figure of developing are carried out in metal substrate 11 back sides that utilize exposure imaging equipment that step 8 is finished the pad pasting operation, carry out etched zone to expose the follow-up needs in metal substrate 11 back sides.
Step 10, the metal substrate back side are carried out total eclipse and are carved or etch partially operation
The zone of removing the photoresist film of part figure referring to Figure 11, to the metal substrate back side in the step 9 is carried out total eclipse simultaneously and is carved or etch partially, and forms the etching area of depression at the metal substrate back side, forms outer basic island 1 and outer pin 2 simultaneously relatively.
Step 11, metal substrate front and back side striping operation
Referring to Figure 12, the photoresist film of metal substrate front and back side remainder is removed.
Gap filler is filled in step 12, metal substrate back etched zone
Referring to Figure 13, in the etching area at the described metal substrate back side, utilize pad device to carry out filling gap filler 10, and carry out gap filler 10 fillings or seal after curing operation, described gap filler can be that filler or packless gap filler are arranged.
Microetch is carried out at step 13, outer Ji Dao and the outer pin back side
Referring to Figure 14, externally microetch is carried out in Ji Dao and zone, the outer pin back side, forms the microetch zone of depression at the metal substrate back side.
Step 14, formation tin ball
Referring to Figure 15, carry out Reflow Soldering again after in microetch zone, the metal substrate back side, inserting tin glue, the tin of Ji Dao and outer pin back side formation outside ball 9.
Step 15, cutting finished product
Referring to Figure 16, step 14 is finished the semi-finished product that form the tin ball carry out cutting operation, make to integrate in array aggregate mode originally and to contain more than cuttings of plastic-sealed body module of chip independent, made basic island ball grid array package structure finished product.
Embodiment 2: single basic island individual pen pin (interior Ji Dao is arranged)
Referring to Figure 18 (A) and Figure 18 (B), Figure 18 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 2.Figure 18 (B) is the vertical view of Figure 18 (A).By Figure 18 (A) and Figure 18 (B) as can be seen, embodiment 2 only is with the difference of embodiment 1: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 3: single basic island individual pen pin passive device (Ji Dao in not having)
Referring to Figure 19 (A) and Figure 19 (B), Figure 19 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 3.Figure 19 (B) is the vertical view of Figure 19 (A).By Figure 19 (A) and Figure 19 (B) as can be seen, the difference of embodiment 3 and embodiment 1 only is: in described between pin 4 and the interior pin 4 by conducting electricity or 8 cross-over connections of non-conductive bonding material have passive device 15.
Embodiment 4: single basic island individual pen pin passive device (interior Ji Dao is arranged)
Referring to Figure 20 (A) and Figure 20 (B), Figure 20 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 4.Figure 20 (B) is the vertical view of Figure 20 (A).By Figure 20 (A) and Figure 20 (B) as can be seen, embodiment 4 only is with the difference of embodiment 3: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 5: single basic island individual pen pin static release ring (Ji Dao in not having)
Referring to Figure 21 (A) and Figure 21 (B), Figure 21 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 5.Figure 21 (B) is the vertical view of Figure 21 (A).By Figure 21 (A) and Figure 21 (B) as can be seen, the difference of embodiment 5 and embodiment 1 only is: be provided with outer static release ring 16 between described outer basic island 1 and the outer pin 2, static release ring 17 in described outer static release ring 16 fronts form by the multilayer plating mode, described in static release ring 17 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 6: single basic island individual pen pin static release ring (interior Ji Dao is arranged)
Referring to Figure 22 (A) and Figure 22 (B), Figure 22 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 6.Figure 22 (B) is the vertical view of Figure 22 (A).By Figure 22 (A) and Figure 22 (B) as can be seen, embodiment 6 only is with the difference of embodiment 5: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 7: single basic island individual pen pin static release ring passive device (Ji Dao in not having)
Referring to Figure 23 (A) and Figure 23 (B), Figure 23 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 7.Figure 23 (B) is the vertical view of Figure 23 (A).By Figure 23 (A) and Figure 23 (B) as can be seen, the difference of embodiment 7 and embodiment 5 only is: in described between pin 4 and the interior pin 4 by conducting electricity or 8 cross-over connections of non-conductive bonding material have passive device 15.
Embodiment 8: single basic island individual pen pin static release ring passive device (interior Ji Dao is arranged)
Referring to Figure 24 (A) and Figure 24 (B), Figure 24 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 8.Figure 24 (B) is the vertical view of Figure 24 (A).By Figure 24 (A) and Figure 24 (B) as can be seen, embodiment 8 only is with the difference of embodiment 7: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 9: single basic island multi-turn pin (Ji Dao in not having)
Referring to Figure 25 (A) and Figure 25 (B), Figure 25 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 9.Figure 25 (B) is the vertical view of Figure 25 (A).By Figure 25 (A) and Figure 25 (B) as can be seen, embodiment 9 only is with the difference of embodiment 1: described outer pin 2 has multi-turn, and outer pin 2 fronts of described multi-turn form interior pin 4 by the multilayer plating mode.
Embodiment 10: single basic island multi-turn pin (interior Ji Dao is arranged)
Referring to Figure 26 (A) and Figure 26 (B), Figure 26 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 10.Figure 26 (B) is the vertical view of Figure 26 (A).By Figure 26 (A) and Figure 26 (B) as can be seen, embodiment 10 only is with the difference of embodiment 9: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 11: single basic island multi-turn pin passive device (Ji Dao in not having)
Referring to Figure 27 (A) and Figure 27 (B), Figure 27 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 11.Figure 27 (B) is the vertical view of Figure 27 (A).By Figure 27 (A) and Figure 27 (B) as can be seen, the difference of embodiment 11 and embodiment 9 only is: in described between pin 4 and the interior pin 4 by conducting electricity or 8 cross-over connections of non-conductive bonding material have passive device 15.
Embodiment 12: single basic island multi-turn pin passive device (interior Ji Dao is arranged)
Referring to Figure 28 (A) and Figure 28 (B), Figure 28 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 12.Figure 28 (B) is the vertical view of Figure 28 (A).By Figure 28 (A) and Figure 28 (B) as can be seen, embodiment 12 only is with the difference of embodiment 11: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 13: single basic island multi-turn pin static release ring (Ji Dao in not having)
Referring to Figure 29 (A) and Figure 29 (B), Figure 29 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 13.Figure 29 (B) is the vertical view of Figure 29 (A).By Figure 29 (A) and Figure 29 (B) as can be seen, the difference of embodiment 13 and embodiment 9 only is: be provided with outer static release ring 16 between described outer basic island 1 and the outer pin 2, static release ring 17 in described outer static release ring 16 fronts form by the multilayer plating mode, described in static release ring 17 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 14: single basic island multi-turn pin static release ring (interior Ji Dao is arranged)
Referring to Figure 30 (A) and Figure 30 (B), Figure 30 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 14.Figure 30 (B) is the vertical view of Figure 30 (A).By Figure 30 (A) and Figure 30 (B) as can be seen, embodiment 14 only is with the difference of embodiment 13: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 15: single basic island multi-turn pin static release ring passive device (Ji Dao in not having)
Referring to Figure 31 (A) and Figure 31 (B), Figure 31 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 15.Figure 31 (B) is the vertical view of Figure 31 (A).By Figure 31 (A) and Figure 31 (B) as can be seen, the difference of embodiment 15 and embodiment 13 only is: in described between pin 4 and the interior pin 4 by conducting electricity or 8 cross-over connections of non-conductive bonding material have passive device 15.
Embodiment 16: single basic island multi-turn pin static release ring passive device (interior Ji Dao is arranged)
Referring to Figure 32 (A) and Figure 32 (B), Figure 32 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 16.Figure 32 (B) is the vertical view of Figure 32 (A).By Figure 32 (A) and Figure 32 (B) as can be seen, embodiment 16 only is with the difference of embodiment 15: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 17: how basic island individual pen pin (Ji Dao in not having)
Referring to Figure 33 (A) and Figure 33 (B), Figure 33 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 17.Figure 33 (B) is the vertical view of Figure 33 (A).By Figure 33 (A) and Figure 33 (B) as can be seen, embodiment 17 only is with the difference of embodiment 1: described outer basic island 1 has a plurality of, described a plurality of outer 1 front, basic island all is provided with chip 5 by conduction or non-conductive bonding material 8, described chip 5 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 18: how basic island individual pen pin (interior Ji Dao is arranged)
Referring to Figure 34 (A) and Figure 34 (B), Figure 34 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 18.Figure 34 (B) is the vertical view of Figure 34 (A).By Figure 34 (A) and Figure 34 (B) as can be seen, embodiment 18 only is with the difference of embodiment 17: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 19: how basic island individual pen pin passive device (Ji Dao in not having)
Referring to Figure 35 (A) and Figure 35 (B), Figure 35 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 19.Figure 35 (B) is the vertical view of Figure 35 (A).By Figure 35 (A) and Figure 35 (B) as can be seen, embodiment 19 only is with the difference of embodiment 3: described outer basic island 1 has a plurality of, described a plurality of outer 1 front, basic island all is provided with chip 5 by conduction or non-conductive bonding material 8, described chip 5 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 20: how basic island individual pen pin passive device (interior Ji Dao is arranged)
Referring to Figure 36 (A) and Figure 36 (B), Figure 36 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 20.Figure 36 (B) is the vertical view of Figure 36 (A).By Figure 36 (A) and Figure 36 (B) as can be seen, embodiment 20 only is with the difference of embodiment 19: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 21: how basic island individual pen pin static release ring (Ji Dao in not having)
Referring to Figure 37 (A) and Figure 37 (B), Figure 37 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 21.Figure 37 (B) is the vertical view of Figure 37 (A).By Figure 37 (A) and Figure 37 (B) as can be seen, embodiment 21 only is with the difference of embodiment 5: described outer basic island 1 has a plurality of, described a plurality of outer 1 front, basic island all is provided with chip 5 by conduction or non-conductive bonding material 8, described chip 5 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 22: how basic island individual pen pin static release ring (interior Ji Dao is arranged)
Referring to Figure 38 (A) and Figure 38 (B), Figure 38 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 22.Figure 38 (B) is the vertical view of Figure 38 (A).By Figure 38 (A) and Figure 38 (B) as can be seen, embodiment 22 is with the difference of embodiment 21: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 23: how basic island individual pen pin static release ring passive device (Ji Dao in not having)
Referring to Figure 39 (A) and Figure 39 (B), Figure 39 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 23.Figure 39 (B) is the vertical view of Figure 39 (A).By Figure 39 (A) and Figure 39 (B) as can be seen, embodiment 23 only is with the difference of embodiment 7: described outer basic island 1 has a plurality of, described a plurality of outer 1 front, basic island all is provided with chip 5 by conduction or non-conductive bonding material 8, described chip 5 positive with chip 5 fronts between be connected by metal wire 6.
Embodiment 24: how basic island individual pen pin static release ring passive device (interior Ji Dao is arranged)
Referring to Figure 40 (A) and Figure 40 (B), Figure 40 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 24.Figure 40 (B) is the vertical view of Figure 40 (A).By Figure 40 (A) and Figure 40 (B) as can be seen, embodiment 24 only is with the difference of embodiment 23: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 25: how basic island multi-turn pin (Ji Dao in not having)
Referring to Figure 41 (A) and Figure 41 (B), Figure 41 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 25.Figure 41 (B) is the vertical view of Figure 41 (A).By Figure 41 (A) and Figure 41 (B) as can be seen, embodiment 25 only is with the difference of embodiment 17: described outer pin 2 has multi-turn, and outer pin 2 fronts of described multi-turn form interior pin 4 by the multilayer plating mode.
Embodiment 26: how basic island multi-turn pin (interior Ji Dao is arranged)
Referring to Figure 42 (A) and Figure 42 (B), Figure 42 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 26.Figure 42 (B) is the vertical view of Figure 42 (A).By Figure 42 (A) and Figure 42 (B) as can be seen, embodiment 26 only is with the difference of embodiment 25: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 27: how basic island multi-turn pin passive device (Ji Dao in not having)
Referring to Figure 43 (A) and Figure 43 (B), Figure 43 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 27.Figure 43 (B) is the vertical view of Figure 43 (A).By Figure 43 (A) and Figure 43 (B) as can be seen, embodiment 27 only is with the difference of embodiment 19: described outer pin 2 has multi-turn, and outer pin 2 fronts of described multi-turn form interior pin 4 by the multilayer plating mode.
Embodiment 28: how basic island multi-turn pin passive device (interior Ji Dao is arranged)
Referring to Figure 44 (A) and Figure 44 (B), Figure 44 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 28.Figure 44 (B) is the vertical view of Figure 44 (A).By Figure 44 (A) and Figure 44 (B) as can be seen, embodiment 28 only is with the difference of embodiment 27: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 29: how basic island multi-turn pin static release ring (Ji Dao in not having)
Referring to Figure 45 (A) and Figure 45 (B), Figure 45 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 29.Figure 45 (B) is the vertical view of Figure 45 (A).By Figure 45 (A) and Figure 45 (B) as can be seen, embodiment 29 is with the difference of embodiment 21: described outer pin 2 has multi-turn, and outer pin 2 fronts of described multi-turn form interior pin 4 by the multilayer plating mode.
Embodiment 30: how basic island multi-turn pin static release ring (interior Ji Dao is arranged)
Referring to Figure 46 (A) and Figure 46 (B), Figure 46 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 30.Figure 46 (B) is the vertical view of Figure 46 (A).By Figure 46 (A) and Figure 46 (B) as can be seen, embodiment 30 is with the difference of embodiment 29: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.
Embodiment 31: how basic island multi-turn pin static release ring passive device (Ji Dao in not having)
Referring to Figure 47 (A) and Figure 47 (B), Figure 47 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 31.Figure 47 (B) is the vertical view of Figure 47 (A).By Figure 47 (A) and Figure 47 (B) as can be seen, embodiment 31 is with the difference of embodiment 23: described outer pin 2 has multi-turn, and outer pin 2 fronts of described multi-turn form interior pin 4 by the multilayer plating mode.
Embodiment 32: how basic island multi-turn pin static release ring passive device (interior Ji Dao is arranged)
Referring to Figure 48 (A) and Figure 48 (B), Figure 48 (A) the present invention has the structural representation of basic island ball grid array package structure embodiment 32.Figure 48 (B) is the vertical view of Figure 48 (A).By Figure 48 (A) and Figure 48 (B) as can be seen, embodiment 32 is with the difference of embodiment 31: the front on described outer basic island 1 forms one or more interior basic islands 3 by the multilayer plating mode, 3 fronts, basic island in chip 5 is arranged at by conduction or non-conductive bonding material 8 at this moment.

Claims (7)

1.一种有基岛球栅阵列封装结构的制造方法，其特征在于所述方法包括以下工艺步骤： 1. A method for manufacturing a base-island ball grid array packaging structure is characterized in that the method comprises the following process steps: 步骤一、取金属基板 Step 1. Take the metal substrate 步骤二、贴膜作业 Step 2, film pasting operation 利用贴膜设备在金属基板的正面及背面分别贴上可进行曝光显影的光刻胶膜， The photoresist film that can be exposed and developed is respectively pasted on the front and back of the metal substrate by using the film sticking equipment. 步骤三、金属基板正面去除部分图形的光刻胶膜 Step 3. Remove the photoresist film of part of the pattern on the front of the metal substrate 利用曝光显影设备将步骤二完成贴膜作业的金属基板正面进行图形的曝光、显影与去除部分图形的光刻胶膜，以露出金属基板正面后续需要进行电镀的区域， Use exposure and developing equipment to expose, develop and remove part of the patterned photoresist film on the front of the metal substrate that has completed the film attachment operation in step 2, so as to expose the area that needs to be electroplated on the front of the metal substrate. 步骤四、电镀第一金属层 Step 4. Plating the first metal layer 对步骤三中金属基板正面去除部分图形的光刻胶膜的区域通过多层电镀方式形成第一金属层， In step 3, the first metal layer is formed by multi-layer electroplating in the region where part of the photoresist film of the pattern is removed from the front of the metal substrate, 步骤五、金属基板正面及背面去膜作业 Step 5. Remove the film from the front and back of the metal substrate 将金属基板正面及背面余下的光刻胶膜去除，在金属基板正面相对形成内引脚， Remove the remaining photoresist film on the front and back of the metal substrate, and form inner leads on the front of the metal substrate. 步骤六、装片打线 Step 6, film loading and wiring 在步骤五形成的内引脚之间的金属基板正面通过导电或不导电粘结物质进行芯片的植入，以及在芯片正面与内引脚正面之间进行键合金属线作业， The front side of the metal substrate between the inner pins formed in step five is implanted with a conductive or non-conductive adhesive substance, and the bonding metal wire operation is performed between the front side of the chip and the front side of the inner pins, 步骤七、包封 Step 7. Encapsulation 利用塑封料注入设备，将已完成芯片植入以及键合金属线作业的金属基板进行包封塑封料作业，并进行塑封料包封后的固化作业， Using the molding compound injection equipment, the metal substrate that has completed the chip implantation and bonding metal wire operations is encapsulated with the plastic compound, and the curing operation is performed after the plastic compound is encapsulated. 步骤八、贴膜作业 Step 8, film pasting operation 利用贴膜设备在完成包封以及固化作业的金属基板的正面及背面分别贴上可进行曝光显影的光刻胶膜， Use film laminating equipment to paste photoresist films that can be exposed and developed on the front and back of the metal substrate that has completed the encapsulation and curing operations, 步骤九、金属基板背面去除部分图形的光刻胶膜 Step 9. Remove part of the patterned photoresist film on the back of the metal substrate 利用曝光显影设备将步骤八完成贴膜作业的金属基板背面进行图形的曝光、显影与去除部分图形的光刻胶膜，以露出金属基板背面后续需要进行蚀刻的区域， Use exposure and development equipment to expose, develop and remove part of the patterned photoresist film on the back of the metal substrate that has completed the film attachment operation in step 8, so as to expose the area that needs to be etched later on the back of the metal substrate. 步骤十、金属基板背面进行全蚀刻或半蚀刻作业 Step 10. Perform full etching or half etching on the back of the metal substrate 对步骤九中金属基板背面去除部分光刻胶膜的图形区域同时进行全蚀刻或半蚀刻，在金属基板背面形成凹陷的蚀刻区域，同时相对形成外基岛和外引脚， Perform full etching or half etching at the same time on the graphic area where part of the photoresist film is removed on the back of the metal substrate in step 9 to form a recessed etching area on the back of the metal substrate, and at the same time relatively form the outer base island and outer pins, 步骤十一、金属基板正面及背面去膜作业 Step 11. Remove the film on the front and back of the metal substrate 将金属基板正面及背面余下的光刻胶膜去除， Remove the remaining photoresist film on the front and back of the metal substrate, 步骤十二、金属基板背面蚀刻区域填充填缝剂 Step 12. Fill the etched area on the back of the metal substrate with caulking agent 在所述金属基板背面的蚀刻区域内利用填充的设备进行充填填缝剂，并进行填缝剂充填或包封后的固化作业， filling the etched area on the back of the metal substrate with filling equipment, and performing the curing operation after the filling or encapsulation of the caulking agent, 步骤十三、外基岛和外引脚背面进行微蚀刻 Step 13. Micro-etching on the back of the outer base island and outer pins 对外基岛和外引脚背面区域进行微蚀刻，在金属基板背面形成凹陷的微蚀刻区域， Microetch the outer base island and the backside of the outer pins to form a recessed microetched area on the backside of the metal substrate, 步骤十四、形成锡球 Step 14, forming solder balls 在金属基板背面微蚀刻区域内填入锡胶后再进行回流焊，在外基岛和外引脚背面形成锡球， Fill the micro-etching area on the back of the metal substrate with tin glue and then perform reflow soldering to form solder balls on the back of the outer base island and the outer pins. 步骤十五、切割成品 Step 15. Cutting the finished product 将已完成步骤十四完成形成锡球的半成品进行切割作业，使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来，制得有基岛球栅阵列封装结构成品。 Cutting the semi-finished products that have completed step 14 and formed solder balls, so that the plastic package modules that were originally integrated in the form of an array assembly and containing chips are cut and separated one by one, and a ball grid array with base islands is obtained. Finished packaging structure. 2.根据权利要求1所述的有基岛球栅阵列封装结构的制造方法，其特征在于：所述外基岛（1）的正面通过多层电镀方式形成一个或多个内基岛（3），所述芯片（5）通过导电或不导电粘结物质（8）设置于内基岛（3）正面。 2. The manufacturing method of a ball grid array package structure with base islands according to claim 1, characterized in that: one or more inner base islands (3 ), the chip (5) is arranged on the front surface of the inner base island (3) through a conductive or non-conductive adhesive substance (8). 3.根据权利要求1所述的有基岛球栅阵列封装结构的制造方法，其特征在于：所述内引脚（4）与内引脚（4）之间通过导电或不导电粘结物质（8）跨接有无源器件（15）。 3. The manufacturing method of the island-based ball grid array package structure according to claim 1, characterized in that: the inner pin (4) is connected to the inner pin (4) through a conductive or non-conductive adhesive substance (8) Passive devices (15) are connected across. 4.根据权利要求1所述的有基岛球栅阵列封装结构的制造方法，其特征在于：所述外基岛（1）与外引脚（2）之间设置有外静电释放圈（16），所述外静电释放圈（16）正面通过多层电镀方式形成内静电释放圈（17），所述内静电释放圈（17）正面与芯片（5）正面之间通过金属线（6）连接。 4. The manufacturing method of a ball grid array package structure with base island according to claim 1, characterized in that: an outer electrostatic discharge ring (16) is arranged between the outer base island (1) and the outer pin (2) ), the front of the outer electrostatic release ring (16) forms an inner electrostatic discharge ring (17) through multi-layer electroplating, and a metal wire (6) passes between the front of the inner electrostatic discharge ring (17) and the front of the chip (5) connect. 5.根据权利要求1~4其中之一所述的有基岛球栅阵列封装结构的制造方法，其特征在于：所述外基岛（1）有单个，所述外引脚（2）有多圈。 5. The method for manufacturing a ball grid array package structure with base islands according to any one of claims 1 to 4, characterized in that: the outer base island (1) has a single one, and the outer pins (2) have Multiple laps. 6.根据权利要求1~4其中之一所述的有基岛球栅阵列封装结构的制造方法，其特征在于：所述外基岛（1）有多个，所述外引脚（2）有单圈。 6. The method for manufacturing a ball grid array package structure with base islands according to any one of claims 1 to 4, characterized in that: there are multiple outer base islands (1), and the outer pins (2) There are laps. 7.根据权利要求1~4其中之一所述的有基岛球栅阵列封装结构的制造方法，其特征在于：所述外基岛（1）有多个，所述外引脚（2）有多圈。 7. The method for manufacturing a ball grid array package structure with base islands according to any one of claims 1 to 4, characterized in that: there are multiple outer base islands (1), and the outer pins (2) There are multiple turns.
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