CN102779480A - Display screen drive circuit and light-emitting diode display device - Google Patents
Display screen drive circuit and light-emitting diode display device Download PDFInfo
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Abstract
The invention discloses a display screen drive circuit which comprises a signal input unit, a data processing and shifting register, a data register, a state register, a counter and a pulse width modulation signal generating unit, wherein the signal input unit is used for inputting a serial data input signal, a gray scale clock signal, a data clock signal and a data control signal; the data processing and shifting register is used for responding the data clock signal and the data control signal and obtaining serial gray scale data and serial state data from the serial data input signal; the data register is used for receiving the serial gray scale data signal; the stage register is used for storing a preset state data and receiving the serial state data; the counter is used for generating a counting value according to the preset state data, the serial state data and the gray scale clock signal; and the pulse width modulation signal generating unit is used for generating a plurality of pulse width modulation signals according to the serial gray scale data obtained from the data register and the counting value of the counter, and outputting the pulse width modulation signals. The invention also provides a light emitting diode display device adopting the display screen drive circuit so that the high refreshing efficiency is realized.
Description
Technical field
The present invention relates to display and drive the field, relate in particular to a kind of display drive circuit and use the light emitting display device of said display drive circuit.
Background technology
Light emitting diode (LED) display screen extensively is used in places such as stadiums, square, building in recent years, in actual use, the situation that scanning ripple and image gray-scale level are lost occurs through regular meeting, can't satisfy the needs of high-end market.For this reason, to occur be the inevitable requirement of market and development in science and technology to the light emitting diode (LED) display screen drive system of high refresh rate.
In general, about per second 30 width of cloth or higher moving image can be thought continuously by human eye, that is to say that human eye under the worst condition only needs the refresh rate of 30Hz.Higher refresh rate can make image more show continuously with stable, if reach the above refresh rate of per second 50Hz, human eye is with regard to imperceptible tangible difference.But in the practical application, for the removal of images flicker, the refreshing frequency of full color display should be not less than 240Hz generally speaking out of doors; Brightness surpasses 4000cd/m
2The refresh rate of full color display should be not less than 400Hz; For the image of high brightness more, the refreshing frequency of display screen will reach 800-1000Hz.
In traditional light emitting diode (LED) display screen drive system; The frequency of GTG clock signal input GCLK is under the situation of 20MHz; If light emitting diode (LED) display screen is applied in the static screen system; If chip for driving is the controls of 16 rank pulse-length modulation GTGs, then the refresh rate of light emitting diode (LED) display screen is about 305Hz; If be applied in the dynamic screen of 1/8 line scanning, then the refresh rate of light emitting diode (LED) display screen is about 38Hz.
In order to improve the refresh rate of light emitting diode (LED) display screen, some chip design producers are cut apart the pulse width modulating signal of chip for driving, with the pulse-length modulation GTG signal on 16 rank, are divided into the pulse width modulating signal on 64 10 rank.Carried out such improvement, in the static state screen was used, the refresh rate of light emitting diode (LED) display screen can be brought up to and be about 19531Hz.Yet, nonetheless, if said method is applied in the screen of 1/8 line scanning; Then can only in the sweep time of oneself, just understand open circuit because of light emitting diode, just, after other 7 row are accomplished 16 rank images; Just can be lighted once more, therefore can't be improved the refresh rate of dynamic screen.
Summary of the invention
In order to solve the problems of the technologies described above the light emitting display device that the embodiment of the invention provides a kind of display drive circuit and adopts said display drive circuit.
According to one embodiment of the invention, a kind of display drive circuit is provided, said display drive circuit comprises: signal input unit is used for input serial data input signal, GTG clock signal, data clock signal and data controlling signal; Data processing and shift register are coupled to said signal input unit, are used to respond said data clock signal and data controlling signal and obtain serial luma data and serial status data from said input serial data signal; Data register is coupled to said data processing and shift register, is used to receive said serial luma data signal; Status register is coupled to said data processing and shift register, is used to store a predetermined status data and receives said serial status data; Counter is coupled to said status register, is used for producing a count value according to said predetermined status data, said serial status data and said GTG clock signal; And the pulse width modulating signal generation unit, be coupled to said data register and said counter, be used for count value according to the serial luma data sum counter that obtains from said data register, produce a plurality of pulse width modulating signals and output.
Wherein, the pulse width modulating signal generation unit is divided into 2 with the serial luma data
LThe pulse width modulating signal on individual H rank, wherein, the high-order exponent number of H indicating impulse bandwidth modulation signals, the low order exponent number of L indicating impulse bandwidth modulation signals.
Wherein, said counter is according to formula: (2
H* T
GCLK+ T) * S * 2
LCalculating has the time of dynamic scan needs of complete image completion of S the number of scanning lines, wherein, and the high-order exponent number of H indicating impulse bandwidth modulation signals, the low order exponent number of L indicating impulse bandwidth modulation signals, T
GCLK* 2
HExpression output each by the time of the pulse width modulating signal needs after cutting apart, T representes line scanning switching time, S representes the number of scanning lines.
Wherein, counter carries out when counting scan period to piece image, carries out the first time 2 earlier
HCounting, then at interval (2
H* T
GCLK+ T) * (S-1) time, continue for the second time 2
HCounting, and then one (2 at interval
H* T
GCLK+ T) * (S-1) time ... circulation successively is up to accomplishing 2
L Inferior 2
HCounting.
Wherein, the output time of accomplishing delegation's pulse width modulating signal is more than or equal to the input time of accomplishing next line serial luma data to be scanned.
Wherein, said status register also is used to supply the user to set the state of driving circuit, to obtain said predetermined status data.
Wherein, Said display drive circuit comprises the chip for driving of a plurality of cascades, and each chip for driving comprises said signal input unit, data processing and a shift register, data register, status register, counter and pulse width modulating signal generation unit.
Wherein, Said signal input unit comprises serial data input end, GTG input end of clock, data clock input end and data controlling signal input end, is respectively applied for the said input serial data signal of transmission, GTG clock signal, data clock signal and data controlling signal.
According to another embodiment of the present invention; A kind of light emitting display device is provided; It comprises at least: light emitting diode (LED) display screen and above-mentioned display drive circuit; This display drive circuit is coupled to said light emitting diode (LED) display screen, to drive said light emitting diode (LED) display screen display image.
Wherein, the output of said pulse width modulating signal generation unit is coupled to a constant current output channel, and pulse width modulating signal is input to said light emitting diode (LED) display screen from said constant current output channel.
The present invention is cut apart form because input pulse width modulation luma data has adopted; And the counter of chip for driving produces count value and interval time according to predetermined requirement, and then a width of cloth complete image data of output just can be regarded as the luma data signal of importing is converted into 2
LThe individual pulse width modulating signal of cutting apart group.And each cuts apart the pulse width modulating signal of group, has comprised the pulse width modulating signal from first row to the capable every capable H of S rank, and the time that every row switches is T.Accomplishing time of cutting apart the pulse width modulating signal of group of output like this is (2
H* T
GCLK+ T) * and S, thus can the refresh rate of display screen be promoted about 2
LDoubly.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the high-level schematic functional block diagram of the display drive circuit that provides of the embodiment of the invention;
Fig. 2 is the sequential chart of the input serial data signal (SDI), data clock signal (DCLK) and the data controlling signal (LE) that are used for the display drive circuit of Fig. 1;
Fig. 3 is the synoptic diagram of pulse width modulating signal of the display drive circuit output of Fig. 1;
Fig. 4 is the structured flowchart of light emitting display device of the display drive circuit of employing Fig. 1 of providing of the embodiment of the invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
The display drive circuit that the present invention proposes is applicable to that dynamic display screen and static display screen system are with the driven for emitting lights diode (OLED) display screen.Can't satisfy the problem that under high display precision, obtains higher refresh rate to what prior art existed; The display drive circuit that the embodiment of the invention provides is cut apart the cascade video data of input; And according to the video data after cutting apart; Under the control of count value, generate pulse-length modulation (PWM) signal, thereby can dynamically obtain higher screen refresh rate in the screen scanning system in order to the adjusting display effect.
The functional module structure figure of the display drive circuit 100 that Fig. 1 provides for the embodiment of the invention for the ease of explanation, only shows the part relevant with the embodiment of the invention.
In the present embodiment, said display drive circuit 100 comprises the chip for driving of a plurality of cascades.For for simplicity, Fig. 1 is that example is described with wherein first order chip for driving only.Concrete, the display drive circuit 100 of present embodiment comprises: signal input unit 10, data processing and shift register 20, data register 30, status register 40, counter 50 and pulse-length modulation (hereinafter to be referred as PWM) signal generation unit 60.Data processing and shift register 20 are coupled to the output terminal of signal input unit 10; Data register 30 all is coupled to data processing and shift register 20 with status register 40; Counter 50 is coupled to status register 40; The input of pwm signal generation unit 60 is coupled to data register 30 and counter 50, and the output of pwm signal generation unit 60 is coupled to a constant current output channel 70.Pwm signal is input to light emitting diode (LED) display screen 102 (seeing also Fig. 4) from constant current output channel 70, shows with control light emitting diode (LED) display screen 102.
Said signal input unit 10 comprises serial data input end, GTG input end of clock, data clock input end and data controlling signal input end, is respectively applied for input serial data signal (SDI), GTG clock signal (GCLK), data clock signal (DCLK) and data controlling signal (LE) that transmission receives from single-chip microcomputer (MCU).Wherein, Data clock signal (DCLK) is used for controlling input serial data signal (SDI) and is input to said data processing and shift register 20, and data clock signal (DCLK) cooperates data controlling signal (LE) that the input serial data signal (SDI) in data processing and the shift register 20 is transferred in the data register 30 simultaneously.GTG clock signal (GCLK) is the clock signal of counter.Data controlling signal (LE) then comprises the number of different data clock signal (DCLK) rising edge, and Data Control order and State Control order are carried out in representative.For example; Data controlling signal (LE) comprises the rising edge of 1 data clock signal (DCLK), and the Data Control order is carried out in representative, that is to say; At the negative edge of this data controlling signal (LE), input serial data signal (SDI) can be stored in the data register 30; If data controlling signal (LE) comprises the rising edge of 2 data clock signals (DCLK), then the State Control order is carried out in representative, and at this moment, input serial data signal (SDI) can be stored in the status register 40.In addition, in the present embodiment, the signal of said signal input unit 10 inputs is a cascade signal.Said input serial data signal (SDI) is imported according to the quantity of the chip for driving of cascade, for example, supposes a cascade M chip for driving, then need import M group input serial data signal (SDI).
Said data processing and shift register 20 are used to receive said data clock signal, data controlling signal and said input serial data signal; And respond said data clock signal and data controlling signal; To obtain serial luma data and serial status data from said at least one group of input serial data signal; And can signal that represent the serial luma data be outputed to said data register 30, and will represent the signal of serial status data to output to status register 40.
Said data register 30 is used for when receiving the data command of data controlling signal (LE), receives said serial luma data signal.
Said status register 40 is used for when receiving the status command of data controlling signal (LE), receiving said serial status data.Said status register 40 can also supply the user to preestablish the state of driving circuit; For example set driving circuit by how many grayscale mode (16 grayscale mode, 14 grayscale mode or 12 grayscale mode etc.) of line scanning, passage of advancing, thereby obtain a predetermined status data and a storage.
Said counter 50 is used for producing a count value according to the data of said predetermined status data, GTG clock signal (GCLK) and said status register 40.In the present embodiment, said counter 50 is according to formula: (2
H* T
GCLK+ T) * S * 2
LCalculating has the time of dynamic scan needs of complete image completion of S the number of scanning lines, wherein, and the high-order exponent number of H indicating impulse bandwidth modulation signals, the low order exponent number of L indicating impulse bandwidth modulation signals, T
GCLK* 2
HTime of high-order pulse width modulating signal needs is cut apart in expression, and T representes line scanning switching time, and S representes the number of scanning lines.The concrete course of work of counter 50 will be introduced in following examples in detail.
The count value of serial luma data sum counter 50 outputs that said pulse-length modulation (calling PWM in the following text) signal generation unit 60 is used for obtaining according to said GTG clock signal, from said data register 30 produces a plurality of pulse width modulating signals and with its output.Pwm signal generation unit 60 is obtained said serial luma data from data register 30 after the serial luma data is input in the data register 30, and under the control of count value, carry out cutting apart of pwm signal, and the output of the pwm signal after will cutting apart.
Need to prove; The first order chip for driving of said display drive circuit 100 also can be exported an output signal SDO; With the input serial data signal (SDI) as next stage cascade chip for driving, and the data controlling signal of cascade chip for driving at different levels (LE), data clock signal (DCLK), GTG clock signal (GCLK) are all corresponding identical with first order chip for driving.
Fig. 2 is that input serial data signal (SDI) and data controlling signal (LE) cooperate data clock signal (DCLK) to accomplish the sequential synoptic diagram of input, with the signal input process of explanation display drive circuit 100.From Fig. 2, can know; If display drive circuit 100 comprises the cascade of M chips; And serial data is imported 1 signal (SDI) serial input at the edge of data clock signal (DCLK), then after M group input serial data signal (SDI) is accomplished in input, according to the control of data controlling signal (LE) and data clock signal (DCLK); Data processing and shift register 20 luma data of will connecting is sent in the data register 30, thereby accomplishes delegation's scan-data input of display drive circuit 100.Carry out the S line scanning if desired, then need accomplish the signal input of S * M group input serial data signal (SDI).It should be noted that; After having imported M group signal at every turn; All need be under the control of data controlling signal (LE) and data clock signal (DCLK); Send the order that the data input is accomplished to the chip for driving of correspondence, and then the serial luma data of data processing and shift register 20 is sent in the data register 30.
As stated; Status register 40 can be through preestablishing;, make luma data cooperate jointly and produce the pwm signal of cutting apart to counter 50 according to the gray level information output data of the information of the number of scanning lines and luma data, and let the high refresh rate of system's acquisition with count value.
For instance, if M chip for driving of driving circuit cascade, the output channel number of every chip for driving is C; The number of scanning lines is S, and line scanning switching time (blanking time) is set at T, and the GTG of the output data of while chip for driving is controlled as the P rank, and (its high-order is the H rank; Low order is the L rank, and H+L=P).Then according to the count value of counter 50, the pwm signal on P rank can be divided into 2 in pwm signal generation unit 60
LThe pwm signal on individual H rank.And, if only triggering at the edge of data clock signal (DCLK), input serial data signal (SDI) gets into chip for driving, time of luma data of then importing the chip for driving of M cascade is T
DCLK* C * M * P.When the P rank luma data of input was divided into pwm signal, the time of cutting apart H rank pwm signal needs was T
GCLK* 2
HIn the time of a H rank pwm signal in accomplishing the output one's own profession, need the input of the luma data of completion next line cascade, imperfect for the data that prevent to import, need satisfy T
DCLK* C * M * P≤T
GCLK* 2
HMoreover if the number of scanning lines is S, then counter 50 carries out the first time 2 earlier when beginning that image carried out cycle count
HCounting, then at interval (2
H* T
GCLK+ T) * (S-1) time, continue for the second time 2
HCounting, and then one (2 at interval
H* T
GCLK+ T) * (S-1) time ... circulation successively is up to accomplishing 2
L Inferior 2
HCounting, just finish the counting of an image complete cycle, the complete cycle time of an image is (2
H* T
GCLK+ T) * S * 2
L
Fig. 3 be display drive circuit 100 under S line scanning situation, accomplish the waveform synoptic diagram of the pwm signal output of a width of cloth complete image, carry out the driving process of data scanning and output to show display drive circuit 100.Wherein, in Fig. 3, for the number of scanning lines 1, pwm signal generation unit 60 is divided into 2 with whole section original PWM waveform
LIndividual width is T
GCLK* 2
HThe PWM waveform.Equally, for the number of scanning lines 2, also whole section original PWM waveform is divided into 2
LIndividual width is T
GCLK* 2
HThe PWM waveform.By that analogy, when number of scanning lines S, also whole section original PWM waveform is divided into 2
LIndividual width is T
GCLK* 2
HThe PWM waveform.First width in each scan line is T
GCLK* 2
HThe PWM waveform occur successively, the time interval (blanking time) that divided PWM waveform occurs between every row is T.(2
H* T
GCLK+T) * and S is after the time, and first width of accomplishing all row is T
GCLK* 2
HThe array output of pwm signal.According to identical principle, second width that carries out all row is T
GCLK* 2
HThe array output of pwm signal, up to carrying out the 2nd of all row
LIndividual width is T
GCLK* 2
HThe array output of pwm signal finish, just accomplish the complete output of piece image.In the present embodiment, the piece image data of display screen are the luma data value of input serial data signal in the driving circuit (SDI), that is to say, the information in the image is represented the luma data value, when the luma data value is big more, then represent bright more; Luma data is more little, and then expression is dark more.
The course of work of display drive circuit 100 of the present invention is described with specific embodiment below, but is not to limit category of the present invention anyways.
In the present embodiment, setting data clock signal (DCLK) equals GTG clock signal (GCLK), i.e. T
GCLKEqual T
DCLK, and carry out 8 line scannings, line scanning interval time is T, 4 chip for driving of every capable cascade, every chip for driving has 16 output channels, and the input luma data is 16 rank.Hence one can see that, in the present embodiment, because the input luma data is 16 rank (high-order is 10, and low order is 6), then need the pwm signal on 16 rank be divided into 64 1024 * T
GCLKThe GTG signal.Therefore, each output channel of chip for driving need be set at 16 rank patterns, promptly need 16 luma data, and because every chip for driving has 16 output channels, then a chip for driving need be imported 256 luma data.4 chip for driving of every capable cascade simultaneously, then when line scanning, every row needs 1024 luma data of input.The luma data of input serial data signal (SDI) is in the input that is shifted of the rising edge of data clock signal (DCLK), and the time that then accomplishing a line scanning input needs is 1024 * T
DCLK, the time that accomplishing 8 line scannings needs is 1024 * T
DCLK* 8.
Be appreciated that input serial data signal (SDI) also can be at the negative edge of data clock signal (DCLK), perhaps simultaneously in rising edge and negative edge input.
Introduce the course of work of counter 50 below.After signal input unit 10 is input to the chip for driving of 4 cascades with 1024 serial luma data signals; Every cascade chip for driving all need obtain 256 luma data signals; That is to say that the passage of each cascade chip for driving has all obtained the luma data on 16 rank.Said 4 cascade chip for driving are according to the data in the status register 40, confirm that chip for driving will carry out 8 line scannings, and the luma data on these 16 rank is divided into 64 1024 * T
GCLKThe PWM waveform.Therefore, the 50 generation cycles of counter are 1024 counter 50 values, behind the counting of accomplishing the first time 1024, and one the 8 * (1024 * T in interval
GCLK+ T) time, the cycle for the second time of carrying out again is 1024 counting, subsequently one 8 * (1024 * T at interval again
GCLK+ T) time ..., and the like, be 1024 counting up to accomplishing the 64th cycle.
When carrying out first line scanning, signal input unit 10 is accomplished the input of 1024 luma data signals of first row earlier, is carried out the scanning output of first row again by pwm signal generation unit 60, just carries out first line data is divided into many group 1024 * T
GCLK, and to first group of 1024 * T
GCLKThe operation of exporting.When carrying out scan-data output, signal input unit 10 is then imported 1024 luma data signals of second row.Accomplish first group of 1024 * T at first row
GCLKCut apart and when being expert at sweep spacing behind the T, begin to carry out the scanning of second row, just carry out first group of 1024 * T in the second line data cutting operation
GCLKOperation.By that analogy, up to the input of in the 7th line scanning output procedure, accomplishing 1024 luma data signals of eighth row, accomplish first group of 1024 * T at the 7th row then
GCLKBehind the T, carrying out the scanning of eighth row when cutting apart with line scanning at interval, also is to carry out first group of 1024 * T in the eighth row data cutting operation
GCLKOperation, just accomplish the output of the assembled pulse width signal that one time 8 row cuts apart after last time T at interval.Owing to accomplished the input of 8 line scannings, one width of cloth complete image luma data, next carry out the scanning of first row once more, carry out second group of 1024 * T in the first line data cutting operation specifically
GCLKOperation, cut apart completion after, behind interval time T, then carry out the scanning of second row, and only carry out second group of 1024 * T in the second line data cutting operation
GCLKOperation ... up to the scanning of carrying out eighth row once more, only carry out second group of 1024 * T in the eighth row data cutting operation
GCLKOperation, last, after time T at interval, promptly accomplish the output of the assembled pulse width signal that 8 row for the second time cut apart.According to this order,, just can accomplish the demonstration of a width of cloth complete image up to accomplishing 64 times 8 line scannings.According to top explanation, accomplish 8 line scannings and need import 1024 * 8 input serial data signals (SDI) altogether; And at 1024 * T
GCLKTime in, need to accomplish the data input of next line scanning, and this data need 1024 * T input time
DCLK, therefore,, require 1024 * T for the input that guarantees data is correct
GCLK>=1024 * T
DCLK
Adopt the partition type pwm signal of 8 line scannings, the combination PWM time that completion output 8 row are cut apart is 8 * (1024+T) * T
GCLKIf the frequency of GTG clock signal (GCLK) is 20MHz, then screen refresh rate is about 2441Hz.Under the same conditions, adopt prior PWM signal chip for driving, its screen refresh rate is about 38Hz.Can find out that the present invention can significantly improve the screen refresh rate of system in dynamic scan.
Be appreciated that and adopted 8 line scannings in the present embodiment, and in other embodiments, also can be any amount line scanning.For example, if be 16 line scannings, then the refresh rate of screen is about 1220Hz.In the light emitting diode (LED) display screen drive system, because the significantly raising of system refresh rate is even the number of scanning lines increases to some extent, also limited to the refresh rate influence of system.Simultaneously, because the increase of the number of scanning lines can increase by a chips and drive more light emitting diode number.
Generally speaking; The data of each width of cloth image of light emitting display device all are input to display drive circuit 100 with serial data mode; Display drive circuit 100 is through data controlling signal, control data handle with shift register 20 with data transfer in data register 30 and status register 40.Counter 50 is exported count value exactly and is exported the pulse width modulating signal of cutting apart according to count value in the control of the status data of status register 40 down.The time that accomplishing a complete image in the conventional dynamic scan screen system needs is (2
P* T
GCLK+ T) * and S, then the refresh rate of screen does
The present invention is cut apart form because input PWM luma data has adopted; And the counter 50 of chip for driving produces count value and interval time according to predetermined requirement, and the PWM luma data signal that a width of cloth complete image data of then exporting just can be regarded input as is converted into 2
LThe individual pwm signal of cutting apart group.And each cuts apart the pwm signal of group, comprised from first row to S capable the pwm signal on every capable H rank, the time that every row switches is T, like this, accomplishing time of cutting apart the pwm signal of group of output is (2
H* T
GCLK+ T) * and S, that is to say that the refresh rate of display screen system does
Therefore can the refresh rate of display screen be promoted about 2
LDoubly.
See also Fig. 4, the light emitting display device 200 that it is to use 1 chip for driving to drive, said light emitting display device 200 comprises switchgear 101 and light emitting diode (LED) display screen 102 in addition.Light emitting diode (LED) display screen 102 need use under the cooperation of switchgear 101.Illustrate, light emitting diode (LED) display screen 102 can be divided into the first row light emitting diode, the second row light emitting diode ... and the capable light emitting diode of S.Switchgear 101 circulate conducting successively first row light emitting diode, the second row light emitting diode ... with the capable light emitting diode of S, the time interval between every capable conducting is T.
When switchgear 101 switches to S when capable; A chip for driving of driving circuit 100 can be exported the drive signal of the capable light emitting diode of S; When the capable signal end of output of S; Switchgear 101 just cuts out all row, and said chip for driving also stops output drive signal simultaneously, and be T this interval time.The principle of work of other each row is identical therewith.And in this cascade system, the driving circuit of back level is identical with the first order with the principle of work of display screen.
Above disclosedly be merely a kind of preferred embodiment of the present invention, can not limit the present invention's interest field certainly with this, the equivalent variations of therefore doing according to claim of the present invention still belongs to the scope that the present invention is contained.
Claims (10)
1. display drive circuit, it comprises:
Signal input unit is used for input serial data input signal, GTG clock signal, data clock signal and data controlling signal;
Data processing and shift register are coupled to said signal input unit, are used to respond said data clock signal and data controlling signal and obtain serial luma data and serial status data from said input serial data signal;
Data register is coupled to said data processing and shift register, is used to receive said serial luma data signal;
Status register is coupled to said data processing and shift register, is used to store a predetermined status data and receives said serial status data;
Counter is coupled to said status register, is used for producing a count value according to said predetermined status data, said serial status data and said GTG clock signal; And
The pulse width modulating signal generation unit is coupled to said data register and said counter, is used for the count value according to the serial luma data sum counter that obtains from said data register, produces a plurality of pulse width modulating signals and output.
2. display drive circuit as claimed in claim 1 is characterized in that: said pulse width modulating signal generation unit is used for the serial luma data is divided into 2
LThe pulse width modulating signal on individual H rank, wherein, the high-order exponent number of H indicating impulse bandwidth modulation signals, the low order exponent number of L indicating impulse bandwidth modulation signals.
3. display drive circuit as claimed in claim 2 is characterized in that: said counter is according to formula: (2
H* T
GCLK+ T) * S * 2
LCalculating has the time of dynamic scan needs of complete image completion of S the number of scanning lines, wherein, and T
GCLK* 2
HExpression output each by the time of the pulse width modulating signal needs after cutting apart, T representes line scanning switching time, S representes the number of scanning lines.
4. display drive circuit as claimed in claim 3 is characterized in that: counter carries out when counting scan period to piece image, carries out the first time 2 earlier
HCounting, then at interval (2
H* T
GCLK+ T) * (S-1) time, continue for the second time 2
HCounting, and then one (2 at interval
H* T
GCLK+ T) * (S-1) time ... circulation successively is up to accomplishing 2
LInferior 2
HCounting.
5. display drive circuit as claimed in claim 4 is characterized in that: the output time of accomplishing delegation's pulse width modulating signal is more than or equal to the input time of accomplishing next line serial luma data to be scanned.
6. display drive circuit as claimed in claim 1 is characterized in that: said status register also is used to supply the user to set the state of driving circuit, to obtain said predetermined status data.
7. display drive circuit as claimed in claim 1; It is characterized in that: said display drive circuit comprises the chip for driving of a plurality of cascades, and each chip for driving comprises said signal input unit, data processing and a shift register, data register, status register, counter and pulse width modulating signal generation unit.
8. display drive circuit as claimed in claim 1; It is characterized in that: said signal input unit comprises serial data input end, GTG input end of clock, data clock input end and data controlling signal input end, is respectively applied for the said input serial data signal of transmission, GTG clock signal, data clock signal and data controlling signal.
9. light emitting display device; It comprises at least: light emitting diode (LED) display screen and like each described display drive circuit of claim 1-8 item; This display drive circuit is coupled to said light emitting diode (LED) display screen, to drive said light emitting diode (LED) display screen display image.
10. light emitting display device as claimed in claim 9; It is characterized in that: the output of said pulse width modulating signal generation unit is coupled to a constant current output channel, and pulse width modulating signal is input to said light emitting diode (LED) display screen from said constant current output channel.
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| US12456413B2 (en) * | 2022-04-28 | 2025-10-28 | BOE MLED Technology Co., Ltd. | Circuit component, electronic device and driving method |
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