CN103699112B - Based on avionics Autonomous test Authentication devices and the verification method thereof of I/O signal fault simulation - Google Patents

Abstract

The invention discloses an avionics self-detection verification device based on IO signal fault simulation, which includes a verification host outside the avionics device and a fault simulation module inside the avionics device, the verification host imitates an external IO fault, and the fault simulation module imitates For internal IO faults, the self-test of the avionics equipment is used to diagnose and isolate the failure mode, and the output results are compared to confirm whether the output results are accurate, so as to judge whether the BIT design of the avionics equipment meets the predetermined requirements. The invention can improve the automatic simulation injection design level and ability of the IO signal failure mode, thereby expanding the simulation range of the IO signal failure mode and the coverage of the self-test verification of the avionics equipment, and improving the self-test verification efficiency.

Description

Avionics self-test verification equipment and verification method based on IO signal fault simulation

technical field

The invention relates to the technical field of testable design verification of avionics products, in particular to the self-test verification of IO fault signals.

Background technique

In the technical field of testability design and verification of avionics products, for the simulation and injection of failure modes such as power supply signals, digital IO signals, and bus communication signals, simple on-off and manual interference signal methods are mostly used, and the injection failure mode is single and It may cause damage to the circuit, and there is no relatively complete and comprehensive automatic fault injection method. This technical patent describes a design method that realizes multiple fault modes of IO signals can be set and automatically injected to verify the level of testability and self-test design of avionics equipment.

Contents of the invention

The purpose of the present invention is to provide an avionics self-test verification device based on IO signal fault simulation, which automatically injects various fault modes of digital IO, power supply, bus and other signals into the device under test to verify the avionics device The testability self-test design level.

The purpose of the invention of the present invention is achieved through the following technical solutions:

An avionics self-test verification device based on IO signal fault simulation, including a verification host located outside the avionics device and a fault simulation module located inside the avionics device:

The verification host is used for external IO fault simulation, including a control computer, a self-test monitoring interface, a simulation fault resource board, a verification test interface, and input and output devices;

The control computer runs the verification program, obtains the self-test information of the avionics equipment through the self-test monitoring interface, and verifies whether the self-test results of the avionics equipment are accurate;

The simulated fault resource board allocates the operating environment of the avionics equipment and the external fault simulation resources to the verification test interface according to the instructions of the control computer, and the verification cable is connected to the external interface of the avionics device through the test;

The self-test monitoring interface obtains various self-test data information output by the avionics equipment through the verification test interface and the test verification cable;

The fault simulation module is used for internal IO fault simulation, and is embedded in the riser board between the imitated module and the equipment motherboard inside the avionics equipment, including SOC and FPGA. FPGA includes control registers and signal conversion arrays. SOC passes serial The communication port communicates with the verification host, writes the control word of the control register according to the command of the control computer, controls the signal conversion array in the FPGA, and inserts the predetermined fault signal under the condition that the imitated module is disconnected to realize the inter-board IO signal Fault simulation.

Preferably, the platform of the verification host is a PXI bus platform.

Preferably, the simulated fault resource board includes:

GJB289A bus interface module: simulate GJB289A bus signal failure, including communication errors: illegal command or data, protocol error;

ARINC429 bus interface module: simulate ARINC429 bus signal failure, including communication errors: illegal command or data, protocol error;

HDLC communication interface module: simulate HDLC signal failure, including communication errors: illegal command or data, protocol error;

RS422/485 bus interface module: simulate RS422/485 bus signal failure, including communication errors: illegal command or data, protocol error;

Analog signal output module: simulate analog signal faults, including signal level overrun;

Digital output module: Simulate digital signal faults, including disconnection/short circuit;

Multifunctional data acquisition module, video signal output module, analog video acquisition module, digital video acquisition module: simulate video signal failure.

Preferably, the self-test monitoring interface includes a 16-bit digital discrete input interface and a 2-channel asynchronous serial communication interface.

Preferably, the fault simulation module is mounted on the rising board between the simulated module and the motherboard of the avionics equipment through two edge connectors.

Preferably, the signal conversion array has 4 kinds of inputs according to the control word gate of the control register and 1 channel is used as the output, so as to realize the IO signal fault simulation between modules;

The four kinds of inputs are 1) NORM: the original signal is connected, and it is in a normal signal state at this time;

2) VCC: Turn on VCC to simulate the fault state that the signal line is deadlocked at logic "1";

3) GND: Connect GND to simulate the fault state that the signal line is deadlocked at logic "0";

4) ARB: Turn on the on-chip signal generator or external expansion signal to simulate the error state of the signal line.

Preferably, a signal generator is also included in the FPGA, and the signal generator provides the following two forms of fault signals according to the control word of the control register:

1) Error sequence: According to the error sequence written by the SOC to the signal generator and the set parameters in the control register, it is sent cyclically according to the set clock frequency and interval;

2) Noise: A pseudo-random sequence circuit is used to generate white noise.

Preferably, the fault simulation module further includes a relay, so that the voltage of the main power supply to the module can be switched between normal and undervoltage, and the auxiliary power can be switched between normal and disconnected, so as to simulate a power failure.

Another object of the present invention is to provide a verification method for avionics self-test verification equipment, comprising the following steps:

a) Start the IO signal failure simulator and avionics equipment;

b) Control the avionics equipment to enter the working mode;

c) Verify that the host computer provides the external signal environment required for the normal operation of the avionics equipment;

d) Verify that the main engine simulates the failure of the external signal of the avionics equipment and the fault of the cross-connection state, and realizes external fault injection;

e) The fault prevention module simulates the faults of the inter-module signals and cross-connection status of the avionics equipment to realize internal fault injection;

f) The self-test monitoring interface reads the self-test information of the avionics equipment;

g) The control computer monitors the self-test data output by the avionics equipment or the change of the self-test mark in real time, and confirms by comparison

Whether the output result is accurate can judge whether the self-test design of avionics equipment meets the predetermined requirements.

Description of drawings

Fig. 1 is the structural representation of IO signal failure emulator of the present invention;

Figure 2 is a schematic diagram of the working connection mode of the fault simulation module;

Figure 3 is a schematic diagram of the working principle of the fault simulation module;

Figure 4 is the basic conversion logic diagram between the input and output signals in the FPGA chip

Figure 5 is a composition diagram of the verification host software;

Figure 6 is a software composition diagram of the fault simulation module.

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings.

The application example of the avionics BIT verification method based on IO signal fault simulation is the avionics self-test verification device based on IO signal fault simulation, including two parts of the verification host and fault simulation module, as well as their respective software programs. The detailed design is described as follows.

Figure 1 is a schematic diagram of the composition of the verification equipment. Each resource module in the verification host runs the verification program under the control of the PXI embedded control computer through the PXI bus to realize the automation of the entire verification test process.

1. Verify the configuration and composition of the host

The verification host introduces signal errors at the interface between the avionics device and the external interface within the time interval set by the software program, so that the interaction between the signals is in a fault state, thereby affecting the operation of the avionics device that is subject to self-test verification. The self-inspection of avionics equipment distinguishes such faults from its own faults, and locates the faults in external devices related to the faults.

The verification host is composed of PXI chassis (including PXI embedded control computer), self-test monitoring interface, simulation fault resource board, verification test interface and input and output devices (keyboard, mouse, monitor, etc.). The simulation fault resource board allocates the avionics equipment operating environment & external fault simulation resources to the verification test interface, including the working power supply, etc., and verifies the connection between the cable and the avionics device through the test. The self-test monitoring interface obtains various BIT data information output by the avionics equipment through the verification test interface and test cable. The detailed configuration is as follows:

1.1 Verify host platform

Verify that the host platform selects the PXI bus platform.

1.2 Embedded computer-on-module

The embedded computer is used as the measurement and control computer of the verification host, and its basic configuration and technical indicators are as follows:

CPU: Intel Pentium M, main frequency 2.0GHz, or above;

·Memory: 2GB;

Hard disk: 80GB or above;

Network port: 10M/100M/1000M adaptive, 2 channels;

·USB interface: 4 channels;

·Serial port: 2 channels;

·Display port: DVI port.

1.3 Avionics equipment operating environment and external fault simulation

The simulation fault resource board used to support the operation of avionics equipment and external IO signal fault simulation in the verification host includes the following modules:

a) GJB289A bus interface module (simulation of GJB289A bus signal failure, such as communication error: illegal command or data, protocol error, etc.);

b) ARINC429 bus interface module (simulation of ARINC429 bus signal faults, such as communication errors: illegal commands or data, protocol errors, etc.);

c) HDLC communication interface module (simulation of HDLC signal faults, such as communication errors: illegal commands or data, protocol errors, etc.);

d) RS422/485 bus interface module (simulation of RS422/485 bus signal faults, such as communication errors: illegal commands or data, protocol errors, etc.);

e) Analog signal output module (simulation of analog signal faults, such as signal level overrun, etc.);

f) Switch output module (simulation of switch signal failure, such as disconnection/short circuit, etc.);

g) multifunctional data acquisition module, h) video signal output module, i) analog video acquisition module, j) digital video acquisition module (analog video signal failure).

1.4 Self-test monitoring interface

The self-test monitoring interface includes the following signal interfaces for reading self-test data and identification:

a) Digital discrete input interface: 16 bits;

b) Asynchronous serial communication interface: 2 channels.

2. Fault Simulation Module (FSM)

See Figure 2 for the working connection diagram of the fault simulation module, and Figure 3 for the working principle.

The fault simulation module is mounted on the rising board between the imitated module and the motherboard of the avionics equipment through two edge connectors, and the verification test program of the verification host controls the internal circuit of the FSM, and then controls the on-off of the signal cross-connection relationship between the original boards , and under the condition of disconnection, insert a predetermined fault signal, change the state of cross-connection of IO signals between modules, and realize fault simulation of IO signals between boards, thereby affecting the operation of avionics equipment. The self-test of avionics equipment determines such failures as their own failures, which are distinguished from external equipment failures.

The basic working principle of FSM is as follows:

a) Fault simulation control

The SOC on the FSM communicates with the verification host through the serial communication port, and controls the conversion circuit array in the FPGA according to the verification host command to generate different fault conditions.

b) IO signal failure simulation

The basic conversion logic between the input and output signals of the FPGA chip on the FSM module is shown in Figure 4. According to the SOC, the control word written into the control register according to the command of the verification host, one of the four different inputs is selected as the output, and the module is realized. Inter-IO signal failure simulation.

1) NORM: Turn on the original signal, which is the normal signal state at this time;

2) VCC: Turn on VCC to simulate the fault state that the signal line is deadlocked at logic "1";

3) GND: Connect GND to simulate the fault state that the signal line is deadlocked at logic "0";

4) ARB: Turn on the on-chip signal generator (or external expansion signal), and simulate the error state of the signal line.

c) Power control

The SOC controls the relay on the FSM so that the main power supply voltage that supplies power to the module can be switched between normal and undervoltage conditions, and the auxiliary power supply can be switched between normal and disconnected conditions to simulate a power failure.

d) Signal generator

The signal generator in the FPGA chip provides the following two forms of fault signals:

1) Error sequence: According to the error sequence written by the SOC to the signal generator and the set parameters in the control register, it is sent cyclically according to the set clock frequency and interval, and cyclically according to the set clock frequency and interval.

2) Noise: A pseudo-random sequence circuit is used to generate white noise.

3. Verify software development

The verification software is divided into two parts: the verification host software and the fault simulation module software. The software composition is shown in Figures 5 and 6.

The verification software development adopts the operating environment of VISUALC++6.0 and WINDOWSXP.

4. Verification process

The verification process consists of the following steps:

a) Start the IO signal failure simulator and avionics equipment;

b) Control the avionics equipment to enter the working mode;

c) Verify that the host computer provides the external signal environment required for the normal operation of the avionics equipment;

d) Verify that the main engine simulates the failure of the external signal of the avionics equipment and the fault of the cross-connection state, and realizes external fault injection;

e) The fault prevention module simulates the on-off of the signals between the internal modules of the avionics equipment and the cross-connection relationship of the signals between the internal modules, so as to realize the injection of internal faults;

f) The self-test monitoring interface reads the self-test information of the avionics equipment;

g) The control computer monitors the self-inspection data output by the avionics equipment or the change of the self-inspection identification in real time, and confirms whether the output results are accurate through comparison to determine whether the self-inspection design of the avionics equipment meets the predetermined requirements.

Claims (9)

1. A kind of avionics self-detection verification equipment based on IO signal fault simulation, comprises the verification main frame that is positioned at the avionics device outside and is positioned at the fault emulation module inside the avionics device, is characterized in that: The verification host is used for external IO fault simulation, including a control computer, a self-test monitoring interface, a simulation fault resource board, a verification test interface, and input and output devices; The control computer runs the verification program, obtains the self-test information of the avionics equipment through the self-test monitoring interface, and verifies whether the self-test results of the avionics equipment are accurate; The simulated fault resource board allocates the operating environment of the avionics equipment and the external fault simulation resources to the verification test interface according to the instructions of the control computer, and the verification cable is connected to the external interface of the avionics device through the test; The self-test monitoring interface obtains various self-test data information output by the avionics equipment through the verification test interface and the test verification cable; The fault simulation module is used for internal IO fault simulation, and is embedded in the riser board between the imitated module and the equipment motherboard inside the avionics equipment, and includes SOC and FPGA. FPGA includes control registers and signal conversion arrays. SOC passes serial The communication port communicates with the verification host, writes the control word of the control register according to the command of the control computer, controls the signal conversion array in the FPGA, and inserts the predetermined fault signal under the condition that the imitated module is disconnected to realize the inter-board IO signal Fault simulation. 2. The avionics self-test verification device according to claim 1, characterized in that the platform of the verification host is a PXI bus platform. 3. The avionics self-test verification device according to claim 1, wherein said simulation failure resource board includes: GJB289A bus interface module: simulate GJB289A bus signal failure, including communication errors: illegal command or data, protocol error; ARINC429 bus interface module: simulate ARINC429 bus signal failure, including communication errors: illegal command or data, protocol error; HDLC communication interface module: simulate HDLC signal failure, including communication errors: illegal command or data, protocol error; RS422/485 bus interface module: simulate RS422/485 bus signal failure, including communication errors: illegal command or data, protocol error; Analog signal output module: simulate analog signal faults, including signal level overrun; Digital output module: Simulate digital signal faults, including disconnection/short circuit; Multifunctional data acquisition module, video signal output module, analog video acquisition module, digital video acquisition module: simulate video signal failure. 4. The avionics self-test verification device according to claim 1, characterized in that the self-test monitoring interface includes a 16-bit digital discrete input interface and a 2-channel asynchronous serial communication interface. 5. The avionics self-test verification device according to claim 1, characterized in that the fault simulation module is mounted on the riser between the simulated module and the avionics motherboard through two edge connectors. 6. Avionics self-test verification equipment according to claim 1, said signal conversion array has 4 kinds of input according to the control word gate of control register 1 way as output, realizes IO signal failure simulation between modules; The four kinds of inputs are 1) NORM: the original signal is connected, and it is in a normal signal state at this time; 2) VCC: Turn on VCC to simulate the fault state that the signal line is deadlocked at logic "1"; 3) GND: Connect GND to simulate the fault state that the signal line is deadlocked at logic "0"; 4) ARB: Turn on the on-chip signal generator or external expansion signal to simulate the error state of the signal line. 7. avionics self-test verification equipment according to claim 1, is characterized in that also comprising signal generator in the described FPGA, and described signal generator provides the fault signal of following two forms according to the control word of control register: 1) Error sequence: According to the error sequence written by the SOC to the signal generator and the set parameters in the control register, it is sent cyclically according to the set clock frequency and interval; 2) Noise: A pseudo-random sequence circuit is used to generate white noise. 8. The avionics self-test verification device according to claim 1, wherein the fault simulation module also includes a relay, so that the voltage of the main power supply to the module can be switched between normal and undervoltage conditions, and the auxiliary power supply Switchable between normal and disconnected conditions to simulate a power failure. 9. The verification method of the avionics self-test verification device according to any one of claims 1-8, comprising the following steps: a) Start the IO signal failure simulator and avionics equipment; b) Control the avionics equipment to enter the working mode; c) Verify that the host computer provides the external signal environment required for the normal operation of the avionics equipment; d) Verify the on-off of the external signal of the main engine simulation avionics equipment and the cross-connection relationship of the external signal, so as to realize the injection of external faults; e) The fault prevention module simulates the on-off of the signals between the internal modules of the avionics equipment and the cross-connection relationship of the signals between the internal modules, so as to realize the injection of internal faults; f) The self-test monitoring interface reads the self-test information of the avionics equipment; g) The control computer monitors the self-inspection data output by the avionics equipment or the change of the self-inspection identification in real time, and confirms whether the output results are accurate through comparison to determine whether the self-inspection design of the avionics equipment meets the predetermined requirements.