CN105655352A - Manufacturing method of low-temperature polysilicon TFT array substrate - Google Patents

Manufacturing method of low-temperature polysilicon TFT array substrate Download PDF

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CN105655352A
CN105655352A CN201610024267.3A CN201610024267A CN105655352A CN 105655352 A CN105655352 A CN 105655352A CN 201610024267 A CN201610024267 A CN 201610024267A CN 105655352 A CN105655352 A CN 105655352A
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low
temperature polysilicon
photoresist
array substrate
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CN105655352B (en
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赵瑜
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes

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Abstract

The invention provides a manufacturing method of a low-temperature polysilicon TFT array substrate. The method is characterized in that residual solidified photoresist after iron doping is totally removed by means of two times of continuous photoresist ashing and photoresist removing processing, so that the problem of solidified photoresist remaining due to that the first time ashing processing is resisted since some areas of the photoresist layer are covered by foreign particles before the first time of ashing processing, the interface cleanliness of a grid electrode insulating layer and an interlayer insulating layer is improved, and the decreasing product yield rate caused by the interface problem is prevented.

Description

The manufacture method of low temperature polycrystalline silicon tft array substrate
Technical field
The present invention relates to Display Technique field, particularly relate to the manufacture method of a kind of low temperature polycrystalline silicon tft array substrate.
Background technology
Thin film transistor (TFT) (ThinFilmTransistor, TFT) it is current liquid crystal indicator (LiquidCrystalDisplay, and active matrix drive type organic electroluminescence display device and method of manufacturing same (ActiveMatrixOrganicLight-EmittingDiode LCD), AMOLED) the main driving element in, the display performance of direct relation panel display apparatus.
Thin film transistor (TFT) has various structures, the material of the thin film transistor (TFT) preparing corresponding construction also has multiple, low temperature polycrystalline silicon (LowTemperaturePoly-silicon, LTPS) material is wherein comparatively preferred a kind of, owing to the atomic rule of low temperature polycrystalline silicon arranges, carrier mobility is high, liquid crystal indicator for voltage driven type, low-temperature polysilicon film transistor has higher mobility due to it, the thin film transistor (TFT) that can use small volume realizes the deflection driven to liquid crystal molecule, reduce the volume shared by thin film transistor (TFT) to a great extent, increase glazed area, obtain higher brightness and resolution, for the active matrix drive type organic electroluminescence display device and method of manufacturing same of current-driven, low-temperature polysilicon film transistor can better meet driving current requirements.
Whether LCD or AMOLED all includes a tft array substrate.
The manufacturing process of existing low temperature polycrystalline silicon tft array substrate is generally: make light shield layer, insulating buffer layer, low-temperature polysilicon silicon semiconductor layer, gate insulator, grid, interlayer insulating film, source/drain, flatness layer, bottom electrode, protective layer and top layer electrode on underlay substrate from bottom to up successively. Wherein, low-temperature polysilicon silicon semiconductor layer includes again the centrally located channel region corresponding to grid and is positioned at the ion doped region corresponding to source/drain at two ends.
Make ion doped region detailed process be: first on low-temperature polycrystalline silicon layer be coated with photoresistance, photoresistance is exposed, develop, toast after obtain pattern photoresist layer, to expose two end regions of low-temperature polycrystalline silicon layer; Then with photoresist layer for shielding layer, two end regions of low-temperature polycrystalline silicon layer are carried out ion doping; Next successively photoresistance ashing and removing photoresistance are carried out. In this course, some region of photoresist layer is likely to be coated with impurity particle, block photoresistance ashing, cause cannot removing photoresist layer completely, cause solidification photoresistance residual, and then have influence on the interface quality of the gate insulator of follow-up making, interlayer insulating film, cause gate insulator, interlayer insulating film to produce to peel off and the problem such as crackle, ultimately result in product quality and decline.
Current existing improve gate insulator, the measure of layer insulation bed boundary has: changes cleaning condition before film forming or carries out plasma treatment, but these measure limited use and all ignore the problem solidifying photoresistance residual caused because some region before ashing processes of the photoresist layer used in ion doping is likely to be coated with impurity particle.
Summary of the invention
It is an object of the invention to provide the manufacture method of a kind of low temperature polycrystalline silicon tft array substrate, the solidification photoresistance remained after can removing ion doping completely, improve the interface cleanness degree of gate insulator and interlayer insulating film, it is to avoid the product yield that interface problem causes declines.
For achieving the above object, the invention provides the manufacture method of a kind of low temperature polycrystalline silicon tft array substrate, comprise the steps:
Step 1, providing a underlay substrate, form the light shield layer of patterning on described underlay substrate, on described light shield layer with underlay substrate, deposition covers insulating buffer layer;
Step 2, on described insulating buffer layer, form the low-temperature polycrystalline silicon layer of patterning corresponding to described light shield layer;
Step 3, on described low-temperature polycrystalline silicon layer and cushion coating photoresist, pattern described photoresist, form photoresist layer, expose two end regions of at least part of low-temperature polycrystalline silicon layer;
Step 4, with described photoresist layer for shielding layer, two end regions of corresponding low-temperature polycrystalline silicon layer are carried out a type of ion doping, form low-temperature polysilicon silicon semiconductor layer;
Step 5, carry out first time photoresistance ashing and removing photoresistance process;
Step 6, carry out second time photoresistance ashing and removing photoresistance process, to remove photoresist layer completely;
Step 7, in described low-temperature polysilicon silicon semiconductor layer and insulating buffer layer, make gate insulator, grid, interlayer insulating film, source/drain, flatness layer, bottom electrode, protective layer and top layer electrode successively.
Described step 7 is after completing making grid, it is additionally included on grid and gate insulator and is coated with and patterns photoresist, form another photoresist layer, with another photoresist layer described for shielding layer, two end regions of the remaining low-temperature polycrystalline silicon layer carrying out ion doping without step 4 are carried out another type of ion doping, form low-temperature polysilicon silicon semiconductor layer and the process that double photoresistance ashing and removing photoresistance process, make described interlayer insulating film afterwards again.
In described step 2, the concrete manufacturing process of the low-temperature polycrystalline silicon layer of patterning is: first deposit one layer of non-crystalline silicon on described insulating buffer layer, again non-crystalline silicon is carried out Crystallizing treatment, prepare low temperature polycrystalline silicon, then pass through lithographic process and obtain the low-temperature polycrystalline silicon layer of patterning.
Described step 3 patterns described photoresist by exposure, developing manufacture process and obtains described photoresist layer.
The P type ion doping of the N-type ion doping that a type of ion doping is Doping Phosphorus ion described in step 4 or doped with boron ion; Another type of ion doping described in step 7 is the P type ion doping or the N-type ion doping that are different from step 4.
Described source/drain contacts respectively through the two ends of the via with described low-temperature polysilicon silicon semiconductor layer that run through interlayer insulating film and gate insulator.
One or both the compound that the material of described insulating buffer layer, gate insulator, interlayer insulating film, flatness layer and protective layer is in silicon oxide, silicon nitride.
Described top layer electrode is by running through the via of described protective layer, bottom electrode and flatness layer and described drain contact.
The material of described top layer electrode and bottom electrode is ITO.
Beneficial effects of the present invention: the manufacture method of a kind of low temperature polycrystalline silicon tft array substrate provided by the invention is processed by double photoresistance ashing and removing photoresistance to be removed totally by the solidification photoresistance remained after ion doping completely, effectively solve photoresist layer some region before first time ashing processes to be likely to be coated with impurity particle and stop that first time ashing processes the problem solidifying photoresistance residual caused, the interface cleanness degree of gate insulator and interlayer insulating film can be improved, it is to avoid the product yield that interface problem causes declines.
Accompanying drawing explanation
In order to be able to be further understood that inventive feature and technology contents, refer to the detailed description below in connection with the present invention and accompanying drawing, but accompanying drawing only provides reference and use is described, be not used for the present invention is any limitation as.
In accompanying drawing,
Fig. 1 is the flow chart of the manufacture method of the low temperature polycrystalline silicon tft array substrate of the present invention;
Fig. 2 is the schematic diagram of the step 1 of the manufacture method of the low temperature polycrystalline silicon tft array substrate of the present invention;
Fig. 3 is the schematic diagram of the step 2 of the manufacture method of the low temperature polycrystalline silicon tft array substrate of the present invention;
Fig. 4 is the schematic diagram of the step 3 of the manufacture method of the low temperature polycrystalline silicon tft array substrate of the present invention;
Fig. 5 is the schematic diagram of the step 4 of the manufacture method of the low temperature polycrystalline silicon tft array substrate of the present invention;
Fig. 6 is the schematic diagram of the step 5 of the manufacture method of the low temperature polycrystalline silicon tft array substrate of the present invention;
Fig. 7 is the schematic diagram of the step 6 of the manufacture method of the low temperature polycrystalline silicon tft array substrate of the present invention;
Fig. 8 is the schematic diagram of the step 7 of the manufacture method of the low temperature polycrystalline silicon tft array substrate of the present invention.
Detailed description of the invention
For further setting forth the technological means and effect thereof that the present invention takes, it is described in detail below in conjunction with the preferred embodiments of the present invention and accompanying drawing thereof.
Referring to Fig. 1, the present invention provides the manufacture method of a kind of low temperature polycrystalline silicon tft array substrate, comprises the steps:
Step 1, as shown in Figure 2 a, it is provided that underlay substrate 10, forms the light shield layer 11 of patterning on described underlay substrate 10, and on described light shield layer 11 with underlay substrate 10, deposition covers insulating buffer layer 12.
Specifically, described underlay substrate 10 is preferably glass substrate; The material of described light shield layer 11 is lighttight metal; The material of described insulating buffer layer 12 is one or both the compound in silicon oxide (SiOx), silicon nitride (SiNx), it is preferred that described insulating buffer layer 12 includes silicon nitride layer and the silicon oxide layer that stacking from bottom to top is arranged.
Step 2 as it is shown on figure 3, form the low-temperature polycrystalline silicon layer 20 of patterning corresponding to described light shield layer 11 on described insulating buffer layer 12.
Specifically, the detailed process of this step 2 is: first deposit one layer of non-crystalline silicon on described insulating buffer layer 12, again through quasi-molecule laser annealing (ExcimerLaserAnnealing, or solid-phase crystallization (SolidPhaseCrystallization ELA), etc. SPC) non-crystalline silicon is carried out Crystallizing treatment by mode, make recrystallized amorphous silicon be changed into low temperature polycrystalline silicon, then pass through lithographic process and obtain the low-temperature polycrystalline silicon layer 20 of described patterning.
Step 3, as shown in Figure 4, coating photoresist on described low-temperature polycrystalline silicon layer 20 with insulating buffer layer 12, by exposing, developing manufacture process pattern described photoresist, form photoresist layer 30, expose two end regions of at least part of low-temperature polycrystalline silicon layer 20.
It is noted that if the final low temperature polycrystalline silicon tft array substrate prepared of design only includes N-type or the monotype TFT of P type, then in this step 3, the photoresist layer 30 of patterning should expose two end regions of whole low-temperature polycrystalline silicon layer 20;If the final low temperature polycrystalline silicon tft array substrate prepared of design not only includes N-type TFT but also include P type TFT, then in this step 3, the photoresist layer 30 of patterning should expose two end regions of part low-temperature polycrystalline silicon layer 20.
Step 4, as shown in Figure 5, with described photoresist layer 30 for shielding layer, two end regions of corresponding low-temperature polycrystalline silicon layer 20 are carried out a type of ion doping, form low-temperature polysilicon silicon semiconductor layer 20 ', wherein become the source drain contact district of polysilicon semiconductor layer 20 ' through the region of ion doping, become the channel region of polysilicon semiconductor layer 20 ' without the region of ion doping.
It is noted that if the final low temperature polycrystalline silicon tft array substrate prepared of design only includes N-type TFT, then a type of ion doping described in this step 4 is the N-type ion doping of Doping Phosphorus (P) ion; If the final low temperature polycrystalline silicon tft array substrate prepared of design only includes P type TFT, then a type of ion doping described in this step 4 is the P type ion doping of doped with boron (B) ion; If the final low temperature polycrystalline silicon tft array substrate prepared of design not only includes N-type TFT but also include P type TFT, then a type of ion doping described in this step 4 is the one of which of N-type ion doping, P type ion doping.
As shown in Figure 5, the ion doping process of this step 4 can cause impurity particle to cover some region of photoresist layer 30.
Step 5, carry out first time photoresistance ashing and removing photoresistance process.
As shown in Figure 6, after this step 5 completes first time photoresistance ashing and removing photoresistance process, the impurity particle produced in above-mentioned steps 4 and the part photoresist layer 30 not covered by impurity particle can be removed, but the region that photoresist layer 30 is covered by impurity particle then can remain solidification photoresistance owing to impurity particle blocks photoresistance ashing.
Step 6, carry out second time photoresistance ashing and removing photoresistance process.
As described in Figure 7, this step 6 carries out photoresistance ashing again and removing photoresistance processes the solidification photoresistance remained after can removing first time photoresistance ashing and removing photoresistance process, thus completely eliminated photoresist layer 30, the interface of cleaning is provided, it is to avoid interface problem causes that peeling off and crackle etc. occurs in gate insulator for follow-up gate insulator film forming.
Step 7, as shown in Figure 8, makes gate insulator 31, grid 41, interlayer insulating film 32, source/drain 42, flatness layer 50, bottom electrode 60, protective layer 70 and top layer electrode 80 successively in described low-temperature polysilicon silicon semiconductor layer 20 ' and insulating buffer layer 12.
It is noted that if the final low temperature polycrystalline silicon tft array substrate prepared of design only includes N-type TFT or P type TFT, then this step 7 only makes above-mentioned each rete successively, if the final low temperature polycrystalline silicon tft array substrate prepared of design not only includes N-type TFT but also include P type TFT, then this step 7 is after completing making grid 41, it is additionally included on grid 41 and gate insulator 31 and is coated with and patterns photoresist, form another photoresist layer, with another photoresist layer described for shielding layer, two end regions of the remaining low-temperature polycrystalline silicon layer 20 carrying out ion doping without step 4 are carried out another type of ion doping, form low-temperature polysilicon silicon semiconductor layer, and the process that double photoresistance ashing and removing photoresistance process, the interface of cleaning is provided for follow-up interlayer insulating film 32 film forming, peeling off and crackle etc. occurs in interlayer insulating film 32 to avoid interface problem to cause, make described interlayer insulating film 32 afterwards again.Further, if what carry out in described step 4 is N-type ion doping, then this step 7 carries out P type ion doping; If what carry out in described step 4 is P type ion doping, then this step 7 carries out N-type ion doping.
Specifically, described source/drain 42 contacts respectively through the two ends of the via with described low-temperature polysilicon silicon semiconductor layer 20 ' that run through interlayer insulating film 32 and gate insulator 31.
Described top layer electrode 80 is by running through the via 81 of described protective layer 70, bottom electrode 60 and flatness layer 50 and described drain contact.
One or both the compound that the material of described gate insulator 31, interlayer insulating film 32, flatness layer 50 and protective layer 70 is in silicon oxide, silicon nitride.
The material of described top layer electrode 80 and bottom electrode 60 is tin indium oxide (IndiumTinOxide, ITO).
In sum, the manufacture method of the low temperature polycrystalline silicon tft array substrate of the present invention is processed by double photoresistance ashing and removing photoresistance to be removed totally by the solidification photoresistance remained after ion doping completely, effectively solve photoresist layer some region before first time ashing processes to be likely to be coated with impurity particle and stop that first time ashing processes the problem solidifying photoresistance residual caused, the interface cleanness degree of gate insulator and interlayer insulating film can be improved, it is to avoid the product yield that interface problem causes declines.
The above, for the person of ordinary skill of the art, it is possible to conceive according to technical scheme and technology and make other various corresponding changes and deformation, and all these change and deform the protection domain that all should belong to the claims in the present invention.

Claims (9)

1.一种低温多晶硅TFT阵列基板的制作方法，其特征在于，包括如下步骤：1. A method for manufacturing a low-temperature polysilicon TFT array substrate, characterized in that, comprising the steps: 步骤1、提供一衬底基板(10)，在所述衬底基板(10)上形成图案化的遮光层(11)，在所述遮光层(11)与衬底基板(10)上沉积覆盖绝缘缓冲层(12)；Step 1. Provide a base substrate (10), form a patterned light-shielding layer (11) on the base substrate (10), and deposit a covering layer on the light-shielding layer (11) and the base substrate (10). Insulating buffer layer (12); 步骤2、在所述绝缘缓冲层(12)上形成对应于所述遮光层(11)的图案化的低温多晶硅层(20)；Step 2, forming a patterned low-temperature polysilicon layer (20) corresponding to the light shielding layer (11) on the insulating buffer layer (12); 步骤3、在所述低温多晶硅层(20)与绝缘缓冲层(12)上涂布光阻材料，图案化所述光阻材料，形成光阻层(30)，暴露出至少部分低温多晶硅层(20)的两端区域；Step 3, coating a photoresist material on the low temperature polysilicon layer (20) and the insulating buffer layer (12), patterning the photoresist material to form a photoresist layer (30), exposing at least part of the low temperature polysilicon layer ( 20) both end regions; 步骤4、以所述光阻层(30)为遮蔽层，对相应低温多晶硅层(20)的两端区域进行一种类型的离子掺杂，形成低温多晶硅半导体层(20’)；Step 4, using the photoresist layer (30) as a shielding layer, performing a type of ion doping on the two end regions of the corresponding low-temperature polysilicon layer (20) to form a low-temperature polysilicon semiconductor layer (20'); 步骤5、进行第一次光阻灰化和去光阻处理；Step 5, performing the first photoresist ashing and photoresist removal treatment; 步骤6、进行第二次光阻灰化和去光阻处理，以完全去除光阻层(30)；Step 6, performing a second photoresist ashing and photoresist removal treatment to completely remove the photoresist layer (30); 步骤7、在所述低温多晶硅半导体层(20’)及绝缘缓冲层(12)上依次制作栅极绝缘层(31)、栅极(41)、层间绝缘层(32)、源/漏极(42)、平坦层(50)、底层电极(60)、保护层(70)、及顶层电极(80)。Step 7, sequentially fabricate a gate insulating layer (31), a gate (41), an interlayer insulating layer (32), and a source/drain on the low-temperature polysilicon semiconductor layer (20') and the insulating buffer layer (12) (42), flat layer (50), bottom electrode (60), protective layer (70), and top electrode (80). 2.如权利要求1所述的低温多晶硅TFT阵列基板的制作方法，其特征在于，所述步骤7在完成制作栅极(41)后，还包括在栅极(41)与栅极绝缘层(31)上涂布并图案化光阻材料，形成另一光阻层，以所述另一光阻层为遮蔽层，对未经步骤4进行离子掺杂的剩余的低温多晶硅层(20)的两端区域进行另一种类型的离子掺杂，形成低温多晶硅半导体层(20’)，及连续两次的光阻灰化和去光阻处理的过程，之后再制作所述层间绝缘层(32)。2. the manufacture method of low-temperature polysilicon TFT array substrate as claimed in claim 1, is characterized in that, described step 7 also comprises after gate (41) is made, after gate (41) and gate insulating layer ( 31) Coating and patterning a photoresist material on top to form another photoresist layer, using the other photoresist layer as a shielding layer, for the remaining low-temperature polysilicon layer (20) that has not been ion-doped in step 4 Another type of ion doping is performed on the regions at both ends to form a low-temperature polysilicon semiconductor layer (20'), and two consecutive photoresist ashing and photoresist removal processes are performed, and then the interlayer insulating layer ( 32). 3.如权利要求1所述的低温多晶硅TFT阵列基板的制作方法，其特征在于，所述步骤2中图案化的低温多晶硅层(20)的具体制作过程为：先在所述绝缘缓冲层(12)上沉积一层非晶硅，再对非晶硅进行晶化处理，制得低温多晶硅，然后通过光刻制程得到图案化的低温多晶硅层(20)。3. the manufacturing method of low-temperature polysilicon TFT array substrate as claimed in claim 1, is characterized in that, the specific manufacturing process of the patterned low-temperature polysilicon layer (20) in the described step 2 is: first in the described insulating buffer layer ( 12) Deposit a layer of amorphous silicon on it, and then crystallize the amorphous silicon to produce low-temperature polysilicon, and then obtain a patterned low-temperature polysilicon layer (20) through a photolithography process. 4.如权利要求1所述的低温多晶硅TFT阵列基板的制作方法，其特征在于，所述步骤3中通过曝光、显影制程图案化所述光阻材料得到所述光阻层(30)。4. The method for manufacturing a low-temperature polysilicon TFT array substrate according to claim 1, characterized in that, in said step 3, said photoresist layer (30) is obtained by patterning said photoresist material through exposure and development processes. 5.如权利要求2所述的低温多晶硅TFT阵列基板的制作方法，其特征在于，步骤4中所述的一种类型的离子掺杂为掺杂磷离子的N型离子掺杂或掺杂硼离子的P型离子掺杂；步骤7中所述另一种类型的离子掺杂为不同于步骤4的P型离子掺杂或N型离子掺杂。5. The manufacturing method of low-temperature polysilicon TFT array substrate as claimed in claim 2, is characterized in that, one type of ion doping described in step 4 is N-type ion doping or doping boron doped with phosphorus ions P-type ion doping of ions; another type of ion doping described in step 7 is P-type ion doping or N-type ion doping different from step 4. 6.如权利要求1所述的低温多晶硅TFT阵列基板的制作方法，其特征在于，所述源/漏极(42)分别通过贯穿层间绝缘层(32)和栅极绝缘层(31)的过孔与所述低温多晶硅半导体层(20’)的两端相接触。6. the manufacture method of low-temperature polysilicon TFT array substrate as claimed in claim 1 is characterized in that, described source/drain (42) passes through interlayer insulating layer (32) and gate insulating layer (31) respectively The via holes are in contact with both ends of the low temperature polysilicon semiconductor layer (20'). 7.如权利要求1所述的低温多晶硅TFT阵列基板的制作方法，其特征在于，所述绝缘缓冲层(12)、栅极绝缘层(31)、层间绝缘层(32)、平坦层(50)、及保护层(70)的材料均为氧化硅、氮化硅中的一种或两种的复合。7. the manufacture method of low-temperature polysilicon TFT array substrate as claimed in claim 1 is characterized in that, described insulating buffer layer (12), gate insulating layer (31), interlayer insulating layer (32), flat layer ( 50) and the protective layer (70) are made of one or a combination of silicon oxide and silicon nitride. 8.如权利要求1所述的低温多晶硅TFT阵列基板的制作方法，其特征在于，所述顶层电极(80)通过贯穿所述保护层(70)、底层电极(60)、及平坦层(50)的过孔(81)与所述漏极接触。8. The method for manufacturing a low-temperature polysilicon TFT array substrate as claimed in claim 1, wherein the top layer electrode (80) passes through the protection layer (70), the bottom electrode (60), and the flat layer (50). ) via hole (81) is in contact with the drain. 9.如权利要求1所述的低温多晶硅TFT阵列基板的制作方法，其特征在于，所述顶层电极(80)和底层电极(60)的材料均为ITO。9. The manufacturing method of the low-temperature polysilicon TFT array substrate according to claim 1, characterized in that, the materials of the top electrode (80) and the bottom electrode (60) are both ITO.
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CN108538860A (en) * 2018-04-27 2018-09-14 武汉华星光电技术有限公司 Manufacturing method of top-gate amorphous silicon TFT substrate
WO2018176829A1 (en) * 2017-03-29 2018-10-04 Boe Technology Group Co., Ltd. Thin film transistor and display substrate, fabrication method thereof, and display device
WO2019056517A1 (en) * 2017-09-21 2019-03-28 深圳市华星光电半导体显示技术有限公司 Thin film transistor structure and fabrication method therefor
CN109643657A (en) * 2017-06-22 2019-04-16 深圳市柔宇科技有限公司 The production method of the making apparatus and array substrate of array substrate

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