CN106165103B - 半导体器件及半导体器件的制造方法 - Google Patents

半导体器件及半导体器件的制造方法 Download PDF

Info

Publication number
CN106165103B
CN106165103B CN201580018706.3A CN201580018706A CN106165103B CN 106165103 B CN106165103 B CN 106165103B CN 201580018706 A CN201580018706 A CN 201580018706A CN 106165103 B CN106165103 B CN 106165103B
Authority
CN
China
Prior art keywords
region
type
area
trench
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201580018706.3A
Other languages
English (en)
Chinese (zh)
Other versions
CN106165103A (zh
Inventor
高谷秀史
斋藤顺
添野明高
山本敏雅
副岛成雅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Toyota Motor Corp
Original Assignee
Denso Corp
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp, Toyota Motor Corp filed Critical Denso Corp
Publication of CN106165103A publication Critical patent/CN106165103A/zh
Application granted granted Critical
Publication of CN106165103B publication Critical patent/CN106165103B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/118—Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CN201580018706.3A 2014-04-09 2015-02-10 半导体器件及半导体器件的制造方法 Active CN106165103B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014-080012 2014-04-09
JP2014080012A JP6231422B2 (ja) 2014-04-09 2014-04-09 半導体装置
PCT/JP2015/053693 WO2015156024A1 (ja) 2014-04-09 2015-02-10 半導体装置及び半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN106165103A CN106165103A (zh) 2016-11-23
CN106165103B true CN106165103B (zh) 2019-07-16

Family

ID=54287605

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580018706.3A Active CN106165103B (zh) 2014-04-09 2015-02-10 半导体器件及半导体器件的制造方法

Country Status (5)

Country Link
US (1) US9853139B2 (2)
JP (1) JP6231422B2 (2)
CN (1) CN106165103B (2)
DE (1) DE112015001751B4 (2)
WO (1) WO2015156024A1 (2)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9991379B1 (en) * 2016-11-17 2018-06-05 Sanken Electric Co., Ltd. Semiconductor device with a gate insulating film formed on an inner wall of a trench, and method of manufacturing the same
US9887287B1 (en) * 2016-12-08 2018-02-06 Cree, Inc. Power semiconductor devices having gate trenches with implanted sidewalls and related methods
JP6871747B2 (ja) * 2017-01-30 2021-05-12 株式会社東芝 半導体装置及びその製造方法
JP7190256B2 (ja) 2018-02-09 2022-12-15 ローム株式会社 半導体装置
CN111384168A (zh) 2018-12-27 2020-07-07 无锡华润华晶微电子有限公司 沟槽mosfet和沟槽mosfet的制造方法
US11158703B2 (en) * 2019-06-05 2021-10-26 Microchip Technology Inc. Space efficient high-voltage termination and process for fabricating same
IT201900013416A1 (it) 2019-07-31 2021-01-31 St Microelectronics Srl Dispositivo di potenza a bilanciamento di carica e procedimento di fabbricazione del dispositivo di potenza a bilanciamento di carica
JP7363539B2 (ja) * 2020-01-31 2023-10-18 株式会社デンソー 窒化物半導体装置の製造方法
US12094926B2 (en) 2020-08-14 2024-09-17 Wolfspeed, Inc. Sidewall dopant shielding methods and approaches for trenched semiconductor device structures
US11355630B2 (en) 2020-09-11 2022-06-07 Wolfspeed, Inc. Trench bottom shielding methods and approaches for trenched semiconductor device structures
EP4465365A1 (en) * 2023-05-17 2024-11-20 Infineon Technologies Austria AG Vertical power semiconductor device
CN116544268B (zh) * 2023-07-06 2023-09-26 通威微电子有限公司 一种半导体器件结构及其制作方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101401212A (zh) * 2006-03-08 2009-04-01 丰田自动车株式会社 绝缘栅极型半导体器件及其制造方法
US20120037954A1 (en) * 2010-08-10 2012-02-16 Force Mos Technology Co Ltd Equal Potential Ring Structures of Power Semiconductor with Trenched Contact

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2314206A (en) * 1996-06-13 1997-12-17 Plessey Semiconductors Ltd Preventing voltage breakdown in semiconductor devices
EP1267415A3 (en) 2001-06-11 2009-04-15 Kabushiki Kaisha Toshiba Power semiconductor device having resurf layer
JP4728508B2 (ja) * 2001-06-11 2011-07-20 株式会社東芝 縦型電力用半導体素子の製造方法
JP5309427B2 (ja) * 2006-04-24 2013-10-09 富士電機株式会社 半導体装置
JP5633992B2 (ja) * 2010-06-11 2014-12-03 トヨタ自動車株式会社 半導体装置および半導体装置の製造方法
JP2012195394A (ja) * 2011-03-16 2012-10-11 Toshiba Corp 半導体装置の製造方法
JP5742657B2 (ja) 2011-10-20 2015-07-01 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
JP5758824B2 (ja) 2012-03-14 2015-08-05 トヨタ自動車株式会社 半導体装置および半導体装置の製造方法
JP5754543B2 (ja) * 2012-03-16 2015-07-29 富士電機株式会社 半導体装置
JP2013201287A (ja) * 2012-03-26 2013-10-03 Toshiba Corp パワー半導体装置
JP2013258327A (ja) * 2012-06-13 2013-12-26 Toshiba Corp 半導体装置及びその製造方法
JP5751213B2 (ja) 2012-06-14 2015-07-22 株式会社デンソー 炭化珪素半導体装置およびその製造方法
KR20140022518A (ko) 2012-08-13 2014-02-25 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9496382B2 (en) * 2013-11-21 2016-11-15 Chengdu Monolithic Power Systems Co., Ltd. Field effect transistor, termination structure and associated method for manufacturing
US9406543B2 (en) * 2013-12-10 2016-08-02 Samsung Electronics Co., Ltd. Semiconductor power devices and methods of manufacturing the same
US9478606B2 (en) * 2014-02-13 2016-10-25 Microsemi Corporation SiC transient voltage suppressor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101401212A (zh) * 2006-03-08 2009-04-01 丰田自动车株式会社 绝缘栅极型半导体器件及其制造方法
US20120037954A1 (en) * 2010-08-10 2012-02-16 Force Mos Technology Co Ltd Equal Potential Ring Structures of Power Semiconductor with Trenched Contact

Also Published As

Publication number Publication date
US20170018643A1 (en) 2017-01-19
DE112015001751T5 (de) 2017-02-09
CN106165103A (zh) 2016-11-23
US9853139B2 (en) 2017-12-26
WO2015156024A1 (ja) 2015-10-15
JP2015201557A (ja) 2015-11-12
JP6231422B2 (ja) 2017-11-15
DE112015001751B4 (de) 2021-03-18

Similar Documents

Publication Publication Date Title
JP6231422B2 (ja) 半導体装置
US9755042B2 (en) Insulated gate semiconductor device and method for manufacturing the insulated gate semiconductor device
JP6169966B2 (ja) 半導体装置及び半導体装置の製造方法
US9640651B2 (en) Semiconductor device and method of manufacturing semiconductor device
KR101840961B1 (ko) 반도체 장치
CN103325818A (zh) 半导体装置及其制造方法
JP6493372B2 (ja) 半導体装置
WO2016009736A1 (ja) スイッチング素子
CN105633162A (zh) 半导体装置以及半导体装置的制造方法
US20160141409A1 (en) Semiconductor device and method for manufacturing semiconductor device
JP2017191817A (ja) スイッチング素子の製造方法
JP5842896B2 (ja) 半導体装置
JP2022100379A (ja) 半導体装置とその製造方法
JP2020064910A (ja) スイッチング素子
CN110945633A (zh) 半导体装置
JP2019176104A (ja) スイッチング素子
KR102183362B1 (ko) 높은 항복 전압을 갖는 트렌치 모스펫을 포함하는 반도체 장치
JP2020096082A (ja) 半導体装置
JP2022139144A (ja) 半導体装置
JP6215152B2 (ja) 半導体装置
JP2019040960A (ja) 窒化物半導体装置
JP2018056380A (ja) スイッチング素子
JP2017188562A (ja) スイッチング素子とその製造方法
JP2016096286A (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant