CN106777571A - A kind of FPGA algorithmic block automatic Verification platform realized based on System Verilog - Google Patents

Abstract

The invention provides a programmable logic algorithm block automatic verification platform based on System Verilog, which includes a top-level test module, a test stimulus automatic generation module, a virtual interface connection module, an algorithm library, a reference model establishment module and an automatic inspection module. The top-level test module starts the test command, the data is generated in the stimulus automatic generation module, and transmitted to the object under test and the reference model through the virtual interface connection module, the object under test receives the data and processes it according to the requirements, and the reference model also processes the data, and finally The data generated by the measured object and the reference model are transmitted to the automatic inspection module through the virtual interface connection module for comparison processing, and the inspection module outputs the comparison result. The invention adopts the virtual interface of the Systerm Verilog to separate the test platform from the object to be tested, so that the test platform does not change greatly with the change of the test object, and the reuse rate is high.

Description

A Programmable Logic Algorithm Block Automation Test Based on System Verilog certificate platform

technical field

The invention relates to the field of nuclear power plant FPGA simulation test, in particular to a programmable logic algorithm block automatic verification platform realized based on System Verilog.

Background technique

General nuclear power plant instrumentation and control equipment will involve the configuration of algorithm blocks. In order to ensure the correctness of the algorithm block, it is necessary to conduct a detailed test on the algorithm block. There are many algorithm blocks involved in the configuration algorithm diagram, and as many examples as possible for each module are given to ensure that the algorithm block is used in various case works correctly. If the test is done by manually inputting incentives and then checking, it will lead to incomplete coverage of test cases and waste a lot of human resources.

There are currently automated tests for algorithm block testing, through the generation of random test stimuli, reference model building, and real-time comparison of the final collected results with the output results of the reference model to achieve automated inspection. Generally, this kind of automatic setting is to carry out the test for a single tested object, or the tested objects have the same input and output interfaces, or the functions of the tested objects are similar.

However, the algorithm blocks have many functions, and the input interface forms of different algorithm blocks are different, resulting in low reusability of the test platform. Each time a module is tested, input data in different formats needs to be produced, and the expected value corresponding to the input stimulus needs to be calculated. , greatly reducing the efficiency of automated testing.

The DUT object tested by the traditional automated test platform is fixed, or the input and output interfaces are similar, but when the test object with many interface changes and large function changes is simulated, the platform will be modified on a large scale to make the platform reusable. Low, the test stimulus has no randomness, and the form diversity of the input interface of the test module leads to a reduction in the degree of automation.

Contents of the invention

The purpose of the present invention is exactly at the situation of above-mentioned prior art, has proposed a kind of automatic verification platform of programmable logic algorithm block realized based on System Verilog, by using the mode of System Verilog virtual interface, realizes the reusability of platform, reduces due to test object The change of the platform is too large, which affects the efficiency of the test.

The purpose of the present invention is achieved through the following technical solutions: a programmable logic algorithm block automation verification platform realized based on System Verilog, including a top-level test module, a test stimulus automatic generation module, a virtual interface connection module, an algorithm library, and a reference model Build modules and automatically check modules;

The top-level test module is used to declare an interface, and is used to call the test stimulus automatic generation module, virtual interface connection module, algorithm library, reference model establishment module and automatic inspection module;

The virtual interface connection module is used to declare the virtual interface connected to the test stimulus automatic generation module, the reference model building module, the automatic inspection module and the measured object, and classify these virtual interfaces, and the test stimulus automatic generation module, the reference The model building module is connected with the automatic inspection module to establish tasks for automatic execution;

The test stimulus automatic generation module is used for the generation of test stimulus, the input data is randomly generated or constrained to stimulate the range, and the test stimulus data is passed to the measured object and the reference model through the virtual interface;

The algorithm library is used to store algorithms commonly used by the reference model building module to build reference models;

The reference model building module is used to call an algorithm from the algorithm library to establish a reference model corresponding to the measured object, process the expected data, and pass the processed data to the automatic inspection module through the virtual interface;

The automatic checking module is used for automatically comparing the real-time data output by the measured object with the expected data output by the reference model.

Further, the algorithm library is also connected with the C language through the DPI interface, and calls the mathematical functions in the C language.

Further, the algorithm of the algorithm library is set according to the object to be tested, including absolute value calculation, binary search method, and conversion algorithm of integer and real data.

The beneficial effects of the present invention are:

The invention adopts the method of Systerm Verilog virtual interface to separate the test platform from the object to be tested, and the modules inside the test platform are all connected by virtual interfaces, thereby ensuring the independence of each part. This avoids design changes and brings major changes to the test platform. The construction of this test platform is suitable for the testing of various algorithm blocks, which improves the efficiency of verification. In addition, this platform has strong flexibility. The influence of the signal, in order to improve the verification efficiency, establish an aman_interface, including all input signals and an enable signal, when the enable signal changes, all input signals change accordingly.

Using the above platform, when verifying algorithm blocks with different interfaces and functions, it is only necessary to modify the functions of the reference model and the type of the interface of the object under test to complete the verification of individual modules.

In addition, for the construction of the reference model of the algorithm block, use the DPI interface between System Verilog and the C language library function, call the commonly used mathematical functions in the C language, such as exp, power, log, abs to build a common algorithm library for the verification platform, and assist the tested Object reference model establishment.

Description of drawings

Fig. 1 is a platform architecture diagram of a programmable logic algorithm block automatic verification platform realized based on System Verilog of the present invention;

FIG. 2 is a data flow diagram of an automated verification platform for programmable logic algorithm blocks implemented based on System Verilog in the present invention.

detailed description

A kind of programmable logic algorithm block automatic verification platform realized based on System Verilog of the present invention will be further described below in conjunction with accompanying drawings: this embodiment is only used to illustrate the present invention and is not intended to limit the scope of the present invention, those skilled in the art will understand the scope of the present invention Modifications in various equivalent forms fall within the scope defined by the appended claims of the present application.

As shown in Figure 1, it is a programmable logic algorithm block automatic verification platform realized based on System Verilog according to the present invention, including a top-level test module, a test stimulus automatic generation module, a virtual interface connection module, an algorithm library, and a reference model establishment modules and auto-check modules;

The top-level test module is used to declare the interface, connect the interface connected by the tested object to the verification platform, and start the operation of the verification platform; the top-level test module calls the test incentive automatic generation module, virtual interface connection module, algorithm library, Reference model building blocks and automatic checking blocks, as follows:

Import alg_pkg::*;

`include "real_sig_if.sv"

`include "bool_sig_if.sv"

`include "real_sig.sv"

`include "bool_sig.sv"

`include "bool_aman_if.sv"

`include "bool_aman_sig.sv"

`include "autocheck.sv"

`include "auto_stimula.sv"

`include "test_bench.sv"

....

The virtual interface connection module is used to declare the virtual interface connected to the test stimulus automatic generation module, the reference model building module, the automatic inspection module and the measured object, and classify these virtual interfaces, and the test stimulus generation module and the reference model building module Connect with the automatic inspection module to create an automatic execution task, as follows:

The test stimulus automatic generation module is used for the generation of test stimulus, randomizes the input data to generate or constrains the range of stimulus, and transmits the data of test stimulus to the measured object and the reference model through the virtual interface.

The algorithm library is used to store the commonly used algorithms for building reference models, which are set according to the characteristics of the tested object, such as absolute value calculations, binary search methods, data integer and real-type conversion algorithms, etc.; The algorithm library is also connected with the C language through the DPI interface, and calls the mathematical functions in the C language.

The data type input to the measured object is generally defined by the designer himself. In the reference model, this data type needs to be converted into a real number to facilitate later data processing. This algorithm is written into the algorithm library and reference model. It can be called and used directly; in addition, the binary search method used in the algorithm block can also be written into the algorithm library with System Verilog. As follows:

Class math_alg;

static function real bits_to_real(bit[29:0]bits);

 …

End funcion

End class

The reference model establishment module is used to call data from the algorithm library to establish a reference model corresponding to the measured object, process the expected data, and transmit the processed data to the automatic inspection module through the virtual interface.

The automatic checking module is used for automatically comparing the real-time data output by the measured object with the expected data output by the reference model.

In the top-level test module, the interface declaration is made, and the algorithm blocks to be tested are counted. There are two data types used, one is real_sig, and the other is bool_sig. The real_sig data type includes the enable bit ena of the data, and the quality bit quality. Range selection bit select, value bit value, bool_sig data type includes enable signal ena_l, quality bit quality_l, value bit value_l, establish the following interface declaration:

Establish an interface-driven transaction processor to facilitate the call of the test stimulus automatic generation module, such as bool_sig:

The invention uses a virtual interface to separate the verification platform from the object to be tested, thereby reducing the influence of design changes on the test platform. There are many types of algorithm blocks tested, and the interfaces are also different. When the interface name changes, users do not need to modify the method of driving this port by using this platform. They only need to bind the virtual interface to the corresponding physical interface in the top-level test module. , and modify the reference model. The flow of data during the test is shown in Figure 2.

When the test is executed, the test execution is started by the top-level test module. First, the data is generated in the stimulus automatic generation module and transmitted to the DUT and the reference model through the virtual interface connection module. The DUT under test processes the data after receiving the data, and the reference model also processes the data. Finally, the data generated by the DUT under test and the reference model is transmitted to the automatic inspection module through the virtual port connection module for comparison processing, and the output ratio of the inspection module is If the result is correct, the test is complete.

The key point of the present invention is to use the connection mode of the virtual interface in the test platform and the object under test, the advantages of the present invention:

(1) Use the virtual interface of System Verilog to separate the test platform from the tested object, so that the test platform does not change greatly with the change of the test object;

(2) This test platform is relatively flexible. For different algorithm block tests, it only needs to modify the object under test and check the function to realize the test of the algorithm block. In the experiment, the test platform was used to complete the test of 96 algorithm blocks. The effect is ideal;

(3) This verification platform contains an algorithm library. To test different modules, write a reference model or check function, and call the relevant algorithm library to improve the verification efficiency.

Embodiment 1: Verification of POW (power function) algorithm block

The POW algorithm block has two inputs, base and power, and one output. The three input types are in long real format. First, define the interface as real_sig_if. In the virtual interface connection module, declare the input, output, and input signals of the virtual interface type to be connected to the test stimulus automatic generation module and the automatic inspection module respectively. The output signal is connected to the automatic test stimulus module. The inspection modules are connected, and the top-level test module declares the input and output interface signals, which are respectively connected to the corresponding signals of the measured object and the virtual interface connection module. Call the test stimulus automatic generation module, which calls the random generation function randomize to generate the input data type that meets the requirements. In the reference model building module, according to the data format requirements, call the bits_to_real function in the algorithm library to convert the input data into corresponding real numbers. Then use the DPI interface to call the POW function in C language to complete the establishment of the POW module reference model, calculate the expected output value, and compare this value with the output value of the DUT in the automatic inspection module, and the error is within the required range If it is within the range, the test is passed; if it is not within the required range, it is not passed.

Embodiment 2: verification of simulated manual algorithm block

The analog manual algorithm block includes 6 bool_signal type inputs, 10 real type parameter inputs and 5 bool_signal type outputs. The 6 input signals are controlled by the signal ena. When ena changes, the 6 input signals change together. According to this characteristic, create an interface declaration of bool_aman_if, including a bool type enable signal, and 6 input signals. The input signal of bool_aman_if, the actual parameter input of type real_sig_if, and the output signal of bool_sig_if are declared in the top-level test module. Call the virtual interface connection module in the top-level module to realize the connection between the interface of the object under test and the virtual interface connection module, call the test stimulus automatic generation module and the automatic inspection module, and connect the two modules through the virtual interface connection module. Call the random function in the test stimulus generation module to generate random test cases; the reference model building module calls the pre-written function in the algorithm library to build a reference model with the same function as the aman module; the aman_alg::av_alg function realizes the core function, the valve position The output is output as required by the set rate. The automatic inspection module receives the measured object and the result output by the reference model building module for automatic comparison processing, outputs the comparison result, and the test is completed.

Claims (3)

1. A programmable logic algorithm block automatic verification platform realized based on System Verilog, characterized in that it comprises a top-level test module, a test stimulus automatic generation module, a virtual interface connection module, an algorithm library, a reference model building module and an automatic inspection module; The top-level test module is used to declare an interface, and is used to call the test stimulus automatic generation module, virtual interface connection module, algorithm library, reference model establishment module and automatic inspection module; The virtual interface connection module is used to declare the virtual interface connected to the test stimulus automatic generation module, the reference model building module, the automatic inspection module and the measured object, and classify these virtual interfaces, and the test stimulus automatic generation module, the reference The model building module is connected with the automatic inspection module to establish tasks for automatic execution; The test stimulus automatic generation module is used for the generation of test stimulus, the input data is randomly generated or constrained to stimulate the range, and the test stimulus data is passed to the measured object and the reference model through the virtual interface; The algorithm library is used to store algorithms commonly used by the reference model building module to build reference models; The reference model building module is used to call an algorithm from the algorithm library to establish a reference model corresponding to the measured object, process the expected data, and pass the processed data to the automatic inspection module through the virtual interface; The automatic checking module is used for automatically comparing the real-time data output by the measured object with the expected data output by the reference model. 2. a kind of programmable logic algorithm block automatic verification platform realized based on System Verilog according to claim 1, is characterized in that, described algorithm storehouse is also connected with C language by DPI interface, calls the mathematical function in C language . 3. A kind of programmable logic algorithm block automatic verification platform realized based on System Verilog according to claim 1 or 3, is characterized in that, the algorithm of described algorithm storehouse is set according to the object under test, comprises taking absolute value operation , binary search method, data integer and real conversion algorithm.