CN106919462A - A kind of method and device for generating processor fault record - Google Patents

Abstract

The application is related to computer realm, more particularly to a kind of method and device for generating processor fault record.In a kind of method for generating processor fault record, the processing unit that control chip is detected in CPU stops response, IA in the current program counter PC of the processing unit is obtained by JTAG passages, and a first kind list item for including the IA in the current PC is created, record in IA table.When the list item quantity recorded in the IA table reaches preset value, the control chip triggers the CPU and interrupts.The scheme that the application is provided, can provide more information, so as to improve the efficiency of accident analysis for processor fault analysis.

Description

A method and device for generating processor fault records

technical field

The present application relates to the field of computers, in particular to a method and device for generating processor fault records.

Background technique

The central processing unit (CPU) is the computing core and control core of devices with data processing functions such as computers and servers. A CPU in a device is connected to a memory in the device through a bus, and processes data by interpreting and executing program instructions in the memory.

The existing CPU usually includes an arithmetic logic unit (arithmetic logic unit, ALU), a register (register), a cache memory (Cache), and a data, control, and status bus (bus) for realizing the connection among the three.

In the program run by the CPU, a series of instructions will be executed repeatedly until a preset condition in the program is reached. During actual operation, due to design defects or unforeseen reasons in the actual application environment, the preset condition has not been reached for a long time, which will cause the series of instructions to be abnormally executed multiple times. The phenomenon that the series of instructions are executed abnormally multiple times within a long period of time, resulting in the CPU being unable to respond to other services, is called an infinite loop.

In the prior art, in order to solve the above problems, a special reset device is usually integrated in the device, such as a watchdog, to monitor the operating status of the CPU in the device, and when it is determined that the CPU stops responding, it triggers the CPU to interrupt and reset, thereby avoiding including Faults including the CPU infinite loop cause business operations to be affected for a long time. For example, the operating status of the CPU is monitored through techniques such as heartbeat detection. When the CPU does not respond to the reset device within the preset time, causing the timer in the heartbeat detection to overflow, the reset device will reset the CPU to break the CPU out of the endless loop state.

The register in the CPU will save the instruction address when the CPU interrupt occurs before the reset. However, since the current program code is designed, there are often more complex nested call relationships between multiple functions. The instruction address stored in the register at the time of the interrupt The corresponding instruction is not necessarily the instruction in the function that causes the infinite loop to occur. Therefore, it is difficult to accurately locate the function where the infinite loop occurs by using the instruction address in the register at the time of interruption.

Existing CPU infinite loop positioning technology relies more on the experience of developers to complete. Through association and guessing, the developer analyzes the function related to the instruction corresponding to the address stored in the register at the time of interruption, and uses the debugging tool to locate it. However, many dead loops that appear in practice are sporadic, or do not appear every time it is run, and it is relatively difficult to reproduce. Therefore, the low efficiency of the existing CPU dead-loop positioning technology has become an urgent problem to be solved in the software product design process. .

Contents of the invention

In view of this, the present application provides a method for generating a processor fault record, which is used to provide more information in the CPU when the fault occurs, thereby reducing the difficulty of locating the cause of the CPU dead cycle.

The technical solutions provided by the embodiments of the present application are as follows.

In a first aspect, a method for generating a processor fault record is provided, which is applied to a hardware platform including a control chip and a central processing unit CPU, and the method includes:

The control chip detects that a processing unit in the CPU stops responding;

The control chip obtains the instruction address in the current program counter PC of the processing unit through the joint test action group JTAG channel;

The control chip creates a first-type entry including the instruction address in the current PC, and records the first-type entry in the instruction address table;

The control chip judges whether the number of entries recorded in the instruction address table reaches a preset value, and the preset value is greater than or equal to 2;

If the number of entries recorded in the instruction address table does not reach the preset value, the control chip returns to execute the step of obtaining the instruction address in the current program counter PC of the processing unit through the JTAG channel;

If the number of entries recorded in the instruction address table reaches the preset value, the control chip triggers the CPU interrupt.

Through the above scheme, when the processing unit stops responding, the control chip obtains multiple instruction addresses stored in the PC of the processing unit through the JTAG channel within a period of time and records them in the instruction address table. The instruction address table reflects the status of the program running by the processing unit within a period of time after the processing unit stops responding. Since when the processing unit enters an infinite loop, the infinite loop function and a corresponding piece of code line will be called repeatedly, therefore, the method provided in the embodiment of the present application, compared with the prior art, detects that the processing unit In terms of triggering an interrupt immediately after stopping the response, and only recording the address of an instruction that the processing unit is running at the time of the interruption, it can more accurately reflect the function and code interval where the infinite loop occurs, and help improve the efficiency of CPU fault analysis.

Optionally, before recording the first type of entry in the instruction address table, the method further includes:

The control chip obtains the instruction address in the current function return address register of the processing unit through the JTAG channel;

The control chip adds the instruction address in the current function return address register to the first type entry.

By recording the instruction address in the current function return address register of the processing unit in the instruction address table, the instruction address table can more clearly reflect the call relationship between the functions being run by the processing unit, further Improved the efficiency of CPU failure analysis.

Optionally, before recording the first type of entry in the instruction address table, the method further includes:

The control chip acquires the current time, and adds the current time to the first type entry.

Optionally, the recording the first type of entry in the instruction address table includes:

The control chip records the first type of entries in the instruction address table according to the sequence in which the first type of entries are generated.

Optionally, the control chip returns to execute the step of obtaining the instruction address in the current PC of the processing unit through the JTAG channel, including:

The control chip delay time period T1;

After the time period T1 arrives, the control chip returns to execute the step of obtaining the instruction address in the current PC of the processing unit through the JTAG channel.

By delaying the time period T1, the control chip can make the control chip perform other tasks during the delayed T1 time period, so as to prevent the control chip from reading the pointer of the processing unit PC due to cyclic execution and recording it in the Steps such as the first type of entries occupy too many resources of the control chip.

Optionally, the control chip detects that the processing unit stops responding, including:

The control chip detects the heartbeat of the processing unit, and determines that the processing unit stops responding.

Optionally, the method further includes that the control chip sequentially reads a first-type entry from the instruction address table according to the order in which the entries are stored, and for each read first-type entry ,implement:

According to the instruction address in the PC included in the first type of entry, the control chip obtains the first The function name and code line corresponding to the instruction address in the PC included in the class entry;

The control chip creates a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry;

The control chip records the second type of entries in the function operation table according to the sequence in which the second type of entries are generated.

The control chip generates a second-type entry in the function operation table according to each first-type entry in the instruction address table, and the function operation table records that within a period of time after the processing unit stops responding, the operation The function name and code line of the program, compared with the instruction address, the function name and code line more intuitively reflect the program run by the processing unit, which helps to further improve the efficiency of CPU fault analysis.

Optionally, the method also includes:

The control chip sequentially reads a first-type entry from the instruction address table according to the sequence in which the entries are stored, and executes for each read first-type entry:

According to the instruction address in the PC included in the first type of entry, the control chip obtains the first The function name and code line corresponding to the instruction address in the PC included in the class entry;

The control chip, according to the instruction address in the function return register included in the first type of entry, obtains the The function name and code line corresponding to the instruction address in the return register included in the first type of entry;

The control chip creates a second type of table entry, the second type of table entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of table entry, and the first type of table entry The function included in the item returns the function name and code line corresponding to the instruction address in the register;

The control chip records the second type of entries in the function operation table according to the sequence in which the second type of entries are generated.

A second aspect provides a method for generating a processor fault record, which is characterized in that it is applied to a hardware platform including a control chip and a multi-core CPU, the multi-core CPU includes a first processing unit and a second processing unit, the The first processing unit and the second processing unit are slave cores in the multi-core CPU,

The methods include:

The control chip detects that the first processing unit stops responding;

If the number of entries recorded in the instruction address table corresponding to the first processing unit does not reach the first preset value, the control chip obtains the current program counter PC of the first processing unit through the joint test working group JTAG channel Instruction address in , the first preset value is greater than or equal to 2;

The control chip creates a first-type entry, and records the first-type entry in the instruction address table corresponding to the first processing unit, and the first-type entry includes the first processing unit The instruction address in the current PC;

If the number of entries recorded in the instruction address table corresponding to the second processing unit does not reach the second preset value, the control chip obtains the instruction address in the current PC of the second processing unit through the JTAG channel , the second preset value is greater than or equal to 2;

The control chip creates another first-type entry, and records the other first-type entry in the instruction address table corresponding to the second processing unit, and the other first-type entry includes an instruction address in the current PC of the second processing unit;

The control chip determines whether the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit reaches a corresponding preset value;

If the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit does not reach the corresponding preset value, the control The chip returns to execute the step of obtaining the instruction address in the current PC of the first processing unit through the JTAG channel;

If the number of entries recorded in the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit both reach a corresponding preset value, the control unit triggers an interrupt of the multi-core CPU.

Through the above solution, when the first processing unit stops responding, the control chip obtains multiple instruction addresses stored in the PC of the first processing unit within a period of time through the JTAG channel and records them in the instruction address table. The instruction address table reflects the state of the program running by the first processing unit within a period of time after the first processing unit stops responding. At the same time, the control chip also records the instruction address stored in the PC of the second processing unit in the same multi-core CPU as the first processing unit. Due to an infinite loop, the infinite loop function and a corresponding section of code line will be called repeatedly, and in a multi-core CPU, there are mutual calls between functions between different slave cores. Therefore, the method provided by this application is better than the existing In the technology, an interrupt is triggered immediately after detecting that the first processing unit stops responding, and only the address of the instruction being executed by the first processing unit and the second processing unit at the time of the interruption is recorded, so as to more accurately reflect the occurrence of the dead Loop function and code section help to improve the efficiency of CPU fault analysis.

Optionally, before recording the first type of entry in the instruction address table corresponding to the first processing unit, the method further includes:

The control chip obtains the instruction address in the current function return address register of the first processing unit through the JTAG channel;

The control chip adds the instruction address in the current function return address register of the first processing unit to the first type entry;

Before recording the other first-type entry in the instruction address table corresponding to the second processing unit, it also includes:

The control chip obtains the instruction address in the current function return address register of the second processing unit through the JTAG channel;

The control chip adds the instruction address in the current function return address register of the second processing unit to the other first-type entry.

By recording the instruction addresses in the current function return address registers of the first processing unit and the second processing unit in the corresponding instruction address table, the instruction address table can more clearly reflect that the corresponding processing unit is running The call relationship between functions further improves the efficiency of CPU fault analysis.

Optionally, the control chip sequentially reads a first-type entry from the instruction address table corresponding to the first processing unit according to the order in which the entries are stored, and for each read first-type entry ,implement:

According to the instruction address in the PC included in the first type of entry, the control chip obtains the The function name and code line corresponding to the instruction address in the PC included in the first type of entry;

The control chip creates a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry;

The control chip records the second type of entries in the function operation table corresponding to the first processing unit according to the sequence in which the second type of entries are generated.

Optionally, the control chip sequentially reads a first-type entry from the instruction address table corresponding to the second processing unit according to the order in which the entries are stored, and for each read first-type entry ,implement:

According to the instruction address in the PC included in the first type of entry, the control chip obtains the The function name and code line corresponding to the instruction address in the PC included in the first type of entry;

The control chip creates a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry;

The control chip records the second type of entries in the function operation table corresponding to the second processing unit according to the sequence in which the second type of entries are generated.

Through the above solution, the control chip generates the second type of entry in the first function operation table according to the first instruction address table, and generates the second type of entry in the second function operation table according to the first type of entry in the second instruction address table. The second type of table item, the function name and code line of the running program recorded in the function operation table within a period of time after the corresponding processing unit stops responding. Compared with the instruction address, the function name and code line are more intuitive The program reflecting the operation of the processing unit is helpful to further improve the efficiency of CPU failure analysis.

In a third aspect, there is provided a device for generating a processor fault record, which is characterized in that it is applied to a hardware platform including the device and a first central processing unit CPU, and the first CPU includes at least one processing unit, The device communicates with the first CPU through a JTAG channel, the device includes: a second processor, a memory, and a JTAG interface, and the second processor, the memory, and the JTAG interface are connected through a bus;

The JTAG interface is used to obtain the instruction address in the program counter PC of the processing unit in the first CPU through the JTAG channel, and send the instruction address in the PC to the first CPU through the bus. two processors;

The second processor is configured to read the program code stored in the memory, and perform the following operations:

detecting that a processing unit in the first CPU has stopped responding;

Obtain the instruction address in the current program counter PC of the processing unit through the JTAG channel;

Create a first type entry including the instruction address in the current PC, and record the first type entry in the instruction address table;

judging whether the number of entries recorded in the instruction address table reaches a preset value, and the preset value is greater than or equal to 2;

If the number of entries recorded in the instruction address table does not reach the preset value, return to the step of obtaining the instruction address in the current program counter PC of the processing unit through the JTAG channel;

If the number of entries recorded in the instruction address table reaches the preset value, an interrupt of the first CPU is triggered.

Optionally, the JTAG interface is also used to obtain the instruction address in the current function return register of the processing unit in the first CPU through the JTAG channel, and return the current function return instruction address in the register. sending an instruction address to the second processor through the bus;

The second processor is further configured to perform the following operations before performing the recording of the first type entry in the instruction address table:

Obtain the instruction address in the current function return address register of the processing unit through the JTAG channel;

Add the instruction address in the current function return address register to the first type entry.

Optionally, the second processor returns to execute the step of obtaining the instruction address in the current program counter PC of the processing unit through the JTAG channel, including executing:

Delay period T1;

After the time period T1 arrives, return to the step of obtaining the instruction address in the current program counter PC of the processing unit through the JTAG channel.

Optionally, the first CPU is a multi-core CPU, and the processing unit is a main core of the first multi-core CPU,

The second processor detects that a processing unit in the first CPU stops responding, including performing:

A heartbeat detection is performed on the main core, and it is determined that the main core stops responding.

Optionally, the second processor is further configured to sequentially read a first-type entry from the instruction address table according to the order in which the entries are stored, and for each read first-type entry ,implement:

According to the instruction address in the PC included in the first type of entry, from the preset correspondence between the instruction address in the processing unit and the function name and code line, query and obtain the first type of entry The included function name and code line corresponding to the instruction address in the PC;

Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry;

According to the order in which the second-type entries are generated, the second-type entries are recorded in the function operation table.

Optionally, the second processor is further configured to sequentially read a first-type entry from the instruction address table according to the order in which the entries are stored, and for each read first-type entry ,implement:

According to the instruction address in the PC included in the first type of entry, from the preset correspondence between the instruction address in the processing unit and the function name and code line, query and obtain the first type of entry The included function name and code line corresponding to the instruction address in the PC;

According to the instruction address in the function return register included in the first type table item, from the preset correspondence between the instruction address in the processing unit, the function name and the code line, query and obtain the first type table The function included in the item returns the function name and code line corresponding to the instruction address in the register;

Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry, and the first type of entry included in the The function returns the function name and code line corresponding to the instruction address in the register;

According to the order in which the second-type entries are generated, the second-type entries are recorded in the function operation table.

Optionally, the JTAG interface is integrated in a monitoring chip, the second processor is integrated in a main control chip, the monitoring chip communicates with the first CPU through the JTAG channel, and the main control chip The chip communicates with the monitoring chip through a bus.

Through the above solution, when the device for generating the processor fault record detects that the processing unit stops responding, it obtains multiple instruction addresses stored in the PC of the processing unit through the JTAG interface within a period of time and records them in the instruction address table. The instruction address table reflects the status of the program running by the processing unit within a period of time after the processing unit stops responding. Since when the processing unit enters an infinite loop, the infinite loop function and a corresponding piece of code line will be repeatedly called, therefore, compared with the prior art, an interrupt is triggered immediately after the processing unit stops responding, and In terms of only recording the address of the instruction that the processing unit is running at the moment of interruption, it can more accurately reflect the function and code interval where the infinite loop occurs, and help to improve the efficiency of CPU fault analysis.

In a fourth aspect, there is provided a device for processor fault recording, which is characterized in that it is applied to a hardware platform including the device and a first multi-core CPU, and the first multi-core CPU includes a first processing unit and a The second processing unit, the first processing unit and the second processing unit are slave cores of the first multi-core CPU, and the device communicates with the first multi-core CPU through a joint test working group JTAG channel, The device includes: a second processor, a memory, and a JTAG interface, and the second processor, the memory, and the JTAG interface are connected through a bus;

The JTAG interface is used to obtain the instruction address in the program counter PC of the processing unit in the first multi-core CPU through the JTAG channel, and send the instruction address in the PC to the the second processor;

The second processor is configured to read the program code stored in the memory, and perform the following operations:

detecting that the first processing unit has stopped responding;

If the number of entries recorded in the instruction address table corresponding to the first processing unit has not reached the first preset value, obtain the instruction address in the current program counter PC of the first processing unit through the JTAG interface, and the first processing unit A preset value is greater than or equal to 2;

Create a first type of entry, the first type of entry is recorded in the instruction address table corresponding to the first processing unit, and the first type of entry includes the current PC of the first processing unit command address;

If the number of entries recorded in the instruction address table corresponding to the second processing unit does not reach the second preset value, obtain the instruction address in the current PC of the second processing unit through the JTAG interface, and the second processing unit 2. The preset value is greater than or equal to 2;

Create another first-type entry, and record the other first-type entry in the instruction address table corresponding to the second processing unit, the other first-type entry includes the first 2. The instruction address in the current PC of the processing unit;

judging whether the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit reaches a corresponding preset value;

If the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit does not reach the corresponding preset value, return to execute the Describe the step of obtaining the instruction address in the current PC of the first processing unit through the JTAG channel;

If the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit reaches the corresponding preset value, triggering the second A multi-core CPU interrupt.

Optionally, the JTAG interface is also used to obtain the instruction address in the current function return register of the processing unit in the first multi-core CPU through the JTAG channel, and return the current function return instruction address in the register. sending an instruction address to the second processor through the bus;

Before the second processor executes the recording of the first type entry in the instruction address table corresponding to the first processing unit, it is also used to execute:

Obtaining the instruction address in the current function return address register of the first processing unit through the JTAG interface;

adding the instruction address in the current function return address register of the first processing unit to the first type entry;

Before the second processor executes the recording of the other first-type entry in the instruction address table corresponding to the second processing unit, it is also used to execute:

Obtaining the instruction address in the current function return address register of the second processing unit through the JTAG interface;

Add the instruction address in the current function return address register of the second processing unit to the other first type entry.

Optionally, the second processor detects that the first processing unit stops responding, including executing:

receiving instruction information sent by the main core in the first multi-core CPU, where the instruction information carries the identifier of the first processing unit;

The second processor determines, according to the indication information, that the first processing unit stops responding.

Optionally, the second processor is further configured to sequentially read a first-type entry from the instruction address table corresponding to the first processing unit according to the order in which the entries are stored, and for each read A first-type entry, execute:

According to the instruction address in the PC included in the first-type table entry, the first-type table is queried to obtain the first-type table from the preset correspondence between the instruction address in the first processing unit, the function name, and the code line The function name and code line corresponding to the instruction address in the PC included in the item;

Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry;

According to the order in which the entries of the second type are generated, the entries of the second type are recorded in the function operation table corresponding to the first processing unit.

Optionally, the second processor is further configured to sequentially read a first-type entry from the instruction address table corresponding to the second processing unit according to the order in which the entries are stored, and for each read For the first type of entry, execute:

According to the instruction address in the PC included in the first-type table entry, the first-type table is queried to obtain the first-type table from the preset correspondence between the instruction address in the second processing unit, the function name, and the code line The function name and code line corresponding to the instruction address in the PC included in the item;

Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry;

According to the order in which the entries of the second type are generated, the entries of the second type are recorded in the function operation table corresponding to the second processing unit.

Optionally, the JTAG interface is integrated in a monitoring chip, the second processor is integrated in a main control chip, the monitoring chip communicates with the first multi-core CPU through the JTAG channel, and the The main control chip communicates with the monitoring chip through a bus.

Through the above solution, when the first processing unit stops responding, the fault record generation device obtains multiple instruction addresses stored in the PC of the first processing unit within a period of time through the JTAG channel and records them in the instruction address table. The instruction address table reflects the state of the program running by the first processing unit within a period of time after the first processing unit stops responding. At the same time, the fault record generation device also records the instruction address stored in the PC of the second processing unit in the same multi-core CPU as the first processing unit. Due to an infinite loop, the infinite loop function and a corresponding section of code line will be called repeatedly, and in a multi-core CPU, functions between different slave cores are called each other. Compared with the prior art, it is detected that the first An interrupt is triggered immediately after a processing unit stops responding, and only the address of the instruction that the first processing unit and the second processing unit are running at the time of the interruption is recorded, so as to more accurately reflect the functions and code intervals where an infinite loop occurs, and there is Helps improve the efficiency of CPU failure analysis.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present application. Those skilled in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the present application;

FIG. 2 is a flow chart of a method for generating a processor failure record provided by an embodiment of the present application;

FIG. 3 is a flow chart of another method for generating a processor failure record provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of an apparatus for generating a processor failure record provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of another device for generating a processor fault record provided by an embodiment of the present application.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

FIG. 1 shows a schematic diagram of an application scenario provided by an embodiment of the present application. The network device 100 includes a hardware platform composed of a CPU 101 and a control chip 102 . The CPU 101 is used to execute programs stored in the memory of the network device 100 to realize the service functions of the network device 100 . The control chip 102 is used to monitor the running status of the CPU 101 .

For example, the control chip 102 may include a main control chip 1021 and a monitoring chip 1022 . The main control chip 1021 manages the business operation status of the CPU 101. For example, the main control chip 1021 monitors the operation status of the CPU by performing heartbeat detection on the CPU 101. When the main control chip 1021 detects that the CPU 101 stops responding, it triggers the CPU 101 to interrupt and restart The CPU 101 makes the CPU 101 out of the fault state. The monitoring chip 1022 is used to manage the working conditions of network equipment, such as voltage and temperature. The main control chip 1021 , the monitoring chip 1022 and the CPU 101 are respectively connected and communicated through a bus.

The CPU 101 may be a single-core processor or a multi-core processor. When the CPU 101 is a single-core processor, it includes a processing unit 1011; when the CPU 101 is a multi-core processor, at least a processing unit 1012 is included.

When the CPU 101 is a multi-core processor, the main control chip 1021 can perform heartbeat detection on the processing unit 1011 and the processing unit 1012 respectively, so as to monitor the operating status of the CPU 101 . In the case where a multi-core processor includes a master core (such as a processing unit 1011) and a slave core (such as a processing unit 1012), the main control chip 1021 may only perform heartbeat detection on the master core, and the master core may check the Detection is performed from the nucleus. When the master core detects that the slave core stops responding, it notifies the master chip 1021 .

The main control chip 1021 can be integrated with the CPU 101 on a printed circuit board (English: printed circuit board, PCB for short), or can be integrated on different PCBs. When the main control chip 1021 and the CPU 101 are integrated on the same PCB, an internal bus can be used for communication. When the main control chip 1021 and the CPU 101 are not on the same PCB, they can communicate through the Ethernet interface. The monitoring chip 1022 is generally integrated with the CPU 101 on the same PCB.

The program executed by the CPU 101 is composed of a series of instructions, and the storage location of each instruction in the memory is identified by an instruction address. When the CPU executes an instruction, it first needs to store the instruction address in a register of the CPU, that is, the program counter (English: program counter, PC for short), and then obtain the instruction from the address corresponding to the memory through the instruction address. and storing the instruction in an instruction register (English: instruction register, IR for short) of the CPU to execute the instruction. In some types of CPUs, a function return address register is also included. When an instruction calls a function in the program, the address of the instruction is stored in the function return address register. When the called function is executed , the CPU continues to execute the next instruction of the instruction address in the function return address register.

In the prior art, when the main control chip 1021 detects that the CPU 101 stops responding, it immediately triggers an interrupt of the CPU 101 . When the CPU 101 responds to the interrupt, it will save the instruction address in the registers such as the PC and the function return register inside the CPU 101 at the time of the interrupt. Thereafter, the CPU 101 can save and output the instruction address in the register saved at the time of the output interruption. However, since the current program code is designed, there are often complex nested calling relationships between multiple functions, and the instruction corresponding to the instruction address stored in the register at the time of interruption is not necessarily the instruction in the function that causes the infinite loop to occur. Therefore, it is difficult to accurately locate the function where the infinite loop occurs by using the instruction address in the register at the time of interruption.

In the method for generating a processor fault record provided in this application, the communication channel between the control chip 102 and the CPU 101 includes a JTAG channel. The JTAG channel refers to a channel for communicating using an interface defined in a related protocol of a joint test action group (English: joint test action group, JTAG for short). For example, in the IEEE 1149.1 standard, it is defined that the JTAG interface requires four interfaces, namely, test data input (TDI, Test Data In), test data output (TDO, Test Data Out), and test clock (TCK, Test Clock) And test mode selection (TMS, Test Mode Select). The control chip reads the information of the register in the processing unit through the interface defined by the IEEE1149.1 standard.

In the case that the control chip 102 includes a main control chip 1021 and a monitoring chip 1022 , the JTAG channel can generally be realized by a communication channel between the CPU 101 and the monitoring chip 1022 . The main control chip 1021 usually includes a processor (English: processor). The monitoring chip 1022 obtains the instruction address of the register in the CPU 101 through the JTAG channel according to the method provided in the embodiment of the present application, and sends it to the main control chip 1021 through the internal bus, and the processor in the main control chip 1021 implements and generates a fault record.

By making full use of the existing chip structure in the distributed network equipment, namely utilizing the monitoring chip on the same PCB board of the CPU to realize the JTAG interface, utilizing the processor in the main control chip to realize the method described in Fig. 2 The generation of the instruction address table is beneficial to reduce the implementation difficulty of the method for generating the processor fault record.

FIG. 2 shows a method for generating a processor fault record provided by an embodiment of the present application, which is applied to a hardware platform including a control chip and a central processing unit CPU. For example, the hardware platform may be the hardware platform shown in FIG. 1 , the control chip may be the control chip 102 shown in FIG. 1 , and the CPU may be the CPU 101 shown in FIG. 1 .

A method for generating a processor fault record provided by an embodiment of the present application will be described in detail below with reference to FIG. 2 .

S201. The control chip detects that a processing unit in the CPU stops responding.

For example, the control chip detects the heartbeat of the processing unit, and determines that the processing unit stops responding. For example, the control chip periodically sends a detection message to the processing unit, and if the control chip does not receive a response from the processing unit to the detection message within a preset time, it determines that the The processing unit stops responding.

The processing unit may be the processing unit 1011 shown in FIG. 1 . In the case that the CPU is a multi-core processor, the processing unit 1011 may be a master core of the CPU, or a slave core of the CPU.

S202. The control chip obtains the instruction address in the current program counter PC of the processing unit through the joint test action group JTAG channel.

It should be noted that, in order to realize reading information of registers in the processing unit through the JTAG channel, the processing unit needs to have a JTAG module inside. The JTAG module is composed of a test access port (English: test access port, abbreviated: TAP) controller and several registers (English: register). The control chip sends instructions to the TAP controller through the JTAG channel, reads the information of internal registers such as the processing unit PC into the registers of the JTAG module, and sends the information to the TAP controller through the JTAG channel. The control chip. Currently common high-level devices have modules that support the JTAG protocol, such as MIPS processors, ARM processors, and so on.

Optionally, in S202, the control chip also obtains the instruction address in the current function return address register of the processing unit through the JTAG channel.

Specifically, in some types of CPUs, a function return address register is included. When an instruction calls a function in the program, the address of the instruction is stored in the function return address register, and when the called function is executed, the CPU continues to execute the address of the instruction in the function return address register. next instruction. For example, in a MIPS architecture CPU, the function return address register may be the R31 register, also known as the Ra register; in an ARM architecture CPU, the function return address register may be the R14 register, also known as the link register (English: link register, abbreviation: LR). For the convenience of description, in the following embodiments, only the Ra register will be used as an example for illustration.

By recording the instruction address in the current function return address register of the processing unit in the instruction address table, the instruction address table can more clearly reflect the call relationship between the functions being run by the processing unit, further Improved the efficiency of CPU failure analysis.

It should be noted that the acquisition of the instruction address in the current PC in S202 and the acquisition of the instruction address in the current Ra register may be acquired at the same time; The instruction address, and then immediately obtain the instruction address in the current Ra register; it is also possible to first obtain the instruction address in the current Ra register, and then immediately obtain the instruction address in the current PC. Because in the process of function calling, for example, function A calls function B, during the entire function B running, the instruction address in the Ra register is the instruction address of the instruction that function A calls function B, that is, during the entire function B running, the Ra register The address of the instruction in does not change. Therefore, those skilled in the art can understand that obtaining the instruction address in the current PC and obtaining the instruction address in the current Ra are not strictly required to be performed at the same time.

S203. The control chip creates a first-type entry including the instruction address in the current PC, and records the first-type entry in the instruction address table.

For example, before the control chip acquires the instruction address in the PC of the processing unit for the first time, it initializes the instruction address table. For example, a certain space is allocated in the memory of the control chip for storing entries in the instruction address table, and a preset value is set for the number of entries to be recorded. The preset value is greater than or equal to 2.

Optionally, if the control chip in S202 also obtains the instruction address in the current function return address register of the processing unit, the control chip in S203 also adds the instruction address in the current function return address register to In the first type of entry.

Optionally, the control chip acquires the current time, and adds the current time to the first type of entry.

It should be noted that since the current time is recorded in the first type of entry, the main purpose is to determine the approximate time when the fault occurs, and the time interval between the creation of each first type of entry in the instruction address table , so the current moment may be the moment when the instruction address in the PC is obtained in S202, or the moment when the instruction address in the register is obtained by the function return register in S202, or the moment when the first type of entry is created in S203 , the current time may be obtained from the processing unit through the JTAG channel, or may be generated by the control chip. The present application does not limit the specific time point and method for obtaining the current moment.

Optionally, the recording the first type of entry in the instruction address table includes: the control chip records the first type of entry in the order in which the first type of entry is generated. instruction address table.

S204. The control chip judges whether the number of entries recorded in the instruction address table reaches a preset value, and the preset value is greater than or equal to 2.

If the number of entries recorded in the instruction address table does not reach the preset value, the control chip returns to execute S202 and S203; if the number of entries recorded in the instruction address table reaches the preset value, Execute S205.

Optionally, if the number of entries recorded in the instruction address table does not reach the preset value, the control chip returns to execute S202 and S203, including: the control chip delays the time period T1; After the segment T1 arrives, the control chip returns to execute S202 and S203.

By delaying the time period T1, the control chip can make the control chip perform other tasks during the delayed T1 time period, so as to prevent the control chip from occupying too many resources of the control chip due to cyclic execution of S202 to S204. For example, the time period T1 may be 1 ms, 10 ms, 50 ms or 100 ms and so on.

S205. The control chip triggers the CPU interrupt.

For example, the interrupt triggered by the control chip may be a non-maskable interrupt (English: non-maskable interrupt, NMI for short). The control chip triggers an interrupt, and then triggers the restart of the CPU, so as to get rid of the current fault.

Table 1 is an example of the instruction address table.

entry Instruction address in PC Instruction address in Ra time 1 0x2dc9c0 0xddb2f0ae 6:18:01.050 2 0x151a4d4 0x2dc3d1 6:18:01.100 3 0x2dc9f2 0xddb2f0ae 6:18:01.150 … … … … N 0x151a12c 0x2dc3d1 6:18:04.150

Table 1

As shown in Table 1, at 6:18:01.050, the control chip acquires that the instruction address in the processing unit PC is 0x2dc9c0, the instruction address in the Ra register is 0xddb2f0ae, and the control chip creates a first-class table entry, that is, entry 1 in Table 1, and record the addresses of the above two instructions in the first type of entry. At 6:18:01.100, the control chip acquires that the instruction address in the processing unit PC is 0x151a4d4, and the instruction address in the Ra register is 0x2dc3d1, and the control chip creates another first-type entry, namely table 1, and record the addresses of the above two instructions in the other first-type entry. Similarly, the control chip also creates entry 3 at 6:18:01.150, and creates entry N at 6:18:04.050, and records the corresponding instruction address.

Through the above scheme, when the processing unit stops responding, the control chip obtains multiple instruction addresses stored in the PC of the processing unit through the JTAG channel within a period of time and records them in the instruction address table. The instruction address table reflects the status of the program running by the processing unit within a period of time after the processing unit stops responding. Since when the processing unit enters an infinite loop, the infinite loop function and a corresponding piece of code line will be called repeatedly, therefore, the method provided by this application, compared with the prior art, detects that the processing unit stops responding In terms of triggering an interrupt immediately after the interrupt, and only recording the address of the instruction that the processing unit is running at the time of the interrupt, it can more accurately reflect the function and code interval where the infinite loop occurs, and help improve the efficiency of CPU fault analysis

Optionally, in S206, the control chip sequentially reads a first-type entry from the instruction address table according to the order in which the entries are stored, and for each read first-type entry, execute: According to the instruction address in the PC included in the entry of the first type, the control chip obtains the first type of The function name and code line corresponding to the instruction address in the PC included in the entry; the control chip creates a second type of entry, and the second type of entry includes the first type of entry The function name and code line corresponding to the instruction address in the PC; the control chip records the second type of entry in the function operation table according to the sequence in which the second type of entry is generated.

For example, the preset correspondence between instruction addresses in the processing unit, function names, and code lines can be obtained by disassembling programs in the processing unit. For example, the program in the processing unit is input into a compiler to generate a disassembly file, the disassembly file includes the name of each function in the program of the processing unit, the code of each function assembly language, and all The corresponding relationship between the code line of the assembly language and the instruction address in the memory of the processing unit is described. For example, the compiler may be the objdump software in the GNU compiler suite (English: GNU compiler collection, GCC for short). For example, the file input to objdump may be a management plane file or a data plane file.

Optionally, if the control chip in S203 also adds the instruction address in the current function return address register to the first type of entry, the control chip in S206 for each read The first type of entry also includes execution: the control chip returns the instruction address in the register according to the function included in the first type of entry, from the preset instruction address and function name and code in the processing unit In the row correspondence, query to obtain the function name and code line corresponding to the instruction address in the function return register included in the first type of entry; return the function included in the first type of entry to the register Add the function name and code line corresponding to the instruction address in the second type of entry.

The control chip generates a second-type entry in the function operation table according to each first-type entry in the instruction address table, and the function operation table records that within a period of time after the processing unit stops responding, the operation The function name and code line of the program, compared with the instruction address, the function name and code line more intuitively reflect the program run by the processing unit, which helps to further improve the efficiency of CPU fault analysis.

Table 2 shows an example of the function execution table.

Table 2

As shown in Table 2, each second-type entry in the function operation table includes six items, which are: the entry number, the function corresponding to the instruction address in the PC, the code line corresponding to the instruction address in the PC, and the The function corresponding to the instruction address in Ra, the code line and time corresponding to the instruction address in Ra. Among them, the function corresponding to the instruction address in Ra, the code line and time corresponding to the instruction address in Ra are optional.

Each entry of the second type corresponds to an entry of the first type created in S203. For example, entry i in Table 2 corresponds to entry 1 in Table 1, entry ii in Table 2 corresponds to entry 2 in Table 1, and entry iii in Table 2 corresponds to entry 1 in Table 1 3, and entry M in Table 2 corresponds to entry N in Table 1. In each of the second-type entries, the function corresponding to the instruction address in the PC and the code line corresponding to the instruction address in the PC refer to the first The instruction address in the PC recorded in the class entry is the function name and code line obtained by querying the preset correspondence between the instruction address in the processing unit and the function name and code line. Similarly, the function corresponding to the instruction address in Ra and the code line corresponding to the instruction address in Ra respectively refer to the The instruction address of the function name and the code line obtained by querying the preset correspondence between the instruction address in the processing unit and the function name and the code line.

In the case that the function corresponding to the instruction address in Ra and the code line corresponding to the instruction address in Ra are not included in Table 2, the fault of the CPU is analyzed through Table 2, and it can be found that function B and function C alternate multiple times is executed, and according to this analysis, the infinite loop may appear in the process of calling each other between function B and function C.

Furthermore, the engineer who analyzes the processor fault can obtain the call relationship between function B and function C by querying the source code of the program. The cause of the cycle.

In the case where Table 2 includes the function corresponding to the instruction address in Ra and the code line corresponding to the instruction address in Ra, the calling relationship between functions can be obtained more intuitively. For example, it can be seen from Table 2 that the instruction corresponding to the 129th line of code of function B calls function C repeatedly. Since function B and function C appear alternately, it means that function C can run normally and return function B. Therefore, it is analyzed that a section of instructions before and after the 129th line of code of function B may be the cause of the infinite loop.

If an interrupt is triggered immediately when the control chip detects that the processing unit stops responding, the instruction address in the PC at the moment of the interrupt may be the instruction address in the function C, so it will be difficult to efficiently analyze the cause of the fault.

FIG. 3 shows another method for generating a processor fault record provided by an embodiment of the present application, which is applied to a hardware platform including a control chip and a multi-core CPU, and the multi-core CPU includes a first processing unit and a second processing unit, The first processing unit and the second processing unit are slave cores in the multi-core CPU. For example, the hardware platform may be the hardware platform shown in FIG. 1, the control chip may be the control chip 102 shown in FIG. 1, the CPU may be the CPU 101 shown in FIG. 1, and the first processing unit may be is the first processing unit 1011 shown in FIG. 1 , and the second processing unit may be the second processing unit 1012 shown in FIG. 1 .

Another method for generating a processor fault record provided by the embodiment of the present application will be described in detail below with reference to FIG. 3 .

S301. The control chip detects that the first processing unit stops responding.

For example, the control chip may directly detect the first processing unit to determine whether the first processing unit stops responding; the main core in the multi-core CPU may also check whether the first processing unit stops responding. detection, when the main core detects that the first processing unit has stopped responding, it sends instruction information to the control chip, the instruction information carries the identification of the first processing unit, and the control chip information, it is determined that the first processing unit stops responding.

S302, if the number of entries recorded in the instruction address table corresponding to the first processing unit does not reach the first preset value, the control chip acquires the current program of the first processing unit through the joint test working group JTAG channel The instruction address in the counter PC, and execute S303, the first preset value is greater than or equal to 2. If the number of entries recorded in the instruction address table corresponding to the first processing unit reaches the first preset value, skip execution of S303.

Optionally, in S302, the control chip also obtains the instruction address in the current function return address register of the first processing unit through the JTAG channel.

S303. The control chip creates a first-type entry, and records the first-type entry in the instruction address table corresponding to the first processing unit, and the first-type entry includes the first The address of the instruction in the current PC of the processing unit.

Optionally, if the control chip in S302 obtains the instruction address in the current function return address register of the first processing unit through the JTAG channel, the control chip in S303 converts the current The instruction address in the function return address register is added to the first type entry.

S304. If the number of entries recorded in the instruction address table corresponding to the second processing unit does not reach the second preset value, the control chip obtains the current address of the second processing unit in the PC through the JTAG channel. Instruction address, and execute S305, the second preset value is greater than or equal to 2.

Optionally, the control chip also obtains the instruction address in the current function return address register of the second processing unit through the JTAG channel.

If the number of entries recorded in the instruction address table corresponding to the second processing unit reaches the second preset value, S305 is skipped.

S305. The control chip creates another first-type entry, and records the other first-type entry in the instruction address table corresponding to the second processing unit, and the other first-type entry Include the instruction address in the current PC of the second processing unit.

Optionally, if the control chip in S304 also obtains the instruction address in the current function return address register of the second processing unit through the JTAG channel, the control chip in S305 converts the current The instruction address in the function return address register is added to the other first-type table entry.

It should be noted that, in this application, S302 and S303 may be executed first, and then S304 and S305 may be executed, or S304 and S305 may be executed first, and then S302 and S303 are executed.

S306. The control chip determines whether the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit reaches a corresponding preset value . If the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit does not reach the corresponding preset value, the control The chip returns to step S302. If the number of entries recorded in the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit both reach a corresponding preset value, execute S307.

S307. The control unit triggers an interrupt of the multi-core CPU. The specific implementation manner is similar to that of S205.

For example, the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit are similar to the instruction address table shown in Table 1.

Through the above solution, when the first processing unit stops responding, the control chip obtains multiple instruction addresses stored in the PC of the first processing unit within a period of time through the JTAG channel and records them in the instruction address table. The instruction address table reflects the state of the program running by the first processing unit within a period of time after the first processing unit stops responding. At the same time, the control chip also records the instruction address stored in the PC of the second processing unit in the same multi-core CPU as the first processing unit. Due to an infinite loop, the infinite loop function and a corresponding section of code line will be called repeatedly, and in a multi-core CPU, there are mutual calls between functions between different slave cores. Therefore, the method provided by this application is better than the existing In the technology, an interrupt is triggered immediately after detecting that the first processing unit stops responding, and only the address of the instruction being executed by the first processing unit and the second processing unit at the time of the interruption is recorded, so as to more accurately reflect the occurrence of the dead Loop function and code section help to improve the efficiency of CPU fault analysis.

Optionally, the method further includes S308 and S309.

S308, the control chip sequentially reads a first-type entry from the instruction address table corresponding to the first processing unit according to the order in which the entries are stored, and executes : According to the instruction address in the PC included in the first type of table item, the control chip obtains all The function name and code line corresponding to the instruction address in the PC included in the first type of entry. The control chip creates a second type of table entry, and the second type of table entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of table entry. The control chip records the second type of entries in the function operation table corresponding to the first processing unit according to the sequence in which the second type of entries are generated.

Optionally, if the control chip in S303 adds the instruction address in the current function return address register of the first processing unit to the first type entry, then in S308 the control chip reads Each first-type entry further includes executing: the control chip returns the instruction address in the register according to the function included in the first-type entry, from the preset instruction address in the first processing unit In the corresponding relationship with the function name and the code line, query the function name and code line corresponding to the instruction address in the function return register included in the first type of entry; The function name and code line corresponding to the instruction address in the function return register are added to the second type of entry.

S309, the control chip sequentially reads a first-type entry from the instruction address table corresponding to the second processing unit according to the order in which the entries are stored, and executes for each read first-type entry : According to the instruction address in the PC included in the first type of table item, the control chip obtains all The function name and code line corresponding to the instruction address in the PC included in the first type of entry. The control chip creates a second type of table entry, and the second type of table entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of table entry. The control chip records the second type of entries in the function operation table corresponding to the second processing unit according to the sequence in which the second type of entries are generated.

Optionally, if the control chip in S305 adds the instruction address in the current function return address register of the second processing unit to the first type entry, then in S309 the control chip reads Each entry of the first type further includes execution: the control chip returns the instruction address in the register according to the function included in the entry of the first type, from the preset instruction address in the second processing unit In the corresponding relationship with the function name and the code line, query the function name and code line corresponding to the instruction address in the function return register included in the first type of entry; The function name and code line corresponding to the instruction address in the function return register are added to the second type of entry.

It should be noted that the sequence of execution of S308 and S309 is not limited in this application.

By recording the instruction addresses in the current function return address registers of the first processing unit and the second processing unit in the corresponding instruction address table, the instruction address table can more clearly reflect that the corresponding processing unit is running The call relationship between functions further improves the efficiency of CPU fault analysis.

Table 3 is an example of an instruction address table corresponding to the first processing unit and an instruction address table corresponding to the second processing unit.

table 3

As shown in Table 3, each second-type entry in the function operation table includes six items, which are: the entry number, the function corresponding to the instruction address in the PC, the code line corresponding to the instruction address in the PC, and the The function corresponding to the instruction address in Ra, the code line and time corresponding to the instruction address in Ra. Among them, the function corresponding to the instruction address in Ra, the code line and time corresponding to the instruction address in Ra are optional.

In the case that the function corresponding to the instruction address in Ra and the code line corresponding to the instruction address in Ra are not included in Table 3, the fault of the CPU is analyzed through Table 3, and it can be found that the first processing unit is in function B. After running to the 300th line of code, it stops running, and the function C in the second processing unit is repeatedly run.

Further, the engineer who analyzes the CPU fault can obtain that function B calls function C of the second processing unit by querying the program source code, and function C has been running in a loop, and it is analyzed that the first processor stops responding , may be caused by an infinite loop of function C of the second processing unit. In the case where Table 3 includes the function corresponding to the instruction address in Ra and the code line corresponding to the instruction address in Ra, the calling relationship between functions can be obtained more intuitively.

Fig. 4 is a schematic structural diagram of an apparatus for generating a processor fault record provided by an embodiment of the present application. As shown in FIG. 4 , the device 400 for generating a processor failure record includes a second processor 410, a memory 420, a JTAG interface 430 and a bus 440, and the second processor 410, the memory 420 and the JTAG interface 430 are interconnected through the bus 440 .

The device 400 for generating a processor fault record is applied to a hardware platform including the device 400 and a first central processing unit CPU, the first CPU includes at least one processing unit, and the device communicates with the device through a JTAG channel. The first CPU communicates.

Memory 420 includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), or portable read-only memory (CD-ROM).

The second processor 410 can be one or more central processing units (English: Central Processing Unit, CPU for short), and in the case where the second processor 410 is a CPU, the CPU can be a single-core CPU or a multi-core CPU.

The JTAG interface 430 may be an interface defined in a related protocol using JTAG. For example, in the IEEE 1149.1 standard, it is defined that the JTAG interface requires four interfaces, namely, test data input (TDI, Test Data In), test data output (TDO, Test Data Out), and test clock (TCK, Test Clock) And test mode selection (TMS, Test Mode Select).

The JTAG interface 430 is used to obtain the instruction address in the program counter PC of the processing unit in the first CPU through the JTAG channel, and send the instruction address in the PC to the the second processor 410 .

Optionally, the JTAG interface 430 is further configured to obtain the instruction address in the current function return register of the processing unit in the first CPU through the JTAG channel, and return the current function return instruction address in the register. The instruction address is sent to the second processor 410 through the bus 440 .

The memory 420 is also used to store the instruction address table shown in Table 1, the function execution table shown in Table 2, and so on.

The second processor 410 is configured to read the program code stored in the memory 420 and perform the following operations.

detecting that a processing unit in the first CPU has stopped responding;

Obtain the instruction address in the current program counter PC of the processing unit through the JTAG channel;

Create a first type entry including the instruction address in the current PC, and record the first type entry in the instruction address table;

judging whether the number of entries recorded in the instruction address table reaches a preset value, and the preset value is greater than or equal to 2;

If the number of entries recorded in the instruction address table does not reach the preset value, return to the step of obtaining the instruction address in the current program counter PC of the processing unit through the JTAG channel;

If the number of entries recorded in the instruction address table reaches the preset value, an interrupt of the first CPU is triggered.

Optionally, the second processor 410 is further configured to, before performing the recording of the first type entry in the instruction address table, perform the following operations:

Obtain the instruction address in the current function return address register of the processing unit through the JTAG channel;

Add the instruction address in the current function return address register to the first type entry.

Optionally, the second processor 410 returns to execute the step of obtaining the instruction address in the current program counter PC of the processing unit through the JTAG channel, including executing:

Delay period T1;

After the time period T1 arrives, return to the step of obtaining the instruction address in the current program counter PC of the processing unit through the JTAG channel.

Optionally, the first CPU is a multi-core CPU, and the processing unit is a main core of the multi-core CPU.

The second processor detects that a processing unit in the first CPU stops responding, including performing:

A heartbeat detection is performed on the main core, and it is determined that the main core stops responding.

Further, the second processor 410 is further configured to sequentially read a first-type entry from the instruction address table according to the order in which the entries are stored, and for each read first-type entry ,implement:

According to the instruction address in the PC included in the first type of entry, from the preset correspondence between the instruction address in the processing unit and the function name and code line, query and obtain the first type of entry The included function name and code line corresponding to the instruction address in the PC;

Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry;

According to the order in which the second-type entries are generated, the second-type entries are recorded in the function operation table.

Further, the second processor 410 is further configured to sequentially read a first-type entry from the instruction address table according to the order in which the entries are stored, and for each read first-type entry ,implement:

According to the instruction address in the PC included in the first type of entry, from the preset correspondence between the instruction address in the processing unit and the function name and code line, query and obtain the first type of entry The included function name and code line corresponding to the instruction address in the PC;

According to the instruction address in the function return register included in the first type table item, from the preset correspondence between the instruction address in the processing unit, the function name and the code line, query and obtain the first type table The function included in the item returns the function name and code line corresponding to the instruction address in the register;

Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry, and the first type of entry included in the The function returns the function name and code line corresponding to the instruction address in the register;

According to the order in which the second-type entries are generated, the second-type entries are recorded in the function operation table.

The device 400 provided in this embodiment can be integrated in the control chip 102 shown in FIG. 1, and the hardware platform including the device 400 and the first CPU is integrated in the network device 100 shown in FIG. 1. The first The CPU may be the CPU 101 shown in FIG. 1 .

Optionally, the JTAG interface 430 is integrated in a monitoring chip, the second processor 410 is integrated in a main control chip, the monitoring chip communicates with the first CPU through the JTAG channel, and the The main control chip communicates with the monitoring chip through the bus 440 .

For example, the device 400 is integrated in the control chip 102 shown in FIG. 1, the JTAG interface is integrated in the monitoring chip 1022 shown in FIG. 1, and the second processor 410 is integrated in the In the main control chip 1021, the first CPU may be the CPU 101 shown in FIG. 1 . The bus 440 between the second processor 410 and the JTAG interface 430 can be realized by the bus between the main control chip 1021 shown in Figure 1 and the monitoring chip 1022, and the JTAG channel can be realized by the bus shown in Figure 1 The bus between the monitoring chip 1022 and the CPU 101 is realized. For the specific structure of the connection between the main control chip 1011 , the monitoring chip 1021 and the CPU 101 , please refer to the detailed description in FIG. 1 .

The apparatus 400 for generating a processor fault record provided in this embodiment can be applied to the method of the embodiment in FIG. 2 to realize the function of the control chip. For other additional functions that can be realized by the apparatus 400 and the interaction process with the first CPU, please refer to the description of the control chip in the method embodiment, and details will not be repeated here.

Through the above solution, when the device for generating the processor fault record detects that the processing unit stops responding, it obtains multiple instruction addresses stored in the PC of the processing unit through the JTAG interface within a period of time and records them in the instruction address table. The instruction address table reflects the status of the program running by the processing unit within a period of time after the processing unit stops responding. Since when the processing unit enters an infinite loop, the infinite loop function and a corresponding piece of code line will be called repeatedly, therefore, the method provided by this application, compared with the prior art, detects that the processing unit stops responding In terms of triggering an interrupt immediately after the interrupt and only recording the address of the instruction that the processing unit is running at the time of the interrupt, it can more accurately reflect the function and code interval where the infinite loop occurs, and help to improve the efficiency of CPU fault analysis.

Fig. 5 is a schematic structural diagram of an apparatus for generating a processor fault record provided by an embodiment of the present application. As shown in FIG. 5 , the device 500 for generating a processor fault record includes a second processor 510, a memory 520, a JTAG interface 530 and a bus 540, and the second processor 510, the memory 520 and the JTAG interface 530 are interconnected through the bus 540 .

The device 500 for generating a processor fault record is applied to a hardware platform including the device 500 and a first multi-core central processing unit CPU, the first CPU includes a first processing unit and a second processing unit, the The first processing unit and the second processing unit are slave cores of the first multi-core CPU, and the device communicates with the first multi-core CPU through a JTAG channel.

Memory 520 includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), or portable read-only memory (CD-ROM).

The second processor 510 may be one or more central processing units (English: Central Processing Unit, CPU for short), and when the processor 510 is a CPU, the CPU may be a single-core CPU or a multi-core CPU.

The JTAG interface 530 may be an interface defined in a related protocol using JTAG. For example, in the IEEE 1149.1 standard, it is defined that the JTAG interface requires four interfaces, namely, test data input (TDI, Test Data In), test data output (TDO, Test Data Out), and test clock (TCK, Test Clock) And test mode selection (TMS, Test Mode Select).

The JTAG interface 530 is used to obtain the instruction address in the program counter PC of the processing unit in the first multi-core CPU through the JTAG channel, and send the instruction address in the PC to the The second processor 510.

Optionally, the JTAG interface 530 is also used to obtain the instruction address in the current function return register of the processing unit in the first multi-core CPU through the JTAG channel, and return the current function return register The instruction address in is sent to the second processor 510 through the bus 540 .

The memory 520 is also used to store the instruction address table shown in Table 1, the function execution table shown in Table 3, and so on.

The second processor 510 is configured to read the program code stored in the memory 520 and perform the following operations.

detecting that the first processing unit has stopped responding;

If the number of entries recorded in the instruction address table corresponding to the first processing unit has not reached the first preset value, obtain the instruction address in the current program counter PC of the first processing unit through the JTAG interface, and the second A preset value is greater than or equal to 2;

Create a first type of entry, the first type of entry is recorded in the instruction address table corresponding to the first processing unit, and the first type of entry includes the current PC of the first processing unit command address;

If the number of entries recorded in the instruction address table corresponding to the second processing unit does not reach the second preset value, obtain the instruction address in the current PC of the second processing unit through the JTAG interface, and the second processing unit 2. The preset value is greater than or equal to 2;

Create another first-type entry, and record the other first-type entry in the instruction address table corresponding to the second processing unit, the other first-type entry includes the first 2. The instruction address in the current PC of the processing unit;

judging whether the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit reaches a corresponding preset value;

If the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit does not reach the corresponding preset value, return to execute the Describe the step of obtaining the instruction address in the current PC of the first processing unit through the JTAG channel;

If the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit reaches the corresponding preset value, triggering the second A multi-core CPU interrupt.

Optionally, before the second processor 510 executes the recording of the first type entry in the instruction address table corresponding to the first processing unit, it is further configured to execute:

Obtain the instruction address in the current function return address register of the first processing unit through the JTAG interface 530;

adding the instruction address in the current function return address register of the first processing unit to the first type entry;

Before the second processor 510 executes the recording of the other first-type entry in the instruction address table corresponding to the second processing unit, it is further configured to:

Obtain the instruction address in the current function return address register of the second processing unit through the JTAG interface 530;

Add the instruction address in the current function return address register of the second processing unit to the other first type entry.

Optionally, the second processor 510 detects that the first processing unit stops responding, including executing:

receiving instruction information sent by the main core in the first multi-core CPU, where the instruction information carries the identifier of the first processing unit;

The second processor 510 determines, according to the indication information, that the first processing unit stops responding.

Further, the second processor 510 is further configured to sequentially read a first-type entry from the instruction address table corresponding to the first processing unit according to the order in which the entries are stored, and for each read A first-type entry, execute:

According to the instruction address in the PC included in the first-type table entry, the first-type table is queried to obtain the first-type table from the preset correspondence between the instruction address in the first processing unit, the function name, and the code line The function name and code line corresponding to the instruction address in the PC included in the item;

Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry;

According to the order in which the entries of the second type are generated, the entries of the second type are recorded in the function operation table corresponding to the first processing unit.

Further, the second processor 510 is further configured to sequentially read a first-type entry from the instruction address table corresponding to the second processing unit according to the order in which the entries are stored, and for each read For the first type of entry, execute:

According to the instruction address in the PC included in the first-type table entry, the first-type table is queried to obtain the first-type table from the preset correspondence between the instruction address in the second processing unit, the function name, and the code line The function name and code line corresponding to the instruction address in the PC included in the item;

Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry;

According to the order in which the entries of the second type are generated, the entries of the second type are recorded in the function operation table corresponding to the second processing unit.

The device 500 provided in this embodiment can be integrated in the control chip 102 shown in FIG. 1, and the hardware platform including the device 500 and the first multi-core CPU is integrated in the network device 100 shown in FIG. 1, the The first CPU may be the CPU 101 shown in FIG. 1 , the first processing unit may be the first processing unit 1011 shown in FIG. 1 , and the second processing unit may be the second processing unit 1012 shown in FIG. 1 .

Optionally, the JTAG interface 530 is integrated in a monitoring chip, the second processor 510 is integrated in a main control chip, and the monitoring chip communicates with the first multi-core CPU through the JTAG channel, The main control chip communicates with the monitoring chip through the bus 540 .

For example, the device 500 is integrated in the control chip 102 shown in FIG. 1, the JTAG interface is integrated in the monitoring chip 1022 shown in FIG. 1, and the second processor 510 is integrated in the In the main control chip 1021, the first CPU may be the CPU 101 shown in FIG. 1 . The bus 540 between the second processor 510 and the JTAG interface 530 can be realized by the bus between the main control chip 1021 shown in Figure 1 and the monitoring chip 1022, and the JTAG channel can be realized by the bus shown in Figure 1 The bus between the monitoring chip 1022 and the CPU 101 is realized. For the specific structure of the connection between the main control chip 1011 , the monitoring chip 1021 and the CPU 101 , please refer to the detailed description in FIG. 1 .

The apparatus 500 for generating a processor fault record provided in this embodiment can be applied to the method of the embodiment in FIG. 3 to realize the function of the control chip. For other additional functions that the apparatus 500 can implement and the interaction process with the first multi-core CPU, please refer to the description of the control chip in the method embodiment, and details will not be repeated here.

Through the above solution, when the first processing unit stops responding, the fault record generation device obtains multiple instruction addresses stored in the PC of the first processing unit within a period of time through the JTAG channel and records them in the instruction address table. The instruction address table reflects the state of the program running by the first processing unit within a period of time after the first processing unit stops responding. At the same time, the fault record generation device also records the instruction address stored in the PC of the second processing unit in the same multi-core CPU as the first processing unit. Due to an infinite loop, the infinite loop function and a corresponding section of code line will be called repeatedly, and in a multi-core CPU, there are mutual calls between functions between different slave cores. Therefore, the method provided by this application is better than the existing In the technology, an interrupt is triggered immediately after detecting that the first processing unit stops responding, and only the address of the instruction being executed by the first processing unit and the second processing unit at the time of the interruption is recorded, so as to more accurately reflect the occurrence of the dead Loop function and code section help to improve the efficiency of CPU fault analysis.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, refer to part of the description of the method embodiment.

Apparently, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims (25)

1. A method for generating a processor failure record, characterized in that, it is applied to a hardware platform comprising a control chip and a central processing unit CPU, The methods include: The control chip detects that a processing unit in the CPU stops responding; The control chip obtains the instruction address in the current program counter PC of the processing unit through the joint test action group JTAG channel; The control chip creates a first-type entry including the instruction address in the current PC, and records the first-type entry in the instruction address table; The control chip judges whether the number of entries recorded in the instruction address table reaches a preset value, and the preset value is greater than or equal to 2; If the number of entries recorded in the instruction address table does not reach the preset value, the control chip returns to execute the step of obtaining the instruction address in the current program counter PC of the processing unit through the JTAG channel; If the number of entries recorded in the instruction address table reaches the preset value, the control chip triggers the CPU interrupt. 2. The method according to claim 1, wherein, before recording the first type entry in the instruction address table, further comprising: The control chip obtains the instruction address in the current function return address register of the processing unit through the JTAG channel; The control chip adds the instruction address in the current function return address register to the first type entry. 3. The method according to claim 1 or 2, wherein before recording the first type of entry in the instruction address table, further comprising: The control chip acquires the current time, and adds the current time to the first type entry. 4. The method according to claim 1, 2, or 3, wherein the recording the first type of entry in the instruction address table comprises: The control chip records the first type of entries in the instruction address table according to the sequence in which the first type of entries are generated. 5. The method according to any one of claims 1 to 4, wherein the control chip returns to execute the step of obtaining the instruction address in the current PC of the processing unit through the JTAG channel, comprising: The control chip delay time period T1; After the time period T1 arrives, the control chip returns to execute the step of obtaining the instruction address in the current PC of the processing unit through the JTAG channel. 6. The method according to any one of claims 1 to 5, wherein the control chip detects that the processing unit stops responding, comprising: The control chip detects the heartbeat of the processing unit, and determines that the processing unit stops responding. 7. The method according to any one of claims 1 to 6, further comprising: The control chip sequentially reads a first-type entry from the instruction address table according to the sequence in which the entries are stored, and executes for each read first-type entry: According to the instruction address in the PC included in the first type of entry, the control chip obtains the first The function name and code line corresponding to the instruction address in the PC included in the class entry; The control chip creates a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry; The control chip records the second type of entries in the function operation table according to the sequence in which the second type of entries are generated. 8. The method of claim 2, further comprising: The control chip sequentially reads a first-type entry from the instruction address table according to the sequence in which the entries are stored, and executes for each read first-type entry: According to the instruction address in the PC included in the first type of entry, the control chip obtains the first The function name and code line corresponding to the instruction address in the PC included in the class entry; The control chip, according to the instruction address in the function return register included in the first type of entry, obtains the The function name and code line corresponding to the instruction address in the return register included in the first type of entry; The control chip creates a second type of table entry, the second type of table entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of table entry, and the first type of table entry The function included in the item returns the function name and code line corresponding to the instruction address in the register; The control chip records the second type of entries in the function operation table according to the sequence in which the second type of entries are generated. 9. A method for generating a processor fault record, characterized in that, it is applied in a hardware platform comprising a control chip and a multi-core CPU, the multi-core CPU comprises a first processing unit and a second processing unit, and the first processing unit and said second processing unit is a slave core in said multi-core CPU, The methods include: The control chip detects that the first processing unit stops responding; If the number of entries recorded in the instruction address table corresponding to the first processing unit does not reach the first preset value, the control chip obtains the current program counter PC of the first processing unit through the joint test working group JTAG channel Instruction address in , the first preset value is greater than or equal to 2, the control chip creates a first-type entry, and records the first-type entry in the instruction address table corresponding to the first processing unit , the first type of entry includes an instruction address in the current PC of the first processing unit; If the number of entries recorded in the instruction address table corresponding to the second processing unit does not reach the second preset value, the control chip obtains the instruction address in the current PC of the second processing unit through the JTAG channel , the second preset value is greater than or equal to 2, the control chip creates another first-type entry, and records the other first-type entry in the instruction address table corresponding to the second processing unit , the other first-type entry includes an instruction address in the current PC of the second processing unit; The control chip determines whether the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit reaches a corresponding preset value; If the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit does not reach the corresponding preset value, the control The chip returns to execute the step of obtaining the instruction address in the current PC of the first processing unit through the JTAG channel; If the number of entries recorded in the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit both reach a corresponding preset value, the control unit triggers an interrupt of the multi-core CPU. 10. The method according to claim 9, wherein before recording the first type of entry in the instruction address table corresponding to the first processing unit, further comprising: The control chip obtains the instruction address in the current function return address register of the first processing unit through the JTAG channel; The control chip adds the instruction address in the current function return address register of the first processing unit to the first type entry; Before recording the other first-type entry in the instruction address table corresponding to the second processing unit, it also includes: The control chip obtains the instruction address in the current function return address register of the second processing unit through the JTAG channel; The control chip adds the instruction address in the current function return address register of the second processing unit to the other first-type entry. 11. The method according to claim 9 or 10, further comprising: The control chip sequentially reads a first-type entry from the instruction address table corresponding to the first processing unit according to the order in which the entries are stored, and executes for each read first-type entry: According to the instruction address in the PC included in the first type of entry, the control chip obtains the The function name and code line corresponding to the instruction address in the PC included in the first type of entry; The control chip creates a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry; The control chip records the second type of entries in the function operation table corresponding to the first processing unit according to the sequence in which the second type of entries are generated. 12. The method according to any one of claims 9 to 11, further comprising: The control chip sequentially reads a first-type entry from the instruction address table corresponding to the second processing unit according to the order in which the entries are stored, and executes for each read first-type entry: According to the instruction address in the PC included in the first type of entry, the control chip obtains the The function name and code line corresponding to the instruction address in the PC included in the first type of entry; The control chip creates a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry; The control chip records the second type of entries in the function operation table corresponding to the second processing unit according to the sequence in which the second type of entries are generated. 13. A device for generating a processor failure record, characterized in that it is applied to a hardware platform comprising the device and a first central processing unit CPU, wherein at least one processing unit is included in the first CPU, and the device passes The JTAG channel communicates with the first CPU, the device includes: a second processor, a memory, and a JTAG interface, and the second processor, the memory, and the JTAG interface are connected through a bus; The JTAG interface is used to obtain the instruction address in the program counter PC of the processing unit in the first CPU through the JTAG channel, and send the instruction address in the PC to the first CPU through the bus. two processors; The second processor is configured to read the program code stored in the memory, and perform the following operations: detecting that a processing unit in the first CPU has stopped responding; Obtain the instruction address in the current program counter PC of the processing unit through the JTAG channel; Create a first type entry including the instruction address in the current PC, and record the first type entry in the instruction address table; judging whether the number of entries recorded in the instruction address table reaches a preset value, and the preset value is greater than or equal to 2; If the number of entries recorded in the instruction address table does not reach the preset value, return to the step of obtaining the instruction address in the current program counter PC of the processing unit through the JTAG channel; If the number of entries recorded in the instruction address table reaches the preset value, an interrupt of the first CPU is triggered. 14. The apparatus of claim 13, wherein: The JTAG interface is also used to obtain the instruction address in the current function return register of the processing unit in the first CPU through the JTAG channel, and pass the current instruction address in the function return register through the The bus is sent to the second processor; The second processor is further configured to perform the following operations before performing the recording of the first type entry in the instruction address table: Obtain the instruction address in the current function return address register of the processing unit through the JTAG channel; Add the instruction address in the current function return address register to the first type entry. 15. The device according to claim 13 or 14, wherein the second processor returns to execute the step of obtaining the instruction address in the current program counter PC of the processing unit through the JTAG channel, comprising: Delay period T1; After the time period T1 arrives, return to the step of obtaining the instruction address in the current program counter PC of the processing unit through the JTAG channel. 16. The device according to any one of claims 13 to 15, wherein the first CPU is a multi-core CPU, and the processing unit is a main core of the first multi-core CPU, The second processor detects that a processing unit in the first CPU stops responding, including performing: A heartbeat detection is performed on the main core, and it is determined that the main core stops responding. 17. The device according to any one of claims 13 to 16, wherein the second processor is further configured to sequentially read a first instruction address table from the instruction address table according to the order in which the entries are stored. Class entry, for each first class entry read, execute: According to the instruction address in the PC included in the first type of entry, from the preset correspondence between the instruction address in the processing unit and the function name and code line, query and obtain the first type of entry The included function name and code line corresponding to the instruction address in the PC; Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry; According to the order in which the second-type entries are generated, the second-type entries are recorded in the function operation table. 18. The device according to claim 14, wherein the second processor is further configured to sequentially read a first-type entry from the instruction address table according to the sequence in which the entries are stored, For each entry of the first type read, execute: According to the instruction address in the PC included in the first type of entry, from the preset correspondence between the instruction address in the processing unit and the function name and code line, query and obtain the first type of entry The included function name and code line corresponding to the instruction address in the PC; According to the instruction address in the function return register included in the first type table item, from the preset correspondence between the instruction address in the processing unit, the function name and the code line, query and obtain the first type table The function included in the item returns the function name and code line corresponding to the instruction address in the register; Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry, and the first type of entry included in the The function returns the function name and code line corresponding to the instruction address in the register; According to the order in which the second type of entries are generated, the second type of entries are recorded in the function operation table. 19. The device according to any one of claims 13 to 18, wherein the JTAG interface is integrated in a monitoring chip, the second processor is integrated in a main control chip, and the monitoring chip passes through the The JTAG channel communicates with the first CPU, and the main control chip communicates with the monitoring chip through a bus. 20. A device for generating a processor failure record, characterized in that it is applied to a hardware platform comprising said device and a first multi-core CPU, said first multi-core CPU comprising a first processing unit and a second processing unit unit, the first processing unit and the second processing unit are slave cores of the first multi-core CPU, and the device communicates with the first multi-core CPU through a joint test working group JTAG channel, and the device Including: a second processor, a memory and a JTAG interface, the second processor, the memory and the JTAG interface are connected through a bus; The JTAG interface is used to obtain the instruction address in the program counter PC of the processing unit in the first multi-core CPU through the JTAG channel, and send the instruction address in the PC to the the second processor; The second processor is configured to read the program code stored in the memory, and perform the following operations: detecting that the first processing unit has stopped responding; If the number of entries recorded in the instruction address table corresponding to the first processing unit has not reached the first preset value, obtain the instruction address in the current program counter PC of the first processing unit through the JTAG interface, and the second a preset value greater than or equal to 2; Create a first type of entry, the first type of entry is recorded in the instruction address table corresponding to the first processing unit, and the first type of entry includes the current PC of the first processing unit command address; If the number of entries recorded in the instruction address table corresponding to the second processing unit does not reach the second preset value, obtain the instruction address in the current PC of the second processing unit through the JTAG interface, and the second processing unit 2. The preset value is greater than or equal to 2; Create another first-type entry, and record the other first-type entry in the instruction address table corresponding to the second processing unit, the other first-type entry includes the first 2. The instruction address in the current PC of the processing unit; judging whether the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit reaches a corresponding preset value; If the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit does not reach the corresponding preset value, return to execute the Describe the step of obtaining the instruction address in the current PC of the first processing unit through the JTAG channel; If the number of entries recorded in at least one of the instruction address table corresponding to the first processing unit and the instruction address table corresponding to the second processing unit reaches the corresponding preset value, triggering the second A multi-core CPU interrupt. 21. The apparatus of claim 20, wherein: The JTAG interface is also used to obtain the instruction address in the current function return register of the processing unit in the first multi-core CPU through the JTAG channel, and pass the current instruction address in the function return register through the The bus is sent to the second processor; Before the second processor executes the recording of the first type entry in the instruction address table corresponding to the first processing unit, it is also used to execute: Obtaining the instruction address in the current function return address register of the first processing unit through the JTAG interface; adding the instruction address in the current function return address register of the first processing unit to the first type entry; Before the second processor executes the recording of the other first-type entry in the instruction address table corresponding to the second processing unit, it is also used to execute: Obtaining the instruction address in the current function return address register of the second processing unit through the JTAG interface; Add the instruction address in the current function return address register of the second processing unit to the other first type entry. 22. The device according to claim 20 or 21, wherein the second processor detects that the first processing unit stops responding, comprising executing: receiving instruction information sent by the main core in the first multi-core CPU, where the instruction information carries the identifier of the first processing unit; The second processor determines, according to the indication information, that the first processing unit stops responding. 23. The device according to any one of claims 20 to 22, wherein the second processor is further configured to, according to the order in which the entries are stored, successively select the instruction address table corresponding to the first processing unit Read a first-type entry in , and for each first-type entry read, execute: According to the instruction address in the PC included in the first-type table entry, the first-type table is queried to obtain the first-type table from the preset correspondence between the instruction address in the first processing unit, the function name, and the code line The function name and code line corresponding to the instruction address in the PC included in the item; Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry; According to the order in which the entries of the second type are generated, the entries of the second type are recorded in the function operation table corresponding to the first processing unit. 24. The device according to any one of claims 20 to 23, wherein the second processor is further configured to sequentially select the instruction address table corresponding to the second processing unit according to the order in which the entries are stored. To read a first-type entry, for each first-type entry read, execute: According to the instruction address in the PC included in the first-type table entry, the first-type table is queried to obtain the first-type table from the preset correspondence between the instruction address in the second processing unit, the function name, and the code line The function name and code line corresponding to the instruction address in the PC included in the item; Create a second type of entry, the second type of entry includes the function name and code line corresponding to the instruction address in the PC included in the first type of entry; According to the order in which the entries of the second type are generated, the entries of the second type are recorded in the function operation table corresponding to the second processing unit. 25. The device according to any one of claims 20 to 24, wherein the JTAG interface is integrated in a monitoring chip, the second processor is integrated in a main control chip, and the monitoring chip passes through the The JTAG channel communicates with the first multi-core CPU, and the main control chip communicates with the monitoring chip through a bus.