CN106941104B - A kind of charge trap-type nonvolatile storage production method of the high pressure resistant transistor of combination - Google Patents
A kind of charge trap-type nonvolatile storage production method of the high pressure resistant transistor of combination Download PDFInfo
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Abstract
A kind of charge trap-type nonvolatile storage production method of the high pressure resistant transistor of combination, comprising: deposit ONO layer in the active area of silicon-based substrate and shallow channel isolation area；The deposit polycrystalline silicon layer on ONO layer；The first insulating layer of at least silicon nitride containing layer is deposited on the polysilicon layer；Control gate is formed by etching, and removes the polysilicon of memory block and external zones；Insulation film is formed in the noncontrolled area of memory block and external zones；The deposit polycrystalline silicon on insulation film；In the second insulating layer that polysilicon surface deposition includes silicon nitride layer；Dry etching second insulating layer and polysilicon layer are to form external zones grid and memory block side wall type grid；External zones ion implanting is carried out through second insulating layer；The silicon nitride layer of the second insulating layer of the silicon nitride layer and external zones top portions of gates of first insulating layer at synchronous removal control gate top.Good compatibility of the present invention not only ensure that the high breakdown voltage of peripheral circuit requirement, but also will not generate damage to memory block, and the area of storage unit is effectively reduced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of charge trap-types of the high pressure resistant transistor of combination
Nonvolatile storage production method.
Background technique
With the development of technology, flush memory device needs and advanced logical device is combined to reach more preferably performance, and
The programming of flush memory device and the erasable peripheral circuit for needing to be made of logical device provide high pressure, and this requires the tools of logical device
There is higher breakdown voltage.
Under normal conditions, logic can be improved by increasing the energy of the shallow doped-drain of high pressure (HVLDD) ion implanting
The breakdown voltage of device, and higher ion implantation energy can bring the risk for punching grid, can pass through increase again at this time
The method of gate height reduces the risk that grid is punched.But advanced logical device for reduce inter-level dielectric filling difficulty,
The considerations of reduce parasitic capacitance and reduce power consumption etc., would generally reduce gate height, at this moment can be hard by deposition grid
The method of mask increases gate height.
It is easy to know ground, when removing the silicon nitride layer of hard mask version, memory block ONO (oxide-nitride-oxide)
The silicon nitride of layer also needs to protect, and it is certain that this certainly will combine the high pressure resistant device of advanced logic to bring to non-volatile storage area
Difficulty.
Therefore in view of the problems of the existing technology, this case designer relies on the experience for being engaged in the industry many years, actively studies
Improvement, then there is a kind of charge trap-type nonvolatile storage production method of the high pressure resistant transistor of combination of the invention.
Summary of the invention
The present invention be directed in the prior art, when removing the silicon nitride layer of hard mask version, memory block ONO (silica-nitrogen
SiClx-silica) silicon nitride of layer also needs to protect, and this certainly will combine the high pressure resistant device of advanced logic to non-volatile storage area
The defects of bringing certain difficulty provides a kind of charge trap-type nonvolatile storage production of high pressure resistant transistor of combination
Method.
Purpose to realize the present invention, the charge trap-type that the present invention provides a kind of high pressure resistant transistor of combination non-volatile are deposited
Reservoir production method, the charge trap-type nonvolatile storage production method of the high pressure resistant transistor of combination, comprising:
It executes step S1: depositing ONO (oxygen in the active area (AA) of silicon-based substrate and the surface of shallow channel isolation area (STI)
SiClx-silicon-nitride and silicon oxide) layer；
It executes step S2: depositing the first polysilicon layer in the side different from silicon-based substrate of the ONO layer；
It executes step S3: at least containing the first hard mask version in the side deposition different from ONO layer of first polysilicon layer
First insulating layer of silicon nitride layer；
It executes step S4: control gate being formed by etching, and removes the first polysilicon of memory block and external zones；
It executes step S5: forming insulation film in the noncontrolled area of memory block and external zones；
Execute step S6: deposition is used to form the second polycrystalline of selection grid and external zones grid on the insulation film
Silicon；
It executes step S7: including the second insulating layer of the second hard mask version silicon nitride layer in the second polysilicon surface deposition；
Execute step S8: dry etching second insulating layer and the second polysilicon layer are to form external zones grid and memory block side
Wall type grid；
It executes step S9: carrying out shallow doped source drain electrode (LDD) ion implanting of external zones high pressure through second insulating layer；
Execute step S10: the first hard mask version silicon nitride layer of first insulating layer at synchronous removal control gate top and outside
Enclose the second hard mask version silicon nitride layer of the second insulating layer of area's top portions of gates.
Optionally, the first hard mask version silicon nitride layer of first insulating layer at the control gate top and external zones grid top
Second hard mask version silicon nitride series of strata of the second insulating layer in portion are removed by wet etching.
Optionally, in first insulating layer, the thickness of the first hard mask version silicon nitride layer is maximum.
Optionally, in the second insulating layer, the thickness of the second hard mask version silicon nitride layer is maximum.
Optionally, the thickness of the second insulating layer is at least 800 angstroms.
Optionally, the thickness of the second insulating layer is greater than the height of external zones grid.
Optionally, first insulating layer and the second insulating layer are using the technology mode for depositing, while removing respectively.
Optionally, the side wall type grid and external zones grid of memory block use while etching the technology mode of formation.
Optionally, the first hard mask version silicon nitride layer of first insulating layer at the control gate top and external zones grid top
Side wall type grid of the removal of second hard mask version silicon nitride layer of the second insulating layer in portion in the control gate side removes it
Preceding completion.
Optionally, after the side wall type grid removal of the control gate side, opposite other side side wall type grid is
The selection grid of memory block.
In conclusion the present invention, which increases control gate height by the method for control gate hard mask version, forms side wall type choosing
Grid are selected, external zones gate height is increased by the method for peripheral circuit region grid hard mask version and reaches reduction grid by ion
The risk punched is injected, and then improves peripheral logic device electric breakdown strength, and the hard mask version of external zones can shallowly be mixed in high pressure
Miscellaneous drain electrode injection back side wall grid is entirely removed before removing, and the presence because of side wall type grid is to guarantee hard mask version
The silicon nitride layer of memory block ONO (oxide-nitride-oxide) layer will not be caused to damage when removal, can be preferably compatible with
Advanced high pressure logical device and charge trap-type non-volatile memory device both ensure that the higher breakdown potential of peripheral circuit requirement
Pressure, and any damage will not be generated to memory block, and effectively reduce the area of storage unit.
Detailed description of the invention
Fig. 1~Figure 19 show the charge trap-type nonvolatile storage production method that the present invention combines high pressure resistant transistor
Flow chart.
Specific embodiment
By the present invention will be described in detail create technology contents, construction feature, reached purpose and efficacy, below in conjunction with reality
It applies example and attached drawing is cooperated to be described in detail.
With the development of technology, flush memory device needs and advanced logical device is combined to reach more preferably performance, and
The programming of flush memory device and the erasable peripheral circuit for needing to be made of logical device provide high pressure, and this requires the tools of logical device
There is higher breakdown voltage.
Under normal conditions, logic can be improved by increasing the energy of the shallow doped-drain of high pressure (HVLDD) ion implanting
The breakdown voltage of device, and higher ion implantation energy can bring the risk for punching grid, can pass through increase again at this time
The method of gate height reduces the risk that grid is punched.But advanced logical device for reduce inter-level dielectric filling difficulty,
The considerations of reduce parasitic capacitance and reduce power consumption etc., would generally reduce gate height, at this moment can be hard by deposition grid
The method of mask increases gate height.
It is easy to know ground, when removing the silicon nitride layer of hard mask version, memory block ONO (oxide-nitride-oxide)
The silicon nitride of layer also needs to protect, and it is certain that this certainly will combine the high pressure resistant device of advanced logic to bring to non-volatile storage area
Difficulty.
In order to overcome drawbacks described above, the present invention provides a kind of charge trap-type non-volatile memory of high pressure resistant transistor of combination
The production method of device, the production method of the charge trap-type nonvolatile storage of the high pressure resistant transistor of combination, comprising:
It executes step S1: depositing ONO (oxygen in the active area (AA) of silicon-based substrate and the surface of shallow channel isolation area (STI)
SiClx-silicon-nitride and silicon oxide) layer；
It executes step S2: depositing the first polysilicon layer in the side different from silicon-based substrate of the ONO layer；
It executes step S3: at least containing the first hard mask version in the side deposition different from ONO layer of first polysilicon layer
First insulating layer of silicon nitride layer；
It executes step S4: control gate being formed by etching, and removes the first polysilicon of memory block and external zones；
It executes step S5: forming insulation film in the noncontrolled area of memory block and external zones；
Execute step S6: deposition is used to form the second polycrystalline of selection grid and external zones grid on the insulation film
Silicon；
It executes step S7: including the second insulating layer of the second hard mask version silicon nitride layer in the second polysilicon surface deposition；
Execute step S8: dry etching second insulating layer and the second polysilicon layer are to form external zones grid and memory block side
Wall type grid；
It executes step S9: carrying out shallow doped source drain electrode (LDD) ion implanting of external zones high pressure through second insulating layer；
Execute step S10: the first hard mask version silicon nitride layer of first insulating layer at synchronous removal control gate top and outside
Enclose the second hard mask version silicon nitride layer of the second insulating layer of area's top portions of gates.
Without limitation, the first hard mask version silicon nitride layer and external zones grid of first insulating layer at the control gate top
Second hard mask version silicon nitride series of strata of the second insulating layer at pole top are removed by wet etching.In first insulating layer
In, the thickness of the first hard mask version silicon nitride layer is maximum.In the second insulating layer, the second hard mask version nitridation
The thickness of silicon layer is maximum.More specifically, the thickness of the second insulating layer is at least 800 angstroms.The thickness of the second insulating layer
Greater than the height of external zones grid.
First insulating layer and the second insulating layer are using the technology mode for depositing, while removing respectively.Memory block
Side wall type grid and external zones grid using and meanwhile etch the technology mode of formation.First insulating layer at the control gate top
The first hard mask version silicon nitride layer and the second hard mask version silicon nitride layer of second insulating layer of external zones top portions of gates go
Except the side wall type grid of the control gate side removal before complete.Further, the side wall type grid of the control gate side
After the removal of pole, opposite other side side wall type grid is the selection grid of memory block.
In order to more intuitively disclose the technical solution of the present invention, the beneficial effect of the present invention is highlighted, now in conjunction with specific implementation
It is illustrated for mode.
Fig. 1~Figure 19 is please referred to, Fig. 1~Figure 19 show the present invention and combines the charge trap-type of high pressure resistant transistor non-easily
Lose the flow chart of memory production method.The charge trap-type nonvolatile storage production side of the high pressure resistant transistor of combination
Method, comprising:
Execute step S1: by deep trap injection silicon-based substrate 100 on successively carry out prerinse, ONO layer 101 deposition,
First polysilicon 102a deposition, the first hard mask version silicon oxide layer 103a deposition, polysilicon ion injection, prerinse, first are firmly
Mask plate silicon nitride layer 104a deposition.
Wherein, the ONO layer 101 further comprises in being stacked in the silicon-based substrate 100, successively from bottom to top
The first silicon oxide layer 101a, silicon nitride layer 101b, the second silicon oxide layer 101c.The active area of the silicon-based substrate 100 is into one
Step is divided into memory block 100a, peripheral low-voltage device area 100b, periphery high voltage device regions 101c, and is located at memory block 100a and institute
State the frontier district 100d between peripheral components area.
Meanwhile for the ease of brief description of the invention, the periphery low-voltage device area 100b, peripheral high voltage device regions
Frontier district 100d between 101c, memory block 100a and the peripheral components area, three regions are relative to the memory block 100a
Referred to as external zones.
Step the S2: the first photoresist 105a coating development is executed, only covers at the 100a of memory block and is used to form control gate
Top area；
First polysilicon 102a of execution step S3: memory block 100a forms the control of memory block 100a after dry etching
Grid 106 processed, the first polysilicon 102a of peripheral circuit region are etched removal simultaneously, and etch and terminate at the of the ONO layer 101
Silicon dioxide layer 101c, and layer 107 is reoxidized in 106 side wall of control gate formation by oxidation technology.It is apparent that active area
It is oxidized since the blocking by silicon nitride layer can be effectively prevented.
Execute step S4: oxide isotropic etching terminates at the silicon nitride layer 101b of ONO layer 101.
Step the S5: the second photoresist 105b coating development is executed, the second photoresist 105b covers peripheral low-voltage device
Area 100b, periphery high voltage device regions 100c and frontier district 100d, and carry out ion implanting.
It is apparent that being covered in the peripheral low-voltage device area 100b, periphery high voltage device regions 100c and frontier district 100d
The first hard mask version silicon oxide layer 103a at 106 top the second photoresist 105b and the control gate and the nitridation of the first hard mask version
Silicon 104a can effectively stop the ion implanting, so that effective ion injection zone be made to be only limitted to the non-control of the memory block 100a
Gate region processed.
As those skilled in the art, it is readily appreciated that ground, the ion implanting is to form selection gate groove, will be described
Ion implantation technology can reduce ONO layer 101 and grow generated influence of the fuel factor to ion implanting when being placed in herein.However,
The processing step of the ion implanting can carry out sequence change on demand, be not limited to this, be not construed as to the technology of the present invention side
The limitation of case.
It executes step S6: after removal the second photoresist 105b, removing active area ONO layer respectively by wet etching
101 silicon nitride layer 101b and the first silicon oxide layer 101a.
It executes step S7: after prerinse, carrying out the first thick grating oxide layer 108a deposition；
It executes step S8: third photoresist 105c coating development and exposes peripheral low-voltage device area 100b, pass through wet etching
Remove the first thick grating oxide layer 108a of peripheral low-voltage device area 100b；
It executes step S9: after removal third photoresist 105c, carrying out thin gate oxide deposition, finally in the peripheral low pressure
Device region 100b forms thin gate oxide 109, and peripheral high voltage device regions 100c forms the second thick grating oxide layer 108b, memory block
The non-controlling gate region of 100a forms the second thick grating oxide layer 108b.It is apparent that in the non-controlling grid region of the memory block 100a
Domain also can form thin gate oxide according to process requirements.
Execute step the S10: the second polysilicon 102b deposition, the second polysilicon 102b cover simultaneously memory block 100a,
Peripheral low-voltage device area 100b, periphery high voltage device regions 100c and frontier district 100d, to be used to form the selection of memory block 100a
The grid of grid and external zones.
The S11: the four photoresist 105d of step coating development is executed, P-type transistor region is covered, carries out N-type ion injection
Annealing reduces gate oxide electrical thickness to inhibit poly-Si depletion effect.It is apparent that in the art also can be according to technique
It needs to choose whether to execute the step.
It executes step S12: being successively sequentially depositing the second hard mask version silicon oxide layer on the second polysilicon 102b
103b and the second hard mask version silicon nitride layer 104b, and the 5th photoresist 105e coating development is carried out, and the 5th photoresist
105e is covered in the top area for being used to form grid of external zones.
It executes step S13: penetrating 104b pairs of silicon nitride layer of the second hard mask version silicon oxide layer 103b and the second hard mask version
The second polysilicon 102b is performed etching, and forms side wall type grid 110 in memory block 100a, forms grid in external zones
111。
The S14: the six photoresist 105f of step coating development is executed, exposes periphery high voltage device regions 100c, it is shallow to carry out high pressure
Doped-drain (HVLDD) ion implanting.It is apparent that due to by second in the shallow doped-drain ion implantation process of the high pressure
The protection of hard mask version silicon oxide layer 103b and the second hard mask version silicon nitride layer 104b, avoid grid punches risk.
Execute step S15: the 6th photoresist 105f removal carries out silicon nitride wet etching, to remove control gate
The second hard mask version silicon nitride layer at 111 top the first hard mask version silicon nitride layer 104a and external zones grid at 106 tops
104b, and the silicon nitride layer 101b of the ONO layer 101 at the 100a of memory block avoided under the protection of the side wall type grid 110 by
Damage.
The S16: the seven photoresist 105g of step coating development is executed, the 7th boundary photoresist 105g is arranged in the control
The top of first hard mask version silicon oxide layer 103a of grid 106 processed.
Execute step S17: the polysilicon between etching removal control gate 106 removes the 7th photoresist 105g, then with shape
At the grid 111 of the control gate 106 of memory block 100a, side wall type grid 110 and external zones.
It executes step S18: by grid curb wall deposition, grid curb wall etching technics, forming grid curb wall 112.
Execute step S19: at the top of the side wall type grid 110,106 top of control gate, external zones grid 111 and active
Area forms metal silicide 113.It is apparent that the height due to side wall type grid 110 is greater than the height of control gate 106, then it is described
The grid curb wall 112 of side wall type grid 110 is effectively prevented positioned at 106 top of control gate and the side wall type grid
The metal silicide 113 at 110 tops is shorted.
As the specific embodiment of the present invention, without limitation, more than described first deposited in the silicon-based substrate 100
Crystal silicon 102a with a thickness of 1000~1500 angstroms, the hard mask version silicon oxide layer 103 with a thickness of 100~200 angstroms, it is described hard
Mask silicon nitride layer 104 with a thickness of 500~1000 angstroms.It is described reoxidize layer 107 with a thickness of 10~30nm.
In conclusion the present invention, which increases control gate height by the method for control gate hard mask version, forms side wall type choosing
Grid are selected, external zones gate height is increased by the method for peripheral circuit region grid hard mask version and reaches raising reduction grid quilt
The risk that ion implanting is punched, and then peripheral logic device electric breakdown strength is improved, and the hard mask version of external zones can be in high pressure
Shallow doped-drain injection back side wall grid is entirely removed before removing, and guarantees to cover firmly because of the presence of side wall type grid
Template will not cause to damage when removing to the silicon nitride layer of memory block ONO (oxide-nitride-oxide) layer, can be preferably
Compatible advanced high pressure logical device and charge trap-type non-volatile memory device, both ensure that the higher of peripheral circuit requirement was hit
Voltage is worn, and any damage will not be generated to memory block, and effectively reduce the area of storage unit.
Those skilled in the art, can be to this hair it will be appreciated that without departing from the spirit or scope of the present invention
It is bright to carry out various modifications and modification.Thus, if any modification or modification fall into the protection of the appended claims and equivalent
When in range, it is believed that the present invention covers these modifications and variations.
Claims (8)
1. a kind of charge trap-type nonvolatile storage production method of the high pressure resistant transistor of combination, which is characterized in that the knot
Close the charge trap-type nonvolatile storage production method of high pressure resistant transistor, comprising:
It executes step S1: depositing ONO (silica-in the active area (AA) of silicon-based substrate and the surface of shallow channel isolation area (STI)
Silicon-nitride and silicon oxide) layer；
It executes step S2: depositing the first polysilicon layer in the side different from silicon-based substrate of the ONO layer；
It executes step S3: at least being nitrogenized containing the first hard mask version in the side deposition different from ONO layer of first polysilicon layer
First insulating layer of silicon layer；
Execute step S4: by etching form control gate, and remove memory block non-controlling gate region and external zones more than first
Crystal silicon；
It executes step S5: forming insulation film in the noncontrolled area of memory block and external zones, the noncontrolled area is non-controlling grid
Region；
Execute step S6: deposition is used to form the second polysilicon of selection grid and external zones grid on the insulation film；
It executes step S7: including the second insulating layer of the second hard mask version silicon nitride layer in the second polysilicon surface deposition；
Execute step S8: dry etching second insulating layer and the second polysilicon layer are to form external zones grid and memory block side wall type
Grid；
It executes step S9: carrying out shallow doped source drain electrode (LDD) ion implanting of external zones high pressure through second insulating layer；
Execute step S10: the first hard mask version silicon nitride layer and external zones top portions of gates of first insulating layer at control gate top
Side wall type grid of the synchronous removal in the control gate side of the second hard mask version silicon nitride layer of second insulating layer remove
It completes before, after the side wall type grid removal of the control gate side, opposite other side side wall type grid is memory block
Selection grid.
2. combining the charge trap-type nonvolatile storage production method of high pressure resistant transistor, feature as described in claim 1
It is, the second of the first hard mask version silicon nitride layer of first insulating layer at the control gate top and external zones top portions of gates is absolutely
Second hard mask version silicon nitride series of strata of edge layer are removed by wet etching.
3. combining the charge trap-type nonvolatile storage production method of high pressure resistant transistor, feature as described in claim 1
It is, in first insulating layer, the thickness of the first hard mask version silicon nitride layer is maximum.
4. combining the charge trap-type nonvolatile storage production method of high pressure resistant transistor, feature as described in claim 1
It is, in the second insulating layer, the thickness of the second hard mask version silicon nitride layer is maximum.
5. combining the charge trap-type nonvolatile storage production method of high pressure resistant transistor, feature as claimed in claim 4
It is, the thickness of the second insulating layer is at least 800 angstroms.
6. combining the charge trap-type nonvolatile storage production method of high pressure resistant transistor, feature as claimed in claim 4
It is, the thickness of the second insulating layer is greater than the height of external zones grid.
7. combining the charge trap-type nonvolatile storage production method of high pressure resistant transistor, feature as described in claim 1
It is, first insulating layer and the second insulating layer are using the technology mode for depositing, while removing respectively.
8. combining the charge trap-type nonvolatile storage production method of high pressure resistant transistor, feature as described in claim 1
It is, the side wall type grid and external zones grid of memory block use while etching the technology mode of formation.
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| US6274430B1 (en) * | 2000-07-07 | 2001-08-14 | United Microelectronics Corp. | Fabrication method for a high voltage electrical erasable programmable read only memory device |
| CN1855425A (en) * | 2005-04-26 | 2006-11-01 | 美格纳半导体有限会社 | Method for manufacturing a semiconductor device |
| KR20060124868A (en) * | 2005-05-26 | 2006-12-06 | 동부일렉트로닉스 주식회사 | Gate forming method of flash memory device |
| CN101165903A (en) * | 2006-10-19 | 2008-04-23 | 三星电子株式会社 | Nonvolatile memory device including double diffused junction region and method of manufacturing the same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6274430B1 (en) * | 2000-07-07 | 2001-08-14 | United Microelectronics Corp. | Fabrication method for a high voltage electrical erasable programmable read only memory device |
| CN1855425A (en) * | 2005-04-26 | 2006-11-01 | 美格纳半导体有限会社 | Method for manufacturing a semiconductor device |
| KR20060124868A (en) * | 2005-05-26 | 2006-12-06 | 동부일렉트로닉스 주식회사 | Gate forming method of flash memory device |
| CN101165903A (en) * | 2006-10-19 | 2008-04-23 | 三星电子株式会社 | Nonvolatile memory device including double diffused junction region and method of manufacturing the same |
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