CN106970519A - Time test circuit and time method of testing - Google Patents

Abstract

The invention relates to a time testing circuit, which includes a voltage comparator, an oscillator, a plurality of D latches, a temperature encoder and a counter. The voltage comparator can output a pair of step signals with steep rising edges as the internal transmission signal of time start and time end; the oscillator is a delay chain circuit composed of multi-level gate delay units connected in series, and the oscillator is connected with the voltage comparator, The counter is connected. Each level of gate delay unit is connected to a D latch, and the output end of the time end signal in the voltage comparator is respectively connected to the clock signal input end of each D latch, and the signal output end of each D latch is connected to the temperature encoder connected to the input. The time test circuit works, and calculates the delay time t through the formula t=N×n×T _LSB +n ₁ ×T _LSB , where N is the count value of the counter, n is the total number of stages of the gate delay unit in the delay chain, T _LSB is the delay time of a single gate delay unit. The time test circuit and the time test method can reduce the inversion time of signals at various levels of gate delay and reduce power consumption.

Description

Time test circuit and time test method

technical field

The invention relates to the technical field of digital circuits, in particular to a time test circuit and a time test method.

Background technique

With the continuous development of integrated circuit size miniaturization, high-precision time test chips have become a research hotspot. The traditional direct counting method realizes time measurement by counting the frequency of the reference clock. When the clock frequency is GHz, its time measurement accuracy It has only reached the ns level, and its accuracy is greatly limited by the frequency of the reference clock, which cannot meet higher measurement accuracy. Then a time measurement method based on delay unit was proposed. The time start signal propagates in the delay chain. When the time end signal arrives, the position where the time start signal propagates is locked. The measured time can be obtained by calculating the number of delay chains. Its accuracy depends on the delay time of each delay unit, and the minimum delay time reaches tens of picoseconds. The gate delay time is affected by factors such as input signal, process, circuit parameter structure and parasitic capacitance resistance. The trigger signal is directly selected as the propagation signal in the delay chain, because the rising edge time of the pulse signal as the trigger signal is relatively long, and at the same time, it is mixed with interference signals. For each stage of the delay chain signal propagation in the delay chain, the signal's inversion time is increased. and power consumption, while interfering signals can easily cause errors in other parts of the circuit.

Contents of the invention

The technical problem to be solved by the present invention is to provide a time test circuit and a time test method that can reduce the inversion time of signals at various levels of gate delay and reduce power consumption in view of the above-mentioned prior art.

The technical solution adopted by the present invention to solve the above-mentioned problems is: a time test circuit, characterized in that it includes a voltage comparator, an oscillator, a plurality of D latches, a temperature encoder and a counter;

The voltage comparator can output a pair of step signals with steep rising edges as internal transmission signals of time start and time end;

The oscillator is a delay chain circuit composed of multi-level gate delay units connected in series, the input end of the first level gate delay unit is connected to the time start signal output end in the voltage comparator, and the output of the last level gate delay unit terminal is connected with the signal input terminal of the voltage comparator, and the output terminal of the last stage gate delay unit is also connected with the input terminal of the counter;

The output end of each level of gate delay unit is connected to the data input end of a D latch, and the time end signal output end in the voltage comparator is connected to the clock signal input end of each D latch respectively, and each D latch The signal output terminals of each are connected with the input terminals of the temperature encoder.

Preferably, the delay chain circuit includes 50 stages of gate delay units.

A semi-static double-edge trigger is used for the temperature encoder.

A time testing method using the aforementioned time testing circuit is characterized in that it comprises the following steps:

Step 1, using a voltage comparator to generate a pair of step signals with steep rising edges as internal transmission signals for the start of time and the end of time;

Step 2, when the voltage comparator detects that the time start signal is triggered, then control the time start signal to propagate in the delay chain circuit;

Step 3. Before the time-end signal is triggered, the counter performs counting work after each step signal propagates to the last stage of gate delay unit;

Step 4. When the voltage comparator detects that the time-out signal is triggered, the counter stops working, and at the same time, each D latch latches the state of each gate delay unit, and transmits the state signal of each gate delay unit to the temperature encoder. The encoder obtains the number of stages n ₁ of the delay unit to which the step signal propagates;

Step 5. Calculate the delay time t by the formula t=N×n×T _LSB +n ₁ ×T _LSB , where N is the count value of the counter, n is the total number of stages of the gate delay unit in the delay chain, and T _LSB is a single gate The delay time of the delay unit.

As an improvement, it also includes step 6, looking up the table of t according to DNL and INL, and correcting the whole circuit.

As a further improvement, the step signal output by the voltage comparator is subjected to voltage division processing, so as to obtain a step signal with a shorter rising edge as the internal transmission signal of time start and time end.

Compared with the prior art, the present invention has the advantages that: on the basis of the traditional time-to-digital converter, the time test circuit utilizes a voltage comparator to generate a step signal with a steep rising edge as the time start and time end control signals. As the internal transmission signal for time measurement, the step signal has a longer rising edge time than the external input pulse signal and is mixed with interference signals, which reduces the flip time of the signal in the gate delay unit, reduces power consumption, and avoids the impact of interference signals on circuit effects. The step signal is transmitted in the oscillator, and after each cycle, it is sent to the delay unit again until the time-out signal is triggered, thereby ending the propagation of the step signal. At this point, the D latch latches all gate delay cell states. The delay time is obtained from the counter value and temperature encoder value. Because the gate delay time is affected by environmental factors such as temperature, process, and voltage, the interference of these factors on the gate delay time can be reduced by calibration.

Description of drawings

FIG. 1 is a circuit block diagram of a time test circuit in an embodiment of the present invention.

Fig. 2 is a timing diagram of the time test circuit in the embodiment of the present invention.

detailed description

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

As shown in FIG. 1 , the time test circuit in this embodiment is characterized in that it includes a voltage comparator 1 , an oscillator 2 , a plurality of D latches 3 , a temperature encoder 4 and a counter 5 .

The voltage comparator 1 can be composed of a bias circuit, a differential amplifier, a common source amplifier, and a push-pull stage output circuit. Since the rising edge time of the signal output by the voltage comparator 1 is too long, the capacitance will be increased during delay propagation in the oscillator 2 The charging and discharging time will increase the delay time of the single gate delay unit 21 accordingly. Therefore, the step signal output by the voltage comparator 1 is divided to obtain a step signal with a shorter rising edge as the start of the time and the end of the time. Stop internal transmission signal. In this way, the flipping time of each gate delay unit 21 in the delay chain can be reduced, which greatly improves the accuracy of the time test circuit. In this embodiment, a step signal with a rising edge of 100 ps is finally generated as the internal transmission signal of the time start Start and the time end Stop. If the rising edge time continues to decrease, it will not be able to ensure that the MOS capacitor has enough charging and discharging time, and the output will get a disordered step signal, which will cause the entire timing circuit to output wrong results.

The oscillator 2 is a delay chain circuit composed of multiple stages of gate delay units 21 connected in series. In this embodiment, the delay chain circuit includes 50 stages of gate delay units 21 . The input terminal of the first stage gate delay unit 21 is connected with the time start signal Start output terminal in the voltage comparator 1, and the output terminal of the last stage gate delay unit 21 is connected with the signal input terminal of the voltage comparator 1, and the last stage The output of the gate delay unit 21 is also connected to the input of the counter 5 .

The design of the counter 5 is mainly to increase the measurement range of time. In the fine measurement, the delay unit time is 30ps and 35ps. If the loop delay is not used, the measurement time range is too short. Such a high counting frequency of ordinary counter 5 will cause logic confusion and errors in counter 5. Therefore, this paper uses double-edge counter 5 to reduce the counting frequency by half, while reducing the use of power consumption and latching the output signal.

The output end of each stage gate delay unit 21 is connected to the data input end of a D latch 3, and the time end signal output end in the voltage comparator 1 is connected with the clock signal input end of each D latch 3 respectively, and each D latch The signal output terminals of the register 3 are all connected with the input terminals of the temperature encoder 4. The temperature encoder 4 uses a semi-static double-edge trigger.

As shown in Figure 2, the time testing method carried out by the aforementioned time testing circuit comprises the following steps:

Step 1, using the voltage comparator 1 to generate a pair of step signals with steep rising edges as internal transmission signals for the start of time and the end of time;

Step 2, when the voltage comparator 1 detects that the time start signal is triggered, the control time start signal propagates in the delay chain circuit;

Step 3, before the time-end signal is triggered, after each step signal propagates to the last stage of gate delay unit 21, the counter 5 performs counting work;

Step 4: After the voltage comparator 1 detects that the time-out signal is triggered, the counter 5 stops working, and at the same time, each D latch 3 latches the state of each gate delay unit 21, and transmits the state signal of each gate delay unit 21 to A temperature encoder 4, the temperature encoder 4 obtains the number of stages n ₁ of the delay unit to which the step signal propagates;

Step 5, calculate delay time t by formula t=N×n×T _LSB +n ₁ ×T _LSB , wherein N is the count value of counter 5, and n is the total number of stages of gate delay unit 21 in the delay chain, and T _LSB is The delay time of a single gate delay unit 21.

Step 6: Look up t according to DNL and INL, and correct the entire circuit. Through the correction, the interference of environmental factors such as temperature, process and voltage on the gate delay time can be reduced.

The entire time measurement circuit design is completed under the TSMC 180nm process. Through Cadence Specter simulation, the minimum measurement time of the time measurement circuit is 20ps, the maximum measurement time is 16ns, the differential nonlinearity (DNL) is 0.6LSB, and the integral nonlinearity (INL) is 2.2LSB.

Claims (6)

1. A time test circuit, characterized in that: comprise a voltage comparator, an oscillator, a plurality of D latches, a temperature encoder and a counter; The voltage comparator can output a pair of step signals with steep rising edges as internal transmission signals of time start and time end; The oscillator is a delay chain circuit composed of multi-level gate delay units connected in series, the input end of the first level gate delay unit is connected to the time start signal output end in the voltage comparator, and the output of the last level gate delay unit terminal is connected with the signal input terminal of the voltage comparator, and the output terminal of the last stage gate delay unit is also connected with the input terminal of the counter; The output end of each level of gate delay unit is connected to the data input end of a D latch, and the time end signal output end in the voltage comparator is connected to the clock signal input end of each D latch respectively, and each D latch The signal output terminals of each are connected with the input terminals of the temperature encoder. 2. The time test circuit according to claim 1, wherein the delay chain circuit comprises 50 stages of gate delay units. 3. The time test circuit according to claim 1, characterized in that: the temperature encoder adopts a semi-static double-edge trigger. 4. A time testing method using the time testing circuit according to any one of claims 1 to 3, characterized in that it comprises the steps of: Step 1, using a voltage comparator to generate a pair of step signals with steep rising edges as internal transmission signals for the start of time and the end of time; Step 2, when the voltage comparator detects that the time start signal is triggered, then control the time start signal to propagate in the delay chain circuit; Step 3. Before the time-end signal is triggered, the counter performs counting work after each step signal propagates to the last stage of gate delay unit; Step 4. When the voltage comparator detects that the time-out signal is triggered, the counter stops working, and at the same time, each D latch latches the state of each gate delay unit, and transmits the state signal of each gate delay unit to the temperature encoder. The encoder obtains the number of stages n ₁ of the delay unit to which the step signal propagates; Step 5. Calculate the delay time t by the formula t=N×n×T _LSB +n ₁ ×T _LSB , where N is the count value of the counter, n is the total number of stages of the gate delay unit in the delay chain, and T _LSB is a single gate The delay time of the delay unit. 5. The time testing method according to claim 4, further comprising step 6, performing a table look-up of t according to DNL and INL, and correcting the entire circuit. 6. The time testing method according to claim 4, characterized in that: the step signal output by the voltage comparator is subjected to voltage division processing, thereby obtaining a step signal with a shorter rising edge as the start of time and the end of time the internal transmission signal.