CN106973245A - Image sensor and image capturing device using the same - Google Patents

Abstract

The invention provides an image sensor and an influence capturing device using the same. The image sensor includes an image sensing array and a voltage supply array. The image sensing array and the voltage supply array are coupled to the analog-to-digital converter array. The image sensing array captures image data. The image sensor array supports one of a rolling shutter mechanism and a global shutter mechanism according to a setting. The voltage supply array comprises a plurality of voltage supply circuits for providing a setting voltage. During the auto-calibration period, the voltage supply array provides a pseudo-setup voltage to the ADC array. A plurality of comparators of the analog-to-digital converter array perform an auto-calibration function according to the pseudo-set voltage. After the comparator completes the automatic correction function, the image sensing array outputs the image data to the analog-to-digital converter array. The analog-to-digital converter array converts the image data into digitized image data. The circuit design of the image sensor is more simplified, the manufacture is easy and the manufacturing cost is low.

Description

Image sensor and image capture device using same

technical field

The present invention relates to an image sensor, and in particular to an image sensor capable of supporting a rolling shutter mechanism and a global shutter mechanism, and an image capture device using the same.

Background technique

With the development of optoelectronic products, the demand for image sensors is also increasing. Image sensors can be roughly divided into two categories: Complementary Metal-Oxide-Semiconductor (CMOS) image sensors and charge-coupled device (CCD) image sensors. Image sensing devices are widely used due to their advantages of low power consumption and low manufacturing cost.

The image sensor includes a plurality of pixels arranged in a matrix and a plurality of comparators. If the image sensor is a Column Analog-to-Digital Converter (Column Analog-to-Digital Converter) structure, the pixels in the same row among the plurality of pixels are coupled to the same comparator. Each pixel is used for sensing a brightness information and correspondingly generating an image data. Each pixel generally includes a photosensitive element and a reading circuit composed of at least one output transistor. Furthermore, the photosensitive element is used for sensing incident light, and correspondingly outputs charges to a floating diffusion region for storage. The output transistor converts the charge accumulated and stored in the floating diffusion area into image data and outputs it to the comparator. The comparator then outputs a corresponding comparison result to the back-end image processing circuit according to the image data and a reference voltage to generate a corresponding image.

The current image sensor can support two mechanisms, namely a rolling shutter mechanism and a global shutter mechanism. When the image sensor works in the rolling shutter mechanism, a plurality of pixels are exposed row by row to generate image data, and then the image data is provided to the comparator row by row. On the other hand, when the image sensor works under the global shutter mechanism, all the pixels are exposed at the same time, and then the plurality of pixels provide image data to the comparator column by column.

Each comparator has a different bias voltage when the image sensor works in rolling shutter mechanism and global shutter mechanism. Generally, the image sensor uses two sets of comparators and image processing circuits to process the image data output by the rolling shutter mechanism and the global shutter mechanism respectively. If the same comparator and image processing circuit are used to meet two different bias voltages, the design of the comparator will be complicated and difficult to realize. However, using two sets of comparators and image processing circuits will increase the cost and area of the image sensor.

Contents of the invention

The present invention provides an image sensor and an image capture device using it to solve the problem that the image sensor in the prior art uses two sets of comparators and image processing circuits to separately process the output under the rolling shutter mechanism and the global shutter mechanism. The technical problem of cost and area increase brought about by the image data.

An embodiment of the invention provides an image sensor. The image sensor includes an image sensor array and a voltage supply array. The image sensor array and the voltage supply array are coupled to an analog-to-digital converter array. The analog-to-digital converter array includes a plurality of comparators. The image sensor array includes a plurality of pixels. The image sensing array is used for capturing image data. The image sensor array supports one of a rolling shutter mechanism and a global shutter mechanism according to settings. The voltage supply array includes a plurality of voltage supply circuits for providing a preset voltage. During auto-calibration, the voltage supply array provides a desired voltage to the analog-to-digital converter array. The plurality of comparators perform an automatic calibration function according to the intended voltage. After the plurality of comparators complete the automatic calibration function, the image sensor array outputs image data to the analog-to-digital converter array. The analog-to-digital converter array converts the image data into digital image data.

An embodiment of the present invention provides an image capture device. The image capture device includes an analog-to-digital converter array and an image sensor. The image sensor includes an image sensor array and a voltage supply array. The image sensor array and the voltage supply array are coupled to the analog-to-digital converter array. The analog-to-digital converter array includes a plurality of comparators. The image sensor array includes a plurality of pixels. The image sensing array is used for capturing image data. The image sensor array supports one of a rolling shutter mechanism and a global shutter mechanism according to settings. The voltage supply array includes a plurality of voltage supply circuits for providing a preset voltage. During auto-calibration, the voltage supply array provides a desired voltage to the analog-to-digital converter array. The plurality of comparators perform an automatic calibration function according to the intended voltage. After the plurality of comparators complete the automatic calibration function, the image sensor array outputs image data to the analog-to-digital converter array. The analog-to-digital converter array converts the image data into digital image data.

To sum up, the image sensor provided by the embodiment of the present invention and the image capture device using it provide a stable preset voltage to the comparator of the analog-to-digital converter array through the voltage supply array, so that the image capture The device uses the same analog-to-digital converter array and image processing circuit to realize the rolling shutter mechanism and the global shutter mechanism, and generate corresponding images. Compared with the traditional image capture device, the circuit design of the image sensor and the image capture device using the image sensor provided by the embodiment of the present invention is more simplified, easy to manufacture and low in manufacturing cost.

In order to enable a further understanding of the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings of the present invention, but these descriptions and accompanying drawings are only used to illustrate the present invention, not to claim the rights of the present invention any limitations on the scope.

Description of drawings

FIG. 1 is a schematic diagram of an image capturing device provided by an embodiment of the present invention.

FIG. 2 is a schematic diagram of an image sensor and an analog-to-digital converter array provided by an embodiment of the present invention.

Fig. 3 is a schematic diagram of a comparator provided by an embodiment of the present invention.

FIG. 4 is an operation waveform diagram of a traditional comparator in a rolling shutter mechanism and a global shutter mechanism.

FIG. 5 is an operation waveform diagram of the comparator provided by the embodiment of the present invention.

Explanation of reference signs:

1: Image capture device

10: Image sensor

11: Analog-to-digital converter array

12: Image processing circuit

100: row pixel matrix

101: Voltage supply circuit

110: Comparator

111: Counter

VDD: supply voltage

PD: photosensitive element

TG: transfer transistor

FD: floating diffusion

RST: reset transistor

SF: source follower

RSL: Column Select Transistor

RSEL: column selection signal

C1: first capacitor

C2: second capacitor

PXO: image data

RDAC: ramp voltage

V _dummy : proposed voltage

IS: current source

M1: first transistor

M2: second transistor

M3: third transistor

M4: fourth transistor

SW1: first switching transistor

SW2: second switching transistor

V _dip : first endpoint

V _din : the second endpoint

T1, T2, T3, T4: points in time

detailed description

Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. However, inventive concepts may be embodied in many different forms and should not be construed as limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers indicate like elements throughout.

It should be understood that although the terms first, second, third etc. may be used herein to describe various elements or signals etc., these elements or signals should not be limited by these terms. These terms are used to distinguish one element from another element, or one signal from another signal. In addition, as used herein, the term "or" may include any one or all combinations of more of the associated listed items depending on the actual situation.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of an image capture device provided by an embodiment of the present invention. The image capture device 1 includes an image sensor 10 , an analog-to-digital converter array 11 and an image processing circuit 12 . The image sensor 10 is coupled to the ADC array 11 . The ADC array 11 is coupled to the image processing circuit 12 .

The image capture device 1 can be applied to electronic devices with imaging functions, including but not limited to digital cameras, digital camcorders, driving recorders, car navigation systems, Scanner, webcam, video phone and surveillance system.

The image sensor 10 is, for example, a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor and a charge-coupled device (CCD) image sensor. The image sensor 10 is used to capture an image data, and output the image data to the analog-to-digital converter array 11 . The detailed structure of the image sensor 10 will be introduced in detail in the following paragraphs.

The analog-to-digital converter array 11 includes appropriate logic, circuits and/or codes for converting the image data into digital image data, that is, converting the image data into a binary format. Then the ADC array 11 outputs the digitized image data to the image processing circuit 12 . The detailed structure of the ADC array 11 will be described in detail in the following paragraphs.

The image processing circuit 12 includes appropriate logic, circuits and/or codes for obtaining real images from the digitized image data, or performing image processing on the digitized image data. For example, the image processing circuit 12 can be used to perform pixel brightness compensation and integration processing on the digitized image data. The image processing circuit 12 has a pixel compensation mechanism, which properly compensates the digitized image data corresponding to each pixel according to the ambient brightness and the conversion gain of each pixel.

The structure and operation of the image sensor 10 and the ADC array 11 will be further introduced below. Please refer to FIG. 2 . FIG. 2 is a schematic diagram of an image sensor and an analog-to-digital converter array provided by an embodiment of the present invention. The image sensor 10 includes an image sensor array and a voltage supply array. The image sensing array includes a plurality of pixels and forms a pixel array. The voltage supply array includes a plurality of voltage supply circuits 101 . The ADC array 11 includes a plurality of comparators 110 , a plurality of counters 111 , a plurality of first capacitors C1 and a plurality of second capacitors C2 . The plurality of first capacitors C1 and the plurality of second capacitors C2 are respectively coupled to the inverting input terminal and the non-inverting input terminal of the plurality of comparators 110 . Output terminals of the plurality of comparators 110 are respectively coupled to the plurality of counters 111 . Output terminals of the plurality of counters 111 are respectively coupled to the image processing circuit 12 . For convenience of illustration, FIG. 2 only shows a comparator 110 , a counter 111 , a first capacitor C1 and a second capacitor C2 .

In this embodiment, the image sensor array is a Column Analog-to-Digital Converter (Column Analog-to-Digital Converter) structure. Therefore, pixels in the same row among the plurality of pixels are coupled to the same comparator 110 to form a plurality of row pixel matrices 100 , wherein the plurality of row pixel matrices 100 are arranged in parallel to form an image sensing array. In other words, the number of comparators 110 corresponds to the number of rows of the image sensor array. In addition, a voltage supply circuit 101 is coupled to a row of pixel matrix 100 and a comparator 110 , so the number of voltage supply circuits 101 also corresponds to the number of rows of the image sensor array. It should be noted that FIG. 2 also only shows one row of pixel matrix 100 and one voltage supply circuit 101 . However, this embodiment does not limit the number of pixels in the row pixel matrix 100 and the number of voltage supply circuits 101 . In other embodiments, one voltage supply circuit 101 may also be coupled to multiple row pixel matrices 100 and multiple comparators 110 .

The image sensor array is used to capture an image data PXO. The image sensing array can support one of a rolling shutter (Rolling Shutter) mechanism and a global shutter (Global Shutter) mechanism according to settings. When the image sensing array works under the rolling shutter mechanism, the plurality of pixels are exposed column by column to generate image data PXO, and then the image data PXO is provided to the analog-to-digital converter array 11 column by column. On the other hand, when the image sensor works under the global shutter mechanism, all the pixels are exposed simultaneously, and then the plurality of pixels provide the image data PXO to the ADC array 11 column by column.

It can be seen from FIG. 2 that the pixel in this embodiment has a 4T (four-transistor) structure. Each pixel includes a photosensitive element PD, a floating diffusion region FD, a source follower (source follower) SF, a column selection transistor RSL, a reset transistor RST, and a transfer transistor (transfer transistor) TG. One end of the photosensitive element PD is coupled to the transfer transistor TG, and the other end of the photosensitive element PD is grounded. The transfer transistor TG is coupled between the photosensitive element PD and the floating diffusion region FD. The gate of the source follower SF is coupled to the floating diffusion region FD, and the drain of the source follower SF is coupled to a power supply terminal to receive a supply voltage VDD. The drain of the column selection transistor RSL is coupled to the source of the source follower SF, and the source of the column selection transistor RSL is coupled to the comparator 110 . The reset transistor RST is coupled between the power supply terminal and the floating diffusion region FD. In addition, the gate of the transfer transistor TG, the gate of the reset transistor RST and the gate of the column select transistor RSL are respectively coupled to the driving circuit (not shown in FIG. 2 ).

The photosensitive element PD is used for sensing incident light and correspondingly generating charges. The photosensitive element PD can be, for example, a photodiode, a phototransistor, a photo-gate, a pinned photodiode (Pinned PhotoDiode), or a combination thereof, which can convert light into electric charge.

The floating diffusion area FD is composed of the parasitic capacitance between the photosensitive element PD and the source follower SF and/or an additional external capacitance. The floating diffusion FD is used to receive and store the charges generated by the photosensitive element PD.

The transfer transistor TG is used for selectively transferring the charge generated by the photosensitive element PD to the floating diffusion region FD. In detail, the transfer transistor TG is controlled by the transfer signal output from the driving circuit. When the driving circuit outputs a logic low level transfer signal to turn off the transfer transistor TG, the charge generated by the photosensitive element PD cannot be transferred to the floating diffusion region FD. When the driving circuit generates a logic high level transfer signal to turn on the transfer transistor TG, the transfer transistor TG transfers the charge generated by the photosensitive element PD to the floating diffusion region FD for accumulation and storage.

When the source follower SF is turned on, the gate voltage formed on the gate of the source follower SF by the charge output from the floating diffusion region FD corresponds to generate image data PXO. The column selection transistor RSL receives the image data PXO, and selectively outputs the image data PXO to the comparator 110 according to the column selection signal RSEL output from the driving circuit.

The reset transistor RST is used for selectively resetting the floating diffusion region FD with the supply voltage VDD output from the power supply terminal according to the reset signal output by the driving circuit. For example, when the reset signal is at a logic low level, the reset transistor RST will cut off the operation and pull down the voltage level of the cathode of the photosensitive element PD. At this time, the photosensitive element PD will sense incident light and correspondingly generate charges stored in floating diffusion FD. And when the reset signal is logic high level, the reset transistor RST will be turned on so that the voltage level of the cathode of the photosensitive element PD is reset to the initial potential (that is, the supply voltage VDD), thereby releasing and clearing the remaining floating The charge in the diffusion area FD, that is, resets the floating diffusion area FD.

It is worth mentioning that, in this embodiment, the plurality of pixels have a 4T structure. However, the present invention is not limited thereto. In other embodiments, the plurality of pixels can also be a 3T (three-transistor) structure or a 5T (five-transistor) structure. If the plurality of pixels have a 3T structure, the plurality of pixels do not include a transfer transistor TG. If the plurality of pixels have a 5T structure, the plurality of pixels further include a photosensitive element PD, a floating diffusion region FD, a source follower SF, a column selection transistor RSL, a reset transistor RST, and a transfer transistor TG. Global shutter transistor (globalshutter transistor). The operation principles of the 3T-structured pixels and the 5T-structured pixels are commonly used in the field of image processing by those with ordinary knowledge in the technical field, so details will not be repeated here.

The voltage supply circuit 101 includes appropriate logic, circuitry and/or code to provide a dummy voltage V _dummy to the comparator 110 . The proposed voltage V _dummy is a stable fixed voltage. The comparator 110 performs an auto-calibration (Auto Zero) function according to the preset voltage V _dummy , so as to solve the mismatch problem of the plurality of transistors of the comparator 110 due to process differences.

In this embodiment, the voltage supply circuit 101 is a kind of light-shielding pixel. For example, the structure of the light-shielding pixel is the same as that of the aforementioned pixel, such as a pixel with a 4T structure. Different from the aforementioned pixels, the photosensitive element PD of the light-shielding pixel is shielded and will not be affected by incident light. Therefore, the voltage of the floating diffusion FD of the light-shielding pixel is stabilized. Then, the shading pixel provides a stable preset voltage _Vdummy to the comparator 110 according to the floating diffusion region FD, and the comparator 110 performs an automatic correction function.

This embodiment does not limit the structure of the voltage supply circuit 101 . In other embodiments, the voltage supply circuit 101 may be a shading pixel with a 3T structure, a light-shielding pixel with a 5T structure, or other circuits that can provide a fixed voltage. However, for the convenience of manufacture, the structure of the voltage supply circuit 101 is designed to be the same as that of the pixels of the image sensor array.

The structure of the comparator 110 will be further introduced below. Referring to FIG. 2 , please refer to FIG. 3 . FIG. 3 is a schematic diagram of a comparator provided by an embodiment of the present invention. The comparator 110 includes a first transistor M1 , a second transistor M2 , a third transistor M3 , a fourth transistor M4 , a first switch transistor SW1 , a second switch transistor SW2 and a current source IS. In this embodiment, the first transistor M1 and the second transistor M2 are N-type MOSFETs, and the third transistor M3 and the fourth transistor M4 are P-type MOSFETs.

The source of the first transistor M1 is coupled to the current source IS, and the drain of the first transistor M1 is coupled to the third transistor M3. The source of the second transistor M2 is coupled to the current source IS, and the drain of the second transistor M2 is coupled to the fourth transistor M4. The current source IS is used to control the amount of current flowing through the first transistor M1 and the second transistor M2. The gate of the first transistor M1 is coupled to the first capacitor C1. The gate of the second transistor M2 is coupled to the second capacitor C2. The gate of the fourth transistor M4 is coupled to the drain of the fourth transistor M4 , and the drain of the fourth transistor M4 is also coupled to the counter 111 .

In addition, the first switch transistor SW1 is electrically connected between the drain and the gate of the first transistor M1. The second switch transistor SW2 is electrically connected between the drain and the gate of the second transistor M2. In this embodiment, the first switch transistor SW1 and the second switch transistor SW2 are P-type MOSFETs. However, the present invention is not limited thereto. In other embodiments, the first switch transistor SW1 and the second switch transistor SW2 may also be N-type MOSFETs. Those skilled in the art can change the types of the first switch transistor SW1 and the second switch transistor SW2 according to the magnitude of the voltage that the comparator 110 withstands.

The comparator 110 receives the ramp voltage RDAC through the gate of the first transistor M1, and receives the image data PXO provided by the row pixel matrix 100 through the gate of the second transistor M2. The comparator 110 then outputs a comparison result to the counter 111 according to the ramp voltage RDAC and the image data PXO.

It should be noted that the structure of the above-mentioned comparator 110 is only for illustration and is not intended to limit the present invention. In other embodiments, the comparator 110 may also have a different structure.

The following will describe the rolling shutter mechanism and the global shutter mechanism according to the structure of the comparator 110 in FIG. 3 . Please refer to FIG. 4 . FIG. 4 is an operation waveform diagram of a traditional comparator in a rolling shutter mechanism and a global shutter mechanism. The ramp voltage RDAC has a fixed waveform. The comparator 110 is designed to support a rolling shutter mechanism or a global shutter mechanism according to settings. It should be noted that in this embodiment, the image sensor 10 does not include a voltage supply array, or the voltage supply circuit 101 of the voltage supply array does not provide the intended voltage V _dummy to the comparator 110 .

First, the description of the image sensor array operating on the rolling shutter mechanism is as follows. Pixels in the image sensing array of the image sensor 10 are exposed column by column. At the time point T1, the comparator 110 performs an automatic calibration function. After the pixels in the first row of the image sensing array are exposed, the transfer transistors TG of the plurality of pixels are not yet turned on, so the floating diffusion region FD does not receive any charge. In other words, the image data PXO output by the pixels at this time is the reference voltage. The column selection transistor RSL of the pixel receives the column selection signal RSEL of logic high level, so that the pixel starts to provide the image data PXO of logic high level to the corresponding comparator 110 . The first switch transistor SW1 and the second switch transistor SW2 of the comparator 110 are in a turn-on state. Therefore, the comparator 110 corrects and records the offset voltage V _offset between the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, and stores the offset voltage V _offset in the first capacitor C1 and the first capacitor C1. In the second capacitor C2, to complete the automatic correction function. In other words, the time point T1 to the time point T2 is the automatic calibration period of the comparator 110 .

It is worth mentioning that the potential of the first terminal V _dip of the comparator 110 is the difference between the supply voltage VDD and the operating voltage V _{th_p} of the third transistor M3 , ie (VDD−V _{th_p} ). The potential of the second terminal V _din of the comparator 110 is the difference between the supply voltage VDD and the operating voltage V _{th_p} of the fourth transistor M4 , ie (VDD−V _{th_p} ).

At time point T2, the comparator 110 enters a first comparison period. Since the offset voltage V _offset has been stored in the first capacitor C1, the potential of the first terminal V _dip will become (VDD-V _{th_p} +V _offset ). Then, the potential of the first terminal V _dip starts to drop as the ramp voltage RDAC decreases. The counter 111 starts to operate to count the time it takes for the potential of the first terminal V _dip to drop below the potential of the second terminal V _din .

At this moment, the transfer transistor TG is not turned on to transfer the charge to the floating diffusion region FD, so the image data PXO is a reference voltage of logic high level. Therefore, the potential of the second terminal V _din will remain at (VDD-V _{th_p} ). The counter 111 stops counting until the potential of the first terminal V _dip is lower than the potential of the second terminal V _din , and outputs the internal count value to the image processing circuit 12 . That is to say, the count value obtained by the counter 111 during the first comparison period corresponds to the magnitude of the offset voltage V _offset . The image processing circuit 12 converts the count value into the gray scale of the image. In other words, the image capture device 1 converts the voltage represented by the image into a concept of time through the counter 111 . The image processing circuit 12 then converts the time into the concept of grayscale.

Specifically, the ramp signal RDAC is a step signal. The count value of the counter 111 corresponds to each step of the ramp signal RDAC. For example: a count value of 1 corresponds to the first stage of the step signal, a count value of 2 corresponds to the second stage of the step signal, and so on. In addition, the count value can correspond to one of the grayscale values (0˜255). Accordingly, the image processing circuit 12 can directly determine the binary gray scale value of the image according to the count value output by the counter 111 .

Incidentally, the first switch transistor SW1 and the second switch transistor SW2 are turned off after the comparator enters the comparison mode (ie, the first comparison period or the second comparison period).

At time point T3, the comparator 110 enters a second comparison period. The ramp voltage RDAC returns to the original logic level, that is, the potential of the first terminal V _dip returns to (VDD-V _{th_p} +V _offset ). Then the ramp voltage RDAC starts to drop, so that the potential of the first terminal V _dip changes again. The counter 111 resets the internal count value and restarts counting. At this time, the transfer transistors TG of the pixels in the first column of the image sensing array are turned on, so that the images captured by the pixels are transferred to the floating diffusion region FD. Next, each of the plurality of pixels outputs image data PXO of a logic low level. The image data PXO is coupled into the second terminal V _din , so that the potential of the second terminal V _din becomes (VDD−V _{th_p} −|ΔV|). ΔV represents the real image.

Similarly, the counter 111 counts the time it takes for the potential of the first terminal V _dip to drop below the potential of the second terminal V _din , and outputs the counted value to the image processing circuit 12 . The count value obtained by the counter 111 during the second comparison period corresponds to the sum of the offset voltage V _offset and the absolute value of the real image, ie (V _offset + |ΔV|).

Incidentally, in order to ensure the normal operation of the comparator 110 , the potential of the current source IS is designed to be lower than the potential of the second terminal V _din . Because the potential of the second terminal V _din is lower than the potential of the current source IS, the current source IS cannot normally provide current to the components in the comparator 110 .

At time point T4, the comparator 110 ends the second comparison period. The column selection signal RSEL becomes a logic low level, so that the column selection transistor RSL is turned off. The image processing circuit 12 subtracts the grayscale value corresponding to the count value obtained during the first comparison period and the second comparison period to obtain the grayscale value of the real image |ΔV|.

On the other hand, the description of the comparator 110 operating in the global shutter mechanism is as follows. All pixels in the image sensing array of the image sensor 10 are exposed simultaneously, and then the image sensing array provides image data PXO to the corresponding comparator 110 column by column. It is worth mentioning that, in order to support the rolling shutter mechanism, the bias voltage of the transistor in the comparator 110 is set at a relatively high level.

At the time point T1, the comparator 110 performs an automatic calibration function. Since the plurality of pixels have already captured images, the comparator 110 receives the image data PXO of logic low level at this time. The comparator 110 corrects and records the offset voltage V _offset between the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, and stores the offset voltage V _offset in the first capacitor C1 and the second capacitor C1. Capacitor C2 to complete the automatic calibration function.

It is worth mentioning that the potential of the first terminal V _dip of the comparator 110 is the difference between the supply voltage VDD and the operating voltage V _{th_p} of the third transistor M3 , ie (VDD−V _{th_p} ). The potential of the second terminal V _din of the comparator 110 is also the difference between the supply voltage VDD and the operating voltage V _{th_p} of the fourth transistor M4 , ie (VDD−V _{th_p} ).

At time point T2, the comparator 110 enters a first comparison period. The potential of the first terminal V _dip is (VDD-V _{th_p} +V _offset ), and the potential of the first terminal V _dip starts to drop as the ramp voltage RDAC decreases. The counter 111 starts to operate to count the time it takes for the potential of the first terminal V _dip to drop below the potential of the second terminal V _din . At this time, the plurality of pixels have been exposed, so the image data PXO is still maintained at a logic low level. In other words, the potential of the second terminal V _din will remain at (VDD-V _{th_p} ), which is lower than the potential of the first terminal V _dip .

At time point T3, the comparator 110 enters a second comparison period. At this time, the reset transistor RST of the pixel is turned on, so that the floating diffusion FD is reset. In other words, what the comparator 110 receives is the image data PXO of logic high level, that is, the reference voltage. The voltage corresponding to the real image ΔV will also be coupled into the second terminal V _din , so that the potential of the second terminal V _din becomes (VDD−V _{th_p} +|ΔV|). That is to say, when the comparator 110 operates in the rolling shutter mechanism and the global shutter mechanism, the second terminal V _din will have several different bias voltages, which makes the design of the comparator 110 difficult.

On the other hand, the second capacitor C2 of the ADC array 11 has stored the offset voltage V _offset . At this time, when the image data PXO of logic high level is received again, the second switch transistor SW2 will be turned on by false touch, so that the charge stored in the second capacitor C2 will be lost. That is to say, the comparator 110 cannot complete automatic calibration.

In addition, the working range of the comparator 110 will also be destroyed due to receiving the image data PXO of logic high level. For example, the working range of the comparator 110 is 0-3.3V, wherein each element in the comparator 110 consumes a working voltage. The current source IS also consumes an operating voltage (for example, 0.5V), and the potential of the second terminal V _din cannot be lower than the operating voltage of the current source IS. Assuming that the bias voltage in the comparator 110 is kept at 2.8V, and a logic high level image data PXO (for example, 0.6V) comes in at this time, the voltage borne by the comparator 110 will exceed the working range, causing the components to fail to work normally. operate.

In order to solve the above problems, the working range of the comparator 110 can be increased. However, if the working range of the comparator 110 is made too large, the manufacturing cost of the comparator 110 will increase, and the high potential working range is rarely used.

Therefore, the embodiments of the present invention adopt different methods to solve the above problems, so that the image sensor array and the comparator 110 can support the rolling shutter mechanism or the global shutter mechanism. Please refer to FIG. 5 . FIG. 5 is an operation waveform diagram of the comparator provided by the embodiment of the present invention. The difference from the embodiment in FIG. 4 is that the image sensor 10 also provides the dummy voltage V _dummy to the comparator 110 through the voltage supply array.

In the following, the operation of the image sensor array under the global shutter mechanism will be described first. At the time point T1, the comparator 110 enters the auto-calibration period to perform the auto-calibration function. All the pixels in the image sensor array of the image sensor 10 are exposed simultaneously. At this time, the column selection signal RSEL maintains a logic low level, so that the column selection transistor RSL is turned off, and the image data PXO captured by the plurality of pixels is not input into the comparator 110 .

Instead, the voltage supply circuit 101 of the voltage supply array starts to provide the dummy voltage V _dummy of logic high level to the corresponding comparator 110 . The comparator 110 completes the auto-calibration function according to the preset voltage _Vdummy of logic high level, and stores the offset voltage in the first capacitor C1 and the second capacitor C2. At this time, the potentials of the first terminal V _dip and the second terminal V _din of the comparator 110 are also (VDD-V _{th_p} ).

At time point T2, the comparator 110 enters the comparison mode. The voltage supply array stops supplying the preset voltage V _dummy . The potential of the first terminal V _dip is (VDD-V _{th_p} +V _offset ), and the potential of the first terminal V _dip begins to decrease as the ramp voltage RDAC decreases. In addition, the column selection signal RSEL transitions to a logic high level to turn on the column selection transistor RSL. The plurality of pixels start to input the captured image data PXO into the comparator 110 . At this time, the voltage corresponding to the real image ΔV is coupled into the second terminal V _din , so that the potential of the second terminal V _din becomes (VDD-V _{th_p} -|ΔV|). At this time, the potential of the second terminal V _din is equivalent to the potential of the second terminal V _din during the second comparison period of the rolling shutter mechanism.

The comparator 110 compares the potential of the first terminal V _dip with the potential of the second terminal V _din , and outputs a first comparison result to the counter 111 . The counter 111 then calculates the time it takes for the potential of the first terminal V _dip to drop below the potential of the second terminal V _din according to the first comparison result, and outputs the corresponding count value to the image processing circuit 12 . The count value obtained by the counter 111 corresponds to the sum of the offset voltage V _offset and the absolute value of the real image, ie (V _offset + |ΔV|).

At time point T3, the comparator 110 enters a second comparison period. The potential of the first terminal V _dip will return to (VDD-V _{th_p} +V _offset ). At this time, the reset transistor RST of the pixel is turned on, so that the floating diffusion FD is reset. In other words, what the comparator 110 receives is the image data PXO of logic high level, that is, the reference voltage. The potential of the second terminal V _din will return to (VDD-V _{th_p} ), which is equivalent to the potential of the second terminal V _din during the first comparison period of the rolling shutter mechanism. It can be seen that the comparator 110 has the same bias voltage under the rolling shutter mechanism and the global shutter mechanism. Therefore, the image capture device 1 can use the same set of analog-to-digital converter array 11 and image processing circuit 12 to process the image data PXO generated when the image sensor 10 operates in the rolling shutter mechanism and the global shutter mechanism.

The comparator 110 compares the potential of the first terminal V _dip with the potential of the second terminal V _din , and outputs a second comparison result to the counter 111 . The counter 111 also calculates the time it takes for the potential of the first terminal V _dip to drop below the potential of the second terminal V _din according to the second comparison result, and outputs the corresponding count value to the image processing circuit 12 . At this time, the count value obtained by the counter 111 corresponds to the magnitude of the offset voltage V _offset .

At time point T4, the comparator 110 ends the second comparison period. The column selection signal RSEL becomes a logic low level, so that the column selection transistor RSL is turned off. The image processing circuit 12 subtracts the gray scale value corresponding to the count value obtained during the first comparison period and the count value obtained during the second comparison period to obtain the real gray scale value of the image |ΔV|.

In this way, when the image sensor array operates under the global shutter mechanism, the comparator 110 can still operate normally, so that the image processing circuit 12 can obtain the real image |ΔV| from the image data PXO provided by the image sensor array.

Incidentally, when the image sensor array operates under the rolling shutter mechanism, the voltage supply circuit 101 can also provide the corresponding comparator 110 with a logic high level preset voltage V _dummy for the comparator 110 to complete automatic calibration. However, the present invention is not limited thereto. The reason is that when the image sensor array operates under the rolling shutter mechanism, the corresponding transfer transistor TG will be turned on after the comparator 110 completes the automatic calibration of the plurality of pixels, so that the charge is transferred to the floating diffusion region FD. During the automatic calibration, the plurality of pixels also provide logic high level voltages to the comparator 110 for automatic calibration. Therefore, the voltage supply circuit 101 may not provide the intended voltage V _dummy to the comparator 110 when the image sensing array operates under the rolling shutter mechanism.

To sum up, the image sensor provided by the embodiment of the present invention and the image capture device using it provide a stable preset voltage to the comparator of the analog-to-digital converter array through the voltage supply array, so that the image capture The device uses the same analog-to-digital converter array and image processing circuit to realize the rolling shutter mechanism and the global shutter mechanism, and generate corresponding images. Compared with the traditional image capture device, the circuit design of the image sensor and the image capture device using the image sensor provided by the embodiment of the present invention is more simplified, easy to manufacture and low in manufacturing cost.

In addition, the image sensor and the image capture device using the image sensor provided by the embodiments of the present invention also use the counters of the analog-to-digital converter array to convert the image data captured by the image sensor into binary form. Since the image processing circuit also operates in binary, the image processing circuit does not need to spend time converting the format of the image data.

The above description is only the best specific embodiment of the present invention, and the features of the present invention are not limited thereto. Any changes or modifications that can be easily conceived by those skilled in the art within the scope of the present invention can be covered. In the following patent scope of this case.

Claims (20)

1. An image sensor coupled to an analog-to-digital converter array, wherein the analog-to-digital converter array includes a plurality of comparators, wherein the image sensor includes: An image sensing array, used to capture an image data, the image sensing array includes a plurality of pixels, wherein the image sensing array supports one of a rolling shutter mechanism and a global shutter mechanism according to settings; A voltage supply array, coupled to the analog-to-digital converter array, includes a plurality of voltage supply circuits for providing a desired voltage; Wherein, during an auto-calibration period, the voltage supply array provides the intended voltage to the analog-to-digital converter array, and the plurality of comparators perform an auto-calibration function according to the intended voltage; during the plurality of comparators After completing the automatic calibration function, the image sensor array outputs the image data to the ADC array, and then the ADC array converts the image data into digital image data. 2. The image sensor according to claim 1, wherein the analog-to-digital converter array further comprises: a plurality of counters, the plurality of counters are respectively coupled to the output terminals of the plurality of comparators, and the count values of the plurality of counters increase with time; Wherein the output terminals of the plurality of counters are coupled to an image processing circuit, and the image processing circuit judges the grayscale value of the digitized image data according to the count values output by the plurality of counters. 3. The image sensor according to claim 2, wherein after the automatic calibration function is completed, each of the plurality of comparators enters a comparison mode; during a first comparison period, the image sensing array providing a part of the image data to the analog-to-digital converter array column by column, and then each of the plurality of comparators compares the image data with a ramp voltage, and outputs a first comparison result to a corresponding counter, the A plurality of counters adjust the plurality of counting values according to the plurality of first comparison results; when the first comparison result indicates that the ramp voltage is lower than the image data, the plurality of counters stop counting and output the current The count value is sent to the image processing circuit. 4. The image sensor according to claim 3, wherein during a second comparison period, the image sensor array resets the floating diffusion region of each pixel and provides a reference voltage to the analog digital column by column. converter array, and each of the plurality of comparators compares the reference voltage with the ramp voltage, and outputs a second comparison result to a corresponding counter; when the second comparison result indicates that the ramp voltage is lower than the The plurality of counters stop counting according to the reference voltage, and output the current counting value to the image processing circuit. 5. The image sensor according to claim 4, wherein the image processing circuit calculates the image data according to count values provided by the plurality of counters during the first comparison period and the second comparison period The gray scale value of the image data and the gray scale value of the reference voltage, and then the image processing circuit subtracts the gray scale value of the image data from the gray scale value of the reference voltage to obtain the real gray scale value of the image. 6. The image sensor according to claim 1, wherein the number of the plurality of comparators corresponds to the number of rows of the image sensing array, and the plurality of comparators of the same row in the image sensing array pixels are coupled to the same comparator. 7. The image sensor as claimed in claim 1, wherein the image sensor array is a CMOS image sensor array. 8. The image sensor according to claim 1, wherein the plurality of pixels are respectively a 3T structure, a 4T structure or a 5T structure. 9. The image sensor according to claim 1, wherein the voltage supply circuit comprises: a plurality of light-shielding pixels, respectively coupled to the plurality of comparators, for providing the preset voltage to the plurality of comparators; Wherein, the photosensitive elements of the plurality of light-shielding pixels are shaded, so that the voltages of the floating diffusion regions of the plurality of light-shielding pixels are stable, and then the plurality of light-shielding pixels provide a stable voltage according to the proposed floating diffusion region. Voltage. 10. The image sensor according to claim 9, wherein the plurality of light-shielding pixels are respectively a 3T structure, a 4T structure or a 5T structure. 11. An image capturing device, comprising: an array of analog-to-digital converters, including a plurality of comparators; An image sensor, coupled to the analog-to-digital converter array, includes: An image sensing array, used to capture an image data, the image sensing array includes a plurality of pixels, wherein the image sensing array supports one of a rolling shutter mechanism and a global shutter mechanism according to settings; A voltage supply array, coupled to the analog-to-digital converter array, includes a plurality of voltage supply circuits for providing a desired voltage; Wherein, during an auto-calibration period, the voltage supply array provides the intended voltage to the analog-to-digital converter array, and the plurality of comparators perform an auto-calibration function according to the intended voltage; during the plurality of comparators After completing the automatic calibration function, the image sensor array outputs the image data to the ADC array, and then the ADC array converts the image data into digital image data. 12. The image capture device according to claim 11, wherein the analog-to-digital converter array further comprises: a plurality of counters, the plurality of counters are respectively coupled to the output terminals of the plurality of comparators, and the count values of the plurality of counters increase with time; The output terminals of the plurality of counters are coupled to an image processing circuit of the image capture device, and the image processing circuit judges the gray scale value of the digitized image data according to the count values output by the plurality of counters. 13. The image capture device according to claim 12, wherein after the automatic calibration function is completed, each of the plurality of comparators enters a comparison mode; during a first comparison period, the image sensing array providing a part of the image data to the analog-to-digital converter array column by column, and then each of the plurality of comparators compares the image data with a ramp voltage, and outputs a first comparison result to a corresponding counter, the A plurality of counters adjust the plurality of counting values according to the plurality of first comparison results; when the first comparison result indicates that the ramp voltage is lower than the image data, the plurality of counters stop counting and output the current The count value is sent to the image processing circuit. 14. The image capture device according to claim 13, wherein during a second comparison period, the image sensor array resets the floating diffusion region of each pixel, and provides a reference voltage to the analog digital column by column. converter array, and each of the plurality of comparators compares the reference voltage with the ramp voltage, and outputs a second comparison result to a corresponding counter; when the second comparison result indicates that the ramp voltage is lower than the The plurality of counters stop counting according to the reference voltage, and output the current counting value to the image processing circuit. 15. The image capture device according to claim 14, wherein the image processing circuit calculates the image data according to the count values provided by the plurality of counters during the first comparison period and the second comparison period The gray scale value of the image data and the gray scale value of the reference voltage, and then the image processing circuit subtracts the gray scale value of the image data from the gray scale value of the reference voltage to obtain the real gray scale value of the image. 16. The image capture device according to claim 11, wherein the number of the plurality of comparators corresponds to the number of rows of the image sensing array, and the plurality of comparators of the same row in the image sensing array pixels are coupled to the same comparator. 17. The image capture device as claimed in claim 11, wherein the image sensor array is a CMOS image sensor array. 18. The image capture device according to claim 11, wherein the plurality of pixels are respectively a 3T structure, a 4T structure or a 5T structure. 19. The image capture device according to claim 11, wherein the voltage supply circuit comprises: a plurality of light-shielding pixels, respectively coupled to the plurality of comparators, for providing the preset voltage to the plurality of comparators; Wherein, the photosensitive elements of the plurality of light-shielding pixels are shaded, so that the voltages of the floating diffusion regions of the plurality of light-shielding pixels are stable, and then the plurality of light-shielding pixels provide a stable voltage according to the proposed floating diffusion region. Voltage. 20. The image capture device according to claim 19, wherein the plurality of light-shielding pixels are respectively a 3T structure, a 4T structure or a 5T structure.