CN108398590A - A kind of voltage peak detection circuit of numeral output - Google Patents

Abstract

The invention discloses a kind of voltage peak detection circuits of numeral output, the circuit realizes that the voltage peak of numeral output detects using what voltage follower, zero passage voltage comparator, A/D converter, register, binary numeral comparator and three inputs one exported with circuits such as doors, it avoids in traditional scheme and first obtains peak value with the voltage peak detection circuit of simulation, then the voltage peak of simulation is obtained into numeral output by A/D conversion circuits.Compared with prior art, the circuit is simple and reliable, it is suitble to low-and high-frequency measured signal voltage peak to the conversion of number, fast response time, measures conversion precision is high, and peak detection voltage dynamic range is big, and minimum can survey the voltage of μ V magnitudes, and number is facultative small suitable for the main logics circuits such as TTL, COMS, dynamic power loss by force.

Description

A digital output voltage peak detection circuit

technical field

The invention relates to an electronic circuit structure, in particular to a digital output voltage peak detection circuit.

Background technique

Peak detectors are widely used in nuclear radiation detection, geology, automatic gain control, oscillators, and feedback protection systems for RF power amplifiers. Peak detectors have analog output and digital output peak detectors, and track weak signals in noise or interference environments, which requires peak detectors to have high detection accuracy, strong anti-interference ability, and easy control and signal processing. Analog output Due to the limitations of the principle and structure, the peak detectors in the field can no longer meet the design requirements, and the peak detectors with digital output are generally used. Due to the current digital output peak detection circuit adopts the principle of analog peak detection first and then digital conversion, there are problems such as low peak detection accuracy, low sampling frequency, poor anti-interference ability, nonlinear capacitance integration, signal distortion, and system debugging. Difficulties and other defects.

The digital output voltage signal peak value measurement circuit is the core circuit of signal data acquisition in the basic electricity test instrument. Traditionally, the voltage signal peak value to digital conversion is mainly to obtain the voltage peak value by using the analog voltage peak value detection circuit, and then pass the voltage peak value through the A/ The D conversion circuit obtains a digital output. There are mainly two types of analog voltage peak detection circuits, one is a voltage-type peak measurement circuit, and the other is a transconductance-type peak measurement circuit. The principle of the voltage-type peak measurement circuit is simple, but the integral nonlinearity is large, the passband is small, and the dynamic range is also small (the response to small-amplitude signals is poor, and the signal is generally required to be greater than 200mV), and the effect of processing fast signals is not satisfactory. . Although the performance of the peak measurement circuit of the transconductance type is better than that of the voltage type, there are also difficulties in circuit design. Due to the use of a transconductance amplifier, there is an integral factor in the loop gain that is related to the capacitance C. In order to improve the linear performance of the circuit, the capacitance C needs to be as large as possible, and increasing the capacitance C will reduce the passband and slew rate of the circuit. In this way, the voltage peak value detected by the two circuits has a hysteresis. When the peak value changes from low level to high level, the subsequent circuit detects this level change and considers the peak value to arrive, and at the same time starts to perform A/C on the peak value output by the peak detection circuit D conversion brings obvious conversion errors. The reliability of the circuit not only depends on the stability of the integrating circuit, but also depends on the waveform of the detected signal. For some slowly changing signals, it is easy to cause false triggers and seriously affect the measurement results.

Contents of the invention

The purpose of the present invention is to provide a voltage peak detection circuit for digital output, and the purpose is to overcome the small signal analog voltage peak value to digital conversion accuracy, low conversion speed, and anti-interference ability that mainly exist in the existing digital output voltage peak detection circuit. Poor, and capacitance integral nonlinearity causes signal distortion, and system debugging is difficult and other defects.

The solution of the present invention to solve its technical problems is: a digital output voltage peak detection circuit, including: a voltage follower, an A/D converter, a register, a zero-crossing voltage comparator, a binary value comparator, three inputs and one output The AND gate of the voltage follower, the non-inverting input terminal of the voltage follower is connected with the signal under test, the output terminal of the voltage follower is connected with its own inverting input terminal, the analog signal input terminal of the A/D converter, the The non-inverting input terminal of the zero-crossing voltage comparator is connected, and the N-bit binary digital signal output terminal of the A/D converter is connected with the N-bit binary digital input terminal of the register and the binary value comparator according to the high and low order of the binary weight position. An N-bit binary digital comparison input terminal of the register is connected in parallel, and the N-bit binary digital output terminal of the register is connected in parallel with another N-bit binary digital comparison input terminal of the binary value comparator according to the order of the binary weight position, and the system works The clock is connected to the clock terminal of the A/D converter and the first input terminal of the AND gate, the output terminal of the zero-crossing voltage comparator is connected to the second input terminal of the AND gate, and the zero-crossing voltage comparator The inverting input terminal of the device is connected to the ground, the output terminal of the binary value comparator is connected to the third input terminal of the AND gate, the output terminal of the AND gate is connected to the control terminal of the register, and the binary The numerical comparator is used to compare the value of the N-bit binary number output by the digital signal output terminal of the A/D converter when a working pulse arrives and the value of the N-bit binary number stored in the register during the last working pulse, When the zero-crossing voltage comparator outputs a high level, when the value output by the digital signal output terminal of the A/D converter is greater than the value currently registered in the register, the output terminal of the binary value comparator outputs a high level Level, when a working pulse arrives, the output terminal of the AND gate outputs a high level, and the register is controlled by the high level output of the AND gate to store the digital signal of the A/D converter when a working pulse arrives The N-bit binary number output by the output terminal, when the value output by the digital signal output terminal of the A/D converter is less than or equal to the value registered in the current register, the output terminal of the binary value comparator outputs a low level , the output terminal of the AND gate outputs a low level, and the register is controlled by the low level output of the AND gate to keep the data registered during the last working pulse unchanged, and the binary value comparator is continuously performed under the action of the system working clock For comparison, the register registers and outputs the value of the maximum N-bit binary digit of the measured signal before the arrival of the next working pulse, that is, the output of the register tracks the peak value of the measured signal, and when the zero-crossing voltage comparator outputs a low level, the output terminal of the AND gate outputs a low level, and the register is controlled by the low level output of the AND gate to keep the registered data unchanged, that is, the voltage peak detection circuit of the digital output only tracks the measured value greater than or equal to zero. signal, the gain of the voltage follower is 1, which is used to isolate the measured signal.

The beneficial effect of the present invention is: this circuit adopts voltage follower, zero-crossing voltage comparator, A/D converter, register, binary value comparator and three-input-one-output AND gate and other circuits to realize the voltage peak detection of digital output, It avoids using the analog voltage peak detection circuit to obtain the peak value in the traditional scheme, and then obtains the digital output through the analog voltage peak value through the A/D conversion circuit. Compared with the existing technology, the circuit is simple and reliable, suitable for the conversion of high and low frequency measured signal voltage peak value to digital, with fast response speed, high measurement conversion accuracy, large dynamic range of peak detection voltage, and the minimum measurable voltage of μV level , Strong digital compatibility, suitable for main logic circuits such as TTL, COMS, etc., with low dynamic energy loss.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly describe the drawings that need to be used in the description of the embodiments. Apparently, the described drawings are only some embodiments of the present invention, not all embodiments, and those skilled in the art can obtain other designs and drawings based on these drawings without creative work.

Fig. 1 is a schematic circuit diagram of the voltage peak detection circuit of the present invention.

Detailed ways

The idea, specific structure and technical effects of the present invention will be clearly and completely described below in conjunction with the embodiments and accompanying drawings, so as to fully understand the purpose, features and effects of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without creative efforts belong to The protection scope of the present invention. In addition, all connection relationships mentioned in the text do not simply refer to the direct connection of components, but mean that a more optimal circuit structure can be formed by adding or reducing connection components according to specific implementation conditions. The various technical features in the invention can be combined interactively on the premise of not conflicting with each other.

Embodiment 1, with reference to Fig. 1, a kind of voltage peak detection circuit of digital output, comprises: the voltage follower that operational amplifier _A1 forms, A/D converter, register, the zero-crossing voltage comparator that is formed by voltage comparator A2 a2, a binary value comparator, an AND gate with three inputs and one output, the non-inverting input terminal of the voltage follower a1 is connected to the measured signal U _i , the output terminal of the voltage follower a1 is connected to its own inverting input terminal, The analog signal input terminal IN ₊ of the A/D converter, the non-inverting input terminal of the zero-crossing voltage comparator a2, the N-bit binary digital signal output terminal D _OUT of the A/D converter according to the level of the binary weight The sequence is connected in parallel with an N-bit binary digital input terminal D of the register and an N-bit binary digital comparison input terminal A of the binary value comparator, and the N-bit binary digital output terminal Q of the register is in the order of binary weight positions It is connected in parallel with another N-bit binary digital comparison input terminal B of the binary value comparator, and the system working clock is connected with the clock terminal CLK of the A/D converter and the first input terminal X of the AND gate. The output terminal of the zero-voltage comparator a2 is connected to the second input terminal Y of the AND gate, the inverting input terminal of the zero-crossing voltage comparator a2 is connected to the ground, and the output terminal A>B of the binary value comparator It is connected with the third input terminal Z of the AND gate, the output terminal W of the AND gate is connected with the control terminal CP of the register, and the binary value comparator is used to compare the A/D conversion when a working pulse arrives. The value of the N-bit binary number output by the digital signal output terminal D _OUT of the device and the value of the N-bit binary number stored in the register during the last working pulse, when the zero-crossing voltage comparator a2 outputs a high level, When the value output by the digital signal output terminal D _OUT of the A/D converter is greater than the value stored in the current register, the output terminal A>B of the binary value comparator outputs a high level, and when a working pulse arrives When the AND gate output terminal W outputs a high level, the register is controlled by the high level output of the AND gate to store the N output of the A/D converter digital signal output terminal D _OUT when a working pulse arrives. When the value output by the digital signal output terminal D _OUT of the A/D converter is less than or equal to the value stored in the current register, the binary value comparator output terminal A>B outputs a low level , the AND gate output terminal W outputs a low level, and the register is controlled by the low level control register output by the AND gate to keep the data registered during the last working pulse unchanged, and the binary value comparator is under the action of the system working clock The comparison is performed continuously, and what the register registers and outputs is the value O _OUT of the largest N-bit binary digit of the signal under test before the arrival of the next working pulse, that is, the output of the register tracks the peak value of the signal under test. When the zero-crossing voltage comparator a2 outputs a low level, the AND gate output terminal W outputs a low level, and the register is controlled by the low level output of the AND gate to keep the registered data unchanged, that is, the digital output The voltage peak detection circuit only tracks the measured signal Ui greater than or equal to zero. In addition, the gain of the voltage follower a1 is 1, which isolates the measured signal Ui and improves the conversion accuracy of the circuit.

The principle of the present invention is further described: in the initial state, the voltage peak detection circuit of the digital output works under the action of the system working clock. When there is no working pulse, that is, before the detection circuit starts to work, the register is reset through the register reset terminal R Reset control. At this time, the register stores the N-bit binary number 0. Since the working pulse state is low level "0", this signal is added to the input terminal X of the AND gate, so the output terminal W of the AND gate outputs a low power level. Level "0", this low level "0" is added to the control terminal CP of the register, at this time the register is locked, the register keeps storing N-bit binary numbers 0, and the output terminal Q of the register outputs N-bit binary numbers 0.

In the working state, when the measured signal U _i =0V, the output terminal of the voltage follower a1 is added to the analog signal input terminal IN ₊ of the A/D converter, because the system working clock is connected to the clock of the A/D converter On the terminal CLK, under the action of the working pulse of the system working clock, the digital signal output terminal D _OUT of the A/D converter outputs N-bit binary digital 0 in parallel at this time, and the N-bit binary digital 0 is parallel in the order of binary weight output to the N-bit binary digital input terminal D of the register and an N-bit binary digital comparison input terminal A of the binary value comparator. At this time, the output terminal Q of the register outputs N-bit binary numbers in parallel to the other N of the binary value comparator. 1-bit binary digital comparison input terminal B, since the initial state of the register is N-bit binary digital 0, that is, the comparison input terminal B added to the binary value comparator is N-bit binary digital 0, obviously added to the comparison terminal A of the binary value comparator The same as the data on the comparison terminal B, the comparison status bit "A>B" of the binary value comparator outputs a low level "0", and the output terminal W of the AND gate outputs a low level, and this low level "0" is passed through the AND gate is added to the control terminal CP of the register, at this time the register is locked, the contents stored in the register remain unchanged, and the output terminal Q of the register outputs an N-bit binary number 0.

When U _i >0V, the digital signal output terminal D _OUT of the A/D converter outputs an N-bit binary number greater than zero, and the N-bit binary number is output to the N-bit binary number of the register in parallel according to the order of the binary weight. The digital input terminal D and an N-bit binary digital comparison input terminal A of the binary value comparator, and the other N-bit binary digital comparison input terminal B added to the binary value comparator is an N-bit binary digital 0, obviously input to the binary value The data of the comparison input terminal A of the comparator is greater than the data input to the comparison input terminal B of the binary value comparator, the comparison status bit "A>B" of the binary value comparator outputs a high level "1", and U _i >0V , the zero-crossing voltage comparator a2 outputs a high level "1", when the working pulse of the system working clock is a high level "1", the output terminal W of the AND gate outputs a high level "1", this high level "1" is added to the control terminal CP of the register, and the data output by the digital signal output terminal D _OUT of the A/D converter is written into the register. Similarly, under the action of the working pulse, the detection circuit continuously compares the A/D The N-bit binary number output by the digital signal output terminal D _OUT of the converter (added to the N-bit binary number comparison input terminal A of the binary value comparator) and the N-bit binary number output by the output terminal Q of the register (added to the binary value comparison input terminal A) The N-bit binary digital comparison input terminal B of the device, if the data of the comparison input terminal A is greater than the data of the comparison input terminal B, the data output by the digital signal output terminal D _OUT of the A/D converter replaces the original data of the register, such as The data of comparison input terminal A is smaller than the data of comparison input terminal B, then the original data of the register remains unchanged, that is, the N-bit binary number output by the output terminal Q of the register is the digital output of the measured signal U _i before the arrival of the next working pulse Peak signal O _OUT .

The circuit has a certain anti-interference ability. When U _i <0V, the zero-crossing voltage comparator a2 outputs a low level "0", and the output terminal W of the AND gate outputs a low level. This low level "0" is passed through the AND gate is added to the control terminal CP of the register, and the register is locked at this time, and the data stored in the register remains unchanged, thereby preventing the circuit from being interfered by negative level signals. In addition, the gain of the voltage follower a1 is 1, and the measured signal U _i To the isolation effect, the conversion accuracy of the circuit is improved.

The choice of A/D converter digits depends on the measurement accuracy requirements. The higher the A/D converter digits, the higher the voltage peak measurement. Here, eight digits, ten digits, twelve digits, and sixteen digits can be used. The A/D converter; the number of bits of the register and the binary value comparator is determined according to the number of bits of the selected A/D converter, that is, the number of bits of the A/D converter is the same as the number of bits of the register and the binary value comparator , are N bits.

The circuit adopts the voltage follower _a1 composed of the operational amplifier A1, the zero-crossing voltage comparator _a2 composed of the voltage comparator A2, the A/D converter, the register, the binary value comparator and the AND gate circuit with three inputs and one output. Realize the voltage peak detection of the digital output, avoiding the traditional scheme to first use the analog voltage peak detection circuit to obtain the peak value, and then use the analog voltage peak value to obtain the digital output through the A/D conversion circuit. Compared with the existing technology, the circuit is simple and reliable, suitable for high and low frequency measured signal voltage peak to digital conversion, fast response, high measurement conversion accuracy, and a large dynamic range of peak detection voltage, the smallest measurable voltage of μV level, Strong digital compatibility, suitable for main logic circuits such as TTL, COMS, etc., with low dynamic energy loss.

The preferred embodiments of the present invention have been described in detail above, but the invention is not limited to the described embodiments, and those skilled in the art can also make various equivalent modifications or replacements without violating the spirit of the present invention. These equivalent modifications or replacements are all within the scope defined by the claims of the present application.

Claims (1)

1. a voltage peak detection circuit of digital output, is characterized in that, comprises: voltage follower, A/D converter, register, zero-crossing voltage comparator, binary value comparator, the AND gate of three input one output, so The non-inverting input terminal of the voltage follower is connected with the measured signal, the output terminal of the voltage follower is connected with its own inverting input terminal, the analog signal input terminal of the A/D converter, and the zero-crossing voltage comparator The N-bit binary digital signal output terminal of the A/D converter is connected with the N-bit binary digital input terminal of the register and an N-bit binary signal of the binary value comparator according to the high and low order of the binary weight. The digital comparison input terminals are connected in parallel, and the N-bit binary digital output terminals of the register are connected in parallel with another N-bit binary digital comparison input terminals of the binary value comparator according to the order of binary weight positions, and the system working clock is connected with the A The clock terminal of the /D converter is connected to the first input terminal of the AND gate, the output terminal of the zero-crossing voltage comparator is connected to the second input terminal of the AND gate, and the inverting input of the zero-crossing voltage comparator The terminal is connected to the ground, the output terminal of the binary value comparator is connected to the third input terminal of the AND gate, the output terminal of the AND gate is connected to the control terminal of the register, and the binary value comparator is used for comparing When a working pulse arrives, the value of the N-bit binary number output by the digital signal output terminal of the A/D converter and the value of the N-bit binary number stored in the register during the last working pulse, when the zero-crossing When the voltage comparator outputs a high level, when the value output by the digital signal output terminal of the A/D converter is greater than the value registered in the current register, the output terminal of the binary value comparator outputs a high level, when a When the working pulse arrives, the output terminal of the AND gate outputs a high level, and the register is controlled by the high level output of the AND gate to store the N outputted by the digital signal output terminal of the A/D converter when a working pulse arrives. When the value output by the digital signal output terminal of the A/D converter is less than or equal to the value registered in the current register, the output terminal of the binary value comparator outputs a low level, and the output terminal of the AND gate Output low level, the register is controlled by the low level output of the AND gate to keep the data registered during the last working pulse unchanged, and the binary value comparator is constantly comparing under the action of the system working clock, the register What is registered and output is the value of the maximum N-bit binary digit of the signal under test before the arrival of the next working pulse, that is, the output of the register tracks the peak value of the signal under test. When the zero-crossing voltage comparator outputs a low level, the AND gate The output terminal outputs a low level, and the register is controlled by the low level output of the AND gate to keep the registered data unchanged, that is, the voltage peak detection circuit of the digital output only tracks the measured signal greater than or equal to zero, and the voltage The gain of the follower is 1, which is used for isolation of the measured signal.