CN109727187A - Method and apparatus for adjusting the storage location of multiple semi-cylindrical hills data - Google Patents

Method and apparatus for adjusting the storage location of multiple semi-cylindrical hills data Download PDF

Info

Publication number
CN109727187A
CN109727187A CN201910005972.2A CN201910005972A CN109727187A CN 109727187 A CN109727187 A CN 109727187A CN 201910005972 A CN201910005972 A CN 201910005972A CN 109727187 A CN109727187 A CN 109727187A
Authority
CN
China
Prior art keywords
data
roi
address
storage
address range
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910005972.2A
Other languages
Chinese (zh)
Other versions
CN109727187B (en
Inventor
李军
李建军
张鑫语
李晓森
黄畅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Horizon Robotics Technology Research and Development Co Ltd
Original Assignee
Beijing Horizon Robotics Technology Research and Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Horizon Robotics Technology Research and Development Co Ltd filed Critical Beijing Horizon Robotics Technology Research and Development Co Ltd
Priority to CN201910005972.2A priority Critical patent/CN109727187B/en
Publication of CN109727187A publication Critical patent/CN109727187A/en
Application granted granted Critical
Publication of CN109727187B publication Critical patent/CN109727187B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Disclose a kind of method and apparatus for adjusting the storage location of multiple semi-cylindrical hills data.This method may include: the score according to the multiple semi-cylindrical hills data to be adjusted, and determine multiple local address ranges corresponding with the storage address range of storage region of multiple semi-cylindrical hills data to be adjusted;The first address in first partial address range for the first data as the regions of interest data currently to be adjusted, in the determination multiple local address ranges to be adjusted;The second data at first address are stored from storage region into buffer storage;And by the storage of the first data at the first address into storage region.By method and apparatus according to an embodiment of the present disclosure, the adjustment on the spot of the storage location of multiple semi-cylindrical hills data can be expeditiously realized.

Description

Method and apparatus for adjusting the storage location of multiple semi-cylindrical hills data
Technical field
The disclosure relates generally to the technical fields of artificial intelligence, and emerging for adjusting multiple senses more particularly to one kind The method and apparatus of the storage location of interesting area data.
Background technique
Such as RCNN (Regions with CNN features), spatial pyramid pond network can be used (Spatial Pyramid Pooling Network, SPP-Net), quick RCNN (Fast RCNN), more rapidly RCNN One or more perpetual objects in the methods of (Faster RCNN) detection input picture or video, and these object detection sides Method needs first to generate (or recommendation) multiple semi-cylindrical hills (Region of Interest, ROI), is then based on generated ROI data executes subsequent processing.
In the method for checking object based on ROI, need to readjust each ROI number generated according to the score of ROI According to storage location.
The common Space-time Complexity for controlling the process of the position of adjustment ROI data is very high, is not suitable in hardware It is expeditiously realized on the limited artificial intelligence chip of resource.
Summary of the invention
According to one aspect of the disclosure, it provides a kind of for adjusting the storage location of multiple semi-cylindrical hills data Method and apparatus.This method may include: the score according to the multiple semi-cylindrical hills data to be adjusted, and determining will adjust with storage The corresponding multiple local address ranges of the address range of the storage region of whole multiple semi-cylindrical hills data;For as working as Before the regions of interest data to be adjusted the first data, first partial in the determination multiple local address ranges to be adjusted The first address within the scope of location;The second data at first address are stored from storage region into buffer storage;And it will The storage of first data is at the first address into storage region.
According to another aspect of the disclosure, it additionally provides a kind of for adjusting the storage position of multiple semi-cylindrical hills data The device set.The apparatus may include buffer storage and processor, wherein it is current that buffer storage can be configured as storage The regions of interest data to be adjusted, and processor can be configured as and at least execute the above method on startup.
According to another aspect of the disclosure, a kind of computer-readable non-transitory storage medium is additionally provided, It is stored thereon with program instruction, which at least executes the above method when executed.
By method and apparatus according to an embodiment of the present disclosure, multiple semi-cylindrical hills data can be expeditiously realized Position adjustment on the spot.
Detailed description of the invention
The embodiment of the present disclosure is described in more detail in conjunction with the accompanying drawings, the above-mentioned and other purposes of the disclosure, Feature and advantage will be apparent.Attached drawing is used to provide to further understand the embodiment of the present disclosure, and constitutes explanation A part of book is used to explain the disclosure together with the embodiment of the present disclosure, does not constitute the limitation to the disclosure.In the accompanying drawings, Identical reference label typically represents same parts or step.
Fig. 1 shows the example of the storage region SR according to an embodiment of the present disclosure that store N number of ROI data.
Fig. 2 shows according to an embodiment of the present disclosure for adjusting the example of the method for the storage location of ROI data.
Fig. 3 shows the example in the process for the exemplary method for executing Fig. 2 for N number of ROI data as shown in Figure 1.
Fig. 4 shows the example of step S130 and step S140 in the exemplary method for executing Fig. 2.
Fig. 5 shows the example in the process for the exemplary method for executing Fig. 2 for N number of ROI data as shown in Figure 1.
Fig. 6 shows according to an embodiment of the present disclosure for adjusting the example of the device of the storage location of ROI data.
Specific embodiment
In the following, will be described in detail by referring to the drawings according to an example embodiment of the present disclosure.Obviously, described embodiment is only It is only a part of this disclosure embodiment, rather than the whole embodiments of the disclosure, it should be appreciated that the disclosure is not by described herein The limitation of example embodiment.
It summarizes
The excellent multistage pair of the detection effect as such as RCNN, SPP-Net, Fast RCNN and Faster RCNN As in detection method, it usually needs arrange the ROI of produced a large amount of (for example, thousands of, tens of thousands of, even hundreds of thousands of) Sequence, that is, the storage location of adjustment ROI data in memory.
In the common scheme for controlling the storage location of adjustment ROI data, it usually needs the memory configured It is capable of providing twice of memory space of the total amount of data more than or equal to ROI data, wherein memory may include above-mentioned Buffer storage and/or memory for storing initial ROI data and final ranking results.
For artificial intelligence chip, the considerations of due to different aspects such as hardware cost and chip spaces and/or limitation, The usual lower on-chip memory of configuration capacity, for example, total capacity can be the static storage of several hundred K bytes to several M bytes Device or cache memory etc..Therefore, artificial intelligence chip nothing in the case where not carrying out data exchange with chip external memory Method is independently ranked up quantity up to hundreds of thousands of or tens of thousands of ROI datas.
Even if being only ranked up to thousands of ROI datas, in artificial intelligence chip, due to needing in on-chip memory Distribution such as capacity storage region at least identical with the storage region for storing all ROI datas, therefore will also occupy more On-chip memory resource, or even need to be arranged more on-chip memories, this will increase the hardware cost of artificial intelligence chip.
Furthermore it is possible to artificial intelligence chip is assembled in terminal device as such as mobile phone, navigator, to detect Such as via one or more perpetual objects in the image or video of the shootings such as camera on terminal device.In such feelings Under condition, artificial intelligence chip can control by the storage of generated ROI data to setting within terminal device and in artificial intelligence It can be in the chip external memory except chip, it might even be possible to which control is executed by the processor in terminal device to being stored in piece external storage The sequence of ROI data in device.
However, terminal device as mobile phone, navigator generally also has treatment effeciency, power consumption and hardware cost etc. It has higher requirements.The higher space complexity of common ROI sequencing schemes is (for example, it is desired to store institute in capacity and memory Have the identical buffer zone of the storage region of ROI data) it will lead to the higher hardware cost of terminal device needs, such as need to match Set the memory of more multicapacity.
Therefore, it is always desirable to while the accuracy and precision of the efficiency and result that ensure to execute, as far as possible It reduces artificial intelligence chip or is assembled with the hardware cost of the terminal device of artificial intelligence chip.
Method and apparatus according to an embodiment of the present disclosure for adjusting the storage location of ROI data, it is intended at least portion Point ground solves or alleviates one or more of above-mentioned technical problem, so that artificial intelligence chip or being assembled with artificial intelligence chip Terminal device can expeditiously realize ROI data storage location adjustment on the spot, may be needed without configuration capacity More than or equal to the buffer zone of the storage region in memory for storing all ROI datas.
Illustrative methods
Fig. 1 shows N number of ROI data ROI in the storage region SR for having generated and being consecutively stored in memory1、 ROI2、……、ROIN, wherein N is greater than 1 integer, such as hundreds of thousands of, tens of thousands of or thousands of, and ROI1、ROI2、……、 ROINThe address AD DR being stored respectively in storage region SR1、ADDR2、……、ADDRNPlace.In other words, N number of ROI data ROI1、ROI2、……、ROINIt is consecutively stored in and corresponds to continuous address space ADDR1To ADDRN(herein, also referred to as " full address range ") storage region SR in.
Here, due to each ROI data usually may include multiple data item (for example, the coordinate of ROI, width, height, Score etc.), so the address AD DR in storage region SR1、ADDR2、……、ADDRNIn each address it is corresponding be memory block For storing the first address of the unit storage region of each ROI data in the SR of domain, rather than each of storage region SR is physically Storage unit first address.Herein, in order to simple, it is assumed that each ROI data only occupy storage region SR one deposits Storage unit, or memory block is only occupied in the case where storage region SR is the two-dimensional storage region determined according to two dimensional memory A storage line or cache lines of domain SR or buffer area.
It needs to adjust storage location of each ROI data in storage region SR according to the score of each ROI data, so that According to a kind of order, for being stored respectively in ADDR after the adjustmentiAnd ADDRi+1ROIiAnd ROIi+1(i is greater than or equal to 1 And it is less than the arbitrary integer of N), ROIiScore be less than or equal to ROIi+1Score, or according to another order, for ADDR is stored respectively in after adjustmentiAnd ADDRi+1ROIiAnd ROIi+1, ROIiScore be greater than or equal to ROIi+1Score.
Fig. 2 shows according to an embodiment of the present disclosure for adjusting ROI1、ROI2、……、ROINStorage location in SR Method example, which may include step S110, S120, S130 and S140.
It in step s 110, can be according to ROI1、ROI2、……、ROINEach of ROI score, it is determining with it is complete Address range ADDR1To ADDRNCorresponding multiple local address range L S1To LSK, wherein K is the integer greater than 1, such as 256, and LS1To LSKIn each local address range size (or included company in each local address range The quantity of continuous address or the corresponding memory capacity of each local address range) ROI can be depended on1、ROI2、……、 ROINIn with score corresponding with the local address range ROI data quantity.
It is then possible to from ROI1、ROI2、……、ROINAny one of data (for example, ROI1) start, to belonging to ROI1、ROI2、……、ROINIn and the data ROI currently to be adjusted of the current cache in buffer storage BUFcur(at this Wen Zhong, also referred to as " the first data ") execute step S120 to S140.
In the step s 120, LS can be determined1To LSKIn LSk(herein, also referred to as " first partial address model Enclose ", wherein k be more than or equal to 1 and be less than or equal to K integer) in ADDRdes(herein, also referred to as " the first ground Location "), wherein ROIcurHave and LSkCorresponding score, and ADDRdesThe data ROI at placenxt(referred to herein as " the second data ") it is not adjusted ROI data.
It in step s 130, can be by ADDRdesThe data ROI at placenxtFrom storage region SR storage to buffer storage BUF In.
It, can be by ROI in step S140curAs adjusted ROI data storage to the ADDR in storage region SRdes Place.
It should be noted that in the ROI being buffered in buffer storage BUFnxtIt is not adjusted ROI data or deposits It, can be for example according to the ROI in buffer storage BUF in the case where further including unadjusted ROI data in the SR of storage area domainnxtReally The fixed new ROI data to be adjusted is (that is, new ROIcur) continue to execute above-mentioned step S120 to S140.Repeatedly, until Until all ROI datas in storage region SR become adjusted ROI data.
Herein, " the adjusted ROI data " in storage region SR may mean that the ROI data is ROI1、 ROI2、……、ROINIn a ROI data, and its storage location in storage region SR is storage position adjusted It sets, therefore the ROI data can be skipped in subsequent processing (if there is);" unadjusted ROI number in storage region SR According to " it may mean that the ROI data is ROI1、ROI2、……、ROINIn previously from it is not visited and/or processing one it is original ROI data;" not being adjusted ROI data " may mean that the data can be unadjusted ROI data, be also possible to Special ROI data or special data with the particular values such as null value (NULL) or " -1 " are (for example, can be used for being marked Note, or the effects of simplifying processing can be played).
It, can be directly on the storage region SR of allocation to ROI number by method according to an embodiment of the present disclosure It is adjusted according to progress " on the spot ".Other than the storage region SR for storing original each ROI data itself, for adjusting The buffer storage BUF for providing the buffer zone of auxiliary in the process may include two cache lines or buffer area (in other reality Apply in example, buffer storage BUF be also possible to including storage region SR memory in different from the two of storage region SR A memory block), for buffering the intermediate data being related to during the adjustment, i.e., ROI above-mentionedcurAnd ROInxt.Even if relative to For the artificial intelligence chip for usually only configuring on-chip memory of several hundred K bytes to several M bytes, buffer storage BUF's is hard Part cost is also negligible.
Moreover, not needing preservation in method according to an embodiment of the present disclosure and being for example used to indicate each ROI data The extra datas such as contextual link, pointer.It means that each of storage region SR and buffer storage BUF Capacity is solely dependent upon the size of ROI data itself.For example, if a ROI data itself (may include ROI coordinate, width The information related with ROI itself such as degree, height, confidence level, but do not include be used to indicate it is contextual with other ROI datas The information such as link, pointer) size be s byte, then the case where not considering the necessary overheads such as alignment of data Under, memory space needed for method according to an embodiment of the present disclosure (including storage region SR and buffer storage BUF) it is total Capacity only has (N+2) * s byte.
In addition, method according to an embodiment of the present disclosure can be while disposably having traversed all ROI datas The adjustment to the storage location of all ROI datas is completed, there is simple and highly efficient control logic.
It therefore, can be expeditiously real with minimum hardware cost by exemplary method according to an embodiment of the present disclosure The adjustment on the spot of existing ROI data, has extremely low space complexity and time complexity.For example, will be according to the reality of the disclosure The exemplary method for applying example is implemented on artificial intelligence chip, with the storage position of the ROI data to initial storage in on-chip memory Set in the case where being adjusted, artificial intelligence chip may not necessarily to on-chip memory carry out dilatation or add it is other for example Capacity may need to be greater than or equal to for storing the buffer storage of the storage region of all ROI datas in on-chip memory, And artificial intelligence chip can expeditiously execute the adjustment of the storage location of ROI data by simple control logic.
It should be appreciated that in the different circulations determined according to step S120 to S140, the first data ROIcur, first partial Address range LSk, the first address AD DRdes, the second data ROInxtDeng and below may trip such as " the second address ", Each of " second local address range " etc. can have or corresponding to different data value/data item/data contents.
The more details of method according to an embodiment of the present disclosure are described below with reference to example.
It in various embodiments, can be by the mode appropriate such as region recommendation network, selective search for input Image or video in one or more perpetual objects (for example, personage, animal, vehicle, marker in image or video, Building, lane line etc.) generate ROI data, wherein and each ROI data generated has corresponding score, such score It usually can be the confidence level of the ROI, and can be pass through during calculating the confidence level of ROI in some embodiments Omit confidence level substitution value obtained from Nonlinear Processing.
In method for checking object (including such as RCNN, SPP-Net, Fast RCNN and Faster RCNN based on ROI The method for checking object of the single phases such as the excellent multistage method for checking object of such detection effect and Tiny-SSD) In, it needs to be ranked up each ROI data according to the score of each ROI data, in other words, according to obtaining for each ROI data Divide the storage location of each ROI data of adjustment in memory, so that after the adjustment, each ROI data is in memory Coutinuous store in an orderly manner.
Due to the limitation of hardware aspect, such as the register or buffer-stored of the score for depositing or caching ROI data Device usually has limited digit, thus the score of the ROI data actually generated and ROI data other data item (for example, The coordinate of ROI, the width of ROI, height of ROI etc.) can only the numerical value with predetermined accuracy be used to indicate.For example, can adopt With the hardware configuration for the floating number that can support 32 bit accuracies, so as to indicate the 2 of ROI data32=4294967296 kinds Score.
As it was noted above, in the artificial intelligence system based on GPU or TPU, it can be not any for resource and power consumption Limitation, therefore with can having no pressure using the floating number representation of 32 bit accuracies.However, for artificial intelligence chip with And mobile phone etc. needs for hardware cost carries out the terminal device of strict control, the floating number expression side of 32 bit accuracies Formula will lead to higher hardware cost.
By analyzing the algorithm principle of the method for checking object based on ROI and carrying out a large amount of experiment discovery, at least for The score of ROI data can use precision more lower than common 32 bit accuracy.For example, by the confirmation that largely works, it can It is final without influencing with by the predetermined accuracies more than Score quantifies of ROI to 6 bits, such as 6 bit accuracies or 8 bit accuracies The precision of testing result.
Then, in embodiment of the disclosure, can be by the Score quantifies of ROI data to predetermined accuracy, such as it can be low In common 32 bit accuracy, such as 6 bit accuracies, 8 bit accuracies, 10 bit accuracies, 16 bit accuracies etc..
For example, each ROI data will have 2 in the case where quantization is to 6 bit accuracy6=64 kinds of scores;It is arrived in quantization In the case where 8 bit accuracies, each ROI data will have 28=256 kinds of scores;In the case where quantization is to 10 bit accuracy, Each ROI data will have 210=1024 kinds of scores;It is such.Using predetermined accuracy more lower than common 32 bit accuracy The score for indicating ROI data can reduce hardware cost significantly and improve treatment effeciency.
As it was noted above, being formed and stored in the ROI in storage region SR1、ROI2、……、ROINQuantity N usually may be used To be hundreds of thousands of, tens of thousands of or thousands of.By the Score quantifies of each ROI to such as 6 bit accuracies or 8 bit accuracy predetermined accuracies In the case where, in fact it could happen that ROI score maximum kind of number (for example, being 64 kinds in the case where 6 bit accuracy, in 8 bits essence It is 256 kinds in the case where degree) it also will be substantially less that N, so that ROI1、ROI2、……、ROINIn one or more ROI datas can be with Score having the same.
In one embodiment, for any score under predetermined accuracy, ROI can generated1、 ROI2、……、ROINIt is middle to count the quantity with the ROI data of this score.For example, as shown in figure 3, can be for predetermined Corresponding counter cnt is arranged in every kind of ROI score under precision1To CNTM, wherein for example the case where using 8 bit accuracy Under, M can be equal to 256, and such as counter cnt1For counting the quantity of the ROI data with the first ROI score, meter Number device CNT2For counting the quantity of the ROI data with second of ROI score, and so on.It will be appreciated, however, that this is simultaneously Do not mean that the first ROI score score value must be 1 and the score value of the first ROI score must be 2.Herein In, for the convenience described, use counter cnt1To CNTMEach of subscript (that is, each of 1 to M) generation It in other words in one embodiment, can be by each ROI number for the score value for indicating ROI score corresponding with the counter According to score be mapped to it is corresponding with predetermined accuracy include 1 to M natural number within the scope of some numerical value.
For the convenience of subsequent adjustment/sequence, and also to the convenience described, it can be stated that for any two Counter cntpAnd CNTn(1≤p < n≤M), with counter cntpCorresponding ROI score is less than counter cntnIt is corresponding ROI score.However, the disclosure is not limited to this, (for example, requirement of sequence) can according to need to counter and ROI score Between corresponding relationship make miscellaneous stipulations, such as also can specify that and counter cntpCorresponding ROI score, which is greater than, to be counted Device CNTnCorresponding ROI score.
Clearly for counter cnt1To CNTMAny one of counter cnt s (s be greater than or equal to 1 and be less than or Any integer equal to M), it final count value after generating all ROI data or is executing according to the disclosure Initial value before the method and step S110 of embodiment can be the value in range [0, N], wherein 0 may mean that and give birth to At and be stored in value of the score of any one of all ROI datas in SR ROI data under predetermined accuracy not for s, And N may mean that value of the score of all ROI datas in be formed and stored in SR under predetermined accuracy is s.It is practical On, as described above, in the case where predetermined accuracy is 6 bits or more, counter cntsInitial value before step S110 is logical Chang Buhui is N, in addition be typically not close to some value.
It then, in step s 110, can be according to counter cnt1To CNTMIn each counter cntsInitial value it is true Fixed and storage region SR full address range ADDR1To ADDRNCorresponding multiple local address range L S1To LSK
For example, K can be identical as M, and if counter cnt1Initial value be C1 and counter cnt2Initial value For C2, that is, in the ROI being stored in SR1、ROI2、……、ROINIn have value of the score of C1 ROI data under predetermined accuracy Be 1, and have value of the score of C2 ROI data under predetermined accuracy be 2, then with counter cnt1Corresponding local address model Enclose LS1It may include the continuous C1 address AD DR in storage region SR1To ADDRC1, and and counter cnt2Corresponding office Portion address range LS2It may include the continuous C2 address AD DR in storage region SRC1+1To ADDRC1+1+C2If, wherein C1=0, then with counter cnt2Corresponding local address range L S2It may include the continuous C2 address in storage region SR ADDR1To ADDR1+c2, and counter cnt can be disabled at this time1, so that local address range L S1Actually become in vain simultaneously Therefore may not necessarily consider.In other examples, the quantity K of actually determined local address range can be less than or equal to The quantity M of the counter of actual setting.For example, K can be less than M in the forbidden situation of one or more counters.
Similarly, local address range L S can be determined1To LSKIn other local address ranges, and similarly, just The counter that initial value is 0 can be disabled.
For the convenience described, in the example of fig. 3, counter cnt1To CNTMEach of initial value not It is 0.Correspondingly, local address range L S1To LSKEach of may include full address range ADDR1To ADDRNInterior one A or multiple continuous address, and full address range ADDR1To ADDRNIn any one address be pertaining only to locally Location range L S1To LSKIn a local address range.
In the example of fig. 3, the data ROI currently to be adjustedcurIt is ROI1、ROI2、……、ROINIn ROIi(i is big In or equal to 1 and be less than or equal to the integer of N), and buffer storage can be buffered in front of executing step S120 In the cache lines or buffer area L1 (referred to herein as " first buffering area ") of BUF.
For example, if ROIcur(for example, the ROI in the example of Fig. 3i) it is ROI1、ROI2、……、ROINIn first The ROI data being adjusted then can store ROI from storage region SR before executing step S120curOriginal address ADDRorg(for example, the ADDR in the example of Fig. 3i) at read ROIcur, and it is cached to the cache lines of buffer storage BUF In L1.
Determining ROIcurLater, for example, by ROIcurIt, can be by ADDR after being cached in buffer storage BUForg The data markers at place be no longer be untreated ROI data.
It in one embodiment, can be by ROIcurThe cache lines L1 of buffer storage BUF is cached to from storage region SR Later, by the address AD DR in storage region SRorgThe data at place empty or are set as empty data (NULL) or " -1 " etc. Special data can also modify ADDRiThe ROI data at place, so that in ADDRorgCertain number in the modified ROI data at place There is particular value as such as " -1 " or empty data according to item (such as score).
It then, in the step s 120, can be according to the ROI being cached in buffer storage BUFcurScore, determine part Address range LS1To LSMIn local address range L S corresponding with the scorek.For example, can be according in buffer storage BUF ROIcurScore, determine above-mentioned counter cnt1To CNTMIn counter cnt corresponding with the scorek, so that it is determined that Local address range L Sk
Obviously, local address range L S at this timekIn at least one address at data be not adjusted ROI data (can be unadjusted ROI data, be also possible to sky data or other special datas).Thus it is possible to determine local address model Enclose LSkIn an address AD DRdes(for example, the ADDR in the example of Fig. 3j), in address AD DRdesData ROInxt(for example, ROI in the example of Fig. 3j) it is not adjusted ROI data.
In one embodiment, local address range L S can one by one be detectedkIn each address at data mode, So that it is determined that address above mentioned ADDRdes
In another embodiment, can according to local address range L SkCorresponding counter cntkIn count value Or data determine address above mentioned ADDRdes.For example, can be according to counter cntkIn count value determine relative to local address Range L SkPresumptive address (for example, LSkFirst address) offset, and local address model can be determined according to the offset Enclose LSkIn address AD DRdes.It is then possible to be in due course, such as determining address ADDRdesLater, address is being read ADDRdesThe ROI at placenxtLater, by ROIcurIt is written to address AD DRdesAfter place, CNT is updatedkIn data or count value, So that updated data correspond to local address range L SkThe address of interior not visited mistake.
For example, it may be determined that in counter cntkEach count value and local address range L SkIn each address between Corresponding relationship, and utilize counter cntkCurrent count value from local address range L SkMiddle determining address above mentioned ADDRdes.For example, can control counter cntkIt is in due course from initial value (that is, having score corresponding with k The quantity of ROI data) start degressively to count, and by counter cntkEach count value as example from local address range LSkFirst address start to local address range L SkTail address direction offset.When initial value is not 0 counter cntk Count value become 0 when, it is meant that the storage location of all ROI datas with score corresponding with k is adjusted It finishes.It is then possible to according to counter cntkCurrent count value CNTk.V with local address range LSkFirst address, definitely Location ADDRdes.Thus, it is possible to ensure local address range L SkIn address AD DRdesThe ROI data at place is not adjusted ROI Data, and in address AD DRdesLater until local address range L SkTail address in each address at ROI data be Adjusted ROI data.
In one embodiment, can be set respectively with local address range L S1To LSMOr counter cnt1To CNTMPhase Corresponding address register AR1To ARM(being not shown in Fig. 3), wherein address register ARkFor saving local address range LSkSuch as first address.That is, with local address range L SkCorresponding register and/or counter for example can wrap Include address register ARk.As it was noted above, the value due to M is smaller, so such hardware spending is even for artificial intelligence core It is also fully acceptable for piece.
In a further embodiment, for example, can in memory or buffer storage store local address range L S1 To LSMIn each local address range first address or tail address, without being separately provided address register.
It should be appreciated that the disclosure is not limited to above-mentioned example.For example, since relative address representation is (for example, count value Or address offset amount) can be easy mutually to convert with absolute address representation, so the meter being described herein as example Number device CNT1To CNTMUsage mode can be revised as based on relative address representation (for example, count value or address offset Amount) other any processing modes appropriate, and can be revised as with the processing mode based on absolute address representation.
Determining address ADDRdesIt later, can be in step s 130 by original storage in ADDRdesThe ROI at placenxtAs ROInxtIt is cached in buffer storage BUF, and by the ROI in buffer storage BUF in step S140curWith covering ADDRdesThe mode of the initial data at place stores ADDRdesPlace.
It in one embodiment, can in step s 130, by the ROI in buffer storage BUFcurFrom buffer storage The cache lines L1 of BUF is moved to another cache lines or buffer area L2 (referred to herein as " second of buffer storage BUF Buffer area ") in, it then will be stored in ADDRdesThe ROI at placenxtIt is cached in the cache lines L1 of buffer storage BUF.Then, may be used With in step S140, by the ROI in cache lines L2curTo cover ADDRdesThe initial data at place is (that is, ROInxt) mode deposit Store up ADDRdesPlace.
In another embodiment, the ROI in the cache lines L1 of buffer storage BUFcurIt can step S120 previous In be moved in the buffer area L2 of buffer storage BUF.Then, in step s 130, ADDRdesThe ROI at placenxtCan directly it delay It is stored in the cache lines L1 of buffer storage BUF.It then, can be by the ROI in cache lines L2 in step S140curWith covering ADDRdesThe mode of the initial data at place stores ADDRdesPlace.In this embodiment it is possible to control within a read-write cycle Realize step S130 and S140.
For example, as shown in figure 4, step S130 can be executed to control ADDR in the rising edge of a clockdesPlace ROInxtBe cached in the cache lines L1 of buffer storage BUF, and the failing edge of the clock execute step S140 with control by ROI in cache lines L2curTo cover ADDRdesThe mode of the initial data at place stores ADDRdesPlace.
The ROI currently to be adjusted as a result,cur(for example, the ROI in the example of Fig. 3i) it can be used as adjusted ROI data Store the ADDR of SRdesPlace, and and LSkThe count value of corresponding counter cnt k can in the process appropriate when Machine updates, such as subtracts 1, and becomes in the case where count value is not still 0 and ADDRdesPrevious address AD DRdes-1It is corresponding Value.If CNTkCount value become 0, then mean the storage position of all ROI datas with score corresponding with k Set it is adjusted finish, and counter cnt can be disabled in one embodimentk
As shown in figure 3, in one case, ROI to be processed in each circulationcurOr determine in each cycle The ROI to be handled in circulation next timenxtIt can directly be ROI1To ROINIn a unadjusted ROI data.
Thus it is possible to by ROInxt(that is, ROIj) as the ROI recycled next timecur.For example, step can be being passed through S140 is by ROIcur=ROIiStore the ADDR of storage region SRdes=ADDRjAfter place and enter the step of recycling next time Before S120, by variable R OIcurFrom ROIiIt is updated to ROIj.Then, for new ROIcur=ROIjStep S120 is executed again To S140.
For example, can be by being counted to cycle-index, and can be ended processing when cycle-index reaches n times.
In other some cases (for example, current ROIcurIt is ROI1To ROINIn the ROI that adjusts of the last one needs Data, the ADDR determined in the step s 120desWith reading ROIcurADDRorgADDR that is identical, determining in the step s 120des It has been processed, etc. in circulation previous) under, the ROI that is cached in buffer storage BUF in step s 130nxtIt can It can not be unadjusted ROI data, but for example processed ROI data or be marked in circulation previous (for example, data itself are arranged to the data item such as the score in the special datas such as empty data, " -1 " or data With particular values such as " -1 ") ROI data, or the ROI handled in previous cyclecur(at this point, ADDRdes With ADDRorgIt is identical), etc..
For this purpose, can be after step s 140 and before execute the step S120 recycled next time, for example, in BUF The ROI of middle current cachenxtBe not the adjusted ROI data in unadjusted ROI data and storage region SR quantity it is small In the case where N, the address AD DR of another not visited mistake in storage region SR is determinednew(it is herein, also referred to as " the Double-address "), and use address AD DRnewThe ROI data at place updates the ROI in BUFnxtAnd it to be adjusted as next ROIcur
In order to determine new address AD DRnew, in one embodiment, can determine LS1To LSKIn LSK,(herein In, also referred to as " second local address range ", wherein k ' is more than or equal to 1 and to be less than or equal to the integer of K, and k ' and k can be with It is identical or different), wherein LSK,It inside may include the address of at least one not visited mistake, for example, and LSK,Corresponding meter Number device CNTk’Count value currently not be 0.It is then possible to according to counter cntk’Count value determine new address AD DRnew
In one embodiment, current to detect as shown in figure 5, step S150 can be entered after step s 140 The ROI being buffered in BUFnxtIt whether is unadjusted ROI.In one embodiment, it can detecte current cache BUF's ROI in cache lines L1nxtIt whether is the empty special datas such as data or " -1 ".In another embodiment, it can detecte and work as Before be buffered in ROI in the cache lines L1 of BUFnxtCertain data item or field (such as score) whether have such as " -1 " Equal particular values.
"Yes" is returned (for example, ROI in step S150nxtIt is not special data or does not include the case where special data item) Under, it can be by ROInxtAs new ROIcur, and it is directed to new ROIcurExecute step S120.
In the case where step S150 returns to "No", step S160 can continue to, to redefine ROInxt.For example, can According to CNT1To CNTMIn any one count value still be 0 counter cntk’, so that it is determined that LSk’, then basis should Counter cntk’Current count value determination belong to LSK,Address AD DRnew.It is then possible to by address AD DRnewThe ROI number at place According to as new ROInxtReplace the ROI being cached in BUF in step s 130nxt, and step S120 is continued to execute (that is, Fig. 5 " new ROI is successfully determined in examplenxt" the case where).
If finding CNT in step S1601To CNTMIn each count value be 0, then may mean that memory block The quantity of adjusted ROI data in the SR of domain has reached N, that is, all ROI, which have been adjusted, to be finished.In addition, for example, It can be by being counted to cycle-index, and can be ended processing when cycle-index reaches n times.
In the above example, in step S150, through detection current cache in the cache lines L1 of BUF ROInxtIt whether is the ROI of the empty special datas such as data or " -1 " or current cache in the cache lines L1 of BUFnxt's Whether certain data item or field (such as score) have particular values such as " -1 ", judge current ROInxtIt whether is not adjust Whole ROI.In a further embodiment, such as an address register can be set, the primary data in the register can be with It is original storage address of the ROI data of first processing in storage region SR.It is then possible to which detection exists in step S150 Determination is ADDR in step S120desIt is whether identical as the address stored in the address register.If identical, step S150 "No" can be returned, "Yes" is otherwise returned.Then, in step S160, if being successfully determined new ROInxt, can be used Address AD DRnewThe data in the address register are updated, and method is made to proceed to S120.
As described above, counter cnt1To CNTMQuantity can be much smaller than ROI1To ROINQuantity.Moreover, some In embodiment, the list of counter can establish, control the counter when the count value of some counter becomes 0 from list Then middle deletion or disabling can be attempted to determine new in step S160 according to the gauge outfit for being located at list or the counter at table tail ROInxt.Therefore, the implementation procedure of step S150 and S160 can be very fast, and is not related at other circulation even Reason.
Method according to an embodiment of the present disclosure can traverse ROI1To ROINIn each ROI data while it is complete The adjustment on the spot of the storage location of pairs of each ROI data.
It therefore, can be expeditiously real with minimum hardware cost by exemplary method according to an embodiment of the present disclosure The adjustment on the spot of existing ROI data, has extremely low space complexity and time complexity.
For example, exemplary method according to an embodiment of the present disclosure is implemented on artificial intelligence chip, to initial storage In the case that the storage location of ROI data in on-chip memory is adjusted, artificial intelligence chip may not necessarily be on piece Memory carries out dilatation or adds other such as capacity may needing to be greater than or equal in on-chip memory for storing institute There is the buffer storage of the storage region of ROI data, and artificial intelligence chip can pass through simple control logic high efficiency Ground executes the adjustment of the storage location of ROI data.
It should be appreciated that exemplary method according to an embodiment of the present disclosure can be applied to it is any desired to generated and even The scene that the multiple ROI datas stored continuously are sorted on the spot, and the application being not limited in artificial intelligence chip.
Exemplary means
Fig. 6 shows according to an embodiment of the present disclosure for adjusting the device of the storage location of multiple semi-cylindrical hills data Example DEV, may include processor or controller CON and buffer storage BUF.
Processor or controller CON for example can be the processing based on exploitations such as field programmable gate array, arm processors Device circuit or control logic circuit, and can be configured as and root is executed according to predetermined instruction at starting (for example, being powered) According to the step in the method (for example, Fig. 3 or exemplary method shown in fig. 5) of embodiment of the disclosure.
Buffer storage BUF can be any appropriate type such as cache memory, register, static memory Storage unit.Buffer storage BUF can according to the instruction of processor CON or under the control of processor CON storage or Intermediate data involved in the processing or logic control process of cache processor CON, including for example previously described ROIcurWith/ Or ROInxt
In one embodiment, buffer storage BUF may include two buffer areas or cache lines (for example, the example of Fig. 4 In L1 and L2), and the capacity of each buffer area can depend on single ROI data size.
In addition, as shown in fig. 6, exemplary device DEV can also include multiple counter cnts1To CNTM, so as to respectively to tool There is the quantity of the ROI data of score corresponding with 1 to M to be counted, so that assist process device CON is determined and deposited in memory Store up ROI1To ROINStorage region SR the corresponding multiple local address ranges of address range.
In one embodiment, counter cnt1To CNTMQuantity M can depend on each ROI data score essence Degree.For example, M can be equal to 256, and such as counter cnt using 8 bit accuracy1Have for counting A kind of quantity of the ROI data of ROI score, counter cnt2For counting the number of the ROI data with second of ROI score Amount, and so on.
It should be appreciated that device according to an embodiment of the present disclosure is not limited to the example in Fig. 6.For example, in other reality It applies in example, device according to an embodiment of the present disclosure can also include such as the timing controller of instruction sequencing control, use In the interrupt control unit, the crossbar switch for realizing the interconnection between component and/or multiple selector, association of instruction breaks control The other components such as processor/modules/circuits/cells/elements.
In addition, device/components/elements/the modules/circuits at line both ends can for example pass through data/address bus in Fig. 6 And/or instruction bus etc. is directly connected or is coupled together, can also via crossbar switch (Crossbar) etc. other Mediating device/components/elements/modules/circuits are connected or are coupled together indirectly, wherein the arrow of line can indicate quilt The instruction of concern and/or the flow direction of data, but it is not meant to that instruction and/or data can only flow as indicated by the arrows It is dynamic.
In one embodiment, device according to an embodiment of the present disclosure for example may be embodied as the piece of artificial intelligence chip A part of upper device or on piece device.In a further embodiment, device according to an embodiment of the present disclosure can be applied to In any desired scene to be sorted on the spot to the multiple ROI datas for having generated and continuously having stored or device.
Illustrative computer program product and computer readable storage medium
Other than the above method and equipment, embodiment of the disclosure can also be computer program product comprising meter Calculation machine program instruction, the computer program instructions make processor execute the above-mentioned " example of this specification when being run by processor According to the step in the method for the various embodiments of the disclosure described in property method " part.
Computer program product can be write with any combination of one or more programming languages for executing sheet The program code of open embodiment operation, programming language may include object oriented program language, such as Java, C++ etc. further includes conventional procedural programming language, such as " C " language or similar programming language.Program code It can fully execute on the user computing device, partly execute, held as an independent software package on a user device Part executes on a remote computing or completely in remote computing device or service on the user computing device for row, part It is executed on device.
In addition, embodiment of the disclosure can also be computer readable storage medium, such as computer-readable non-face When property storage medium, is stored thereon with program instruction, and program instruction makes processor execute this explanation when being run by processor According to the step in the method for the various embodiments of the disclosure described in above-mentioned " illustrative methods " part of book.
Computer readable storage medium can be using any combination of one or more readable mediums.Readable medium can be Readable signal medium or readable storage medium storing program for executing.Readable storage medium storing program for executing for example can include but is not limited to electricity, magnetic, optical, electromagnetic, red The system of outside line or semiconductor, device or device, or any above combination.The more specific example of readable storage medium storing program for executing (non exhaustive list) includes: the electrical connection with one or more conducting wires, portable disc, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, portable tight Gather disk read-only memory (CD-ROM), light storage device, magnetic memory device or above-mentioned any appropriate combination.
The basic principle of the disclosure is described in conjunction with specific embodiments above, however, it is desirable to, it is noted that in the disclosure The advantages of referring to, advantage, effect etc. are only exemplary rather than limitation, must not believe that these advantages, advantage, effect etc. are the disclosure Each embodiment is prerequisite.In addition, detail disclosed above is merely to exemplary effect and the work being easy to understand With, rather than limit, it is that must be realized using above-mentioned concrete details that above-mentioned details, which is not intended to limit the disclosure,.
Device involved in the disclosure, device, equipment, system block diagram only as illustrative example and be not intended to It is required that or hint must be attached in such a way that box illustrates, arrange, configure.As those skilled in the art will appreciate that , it can be connected by any way, arrange, configure these devices, device, equipment, system.Such as "include", "comprise", " tool " etc. word be open vocabulary, refer to " including but not limited to ", and can be used interchangeably with it.Vocabulary used herein above "or" and "and" refer to vocabulary "and/or", and can be used interchangeably with it, unless it is not such that context, which is explicitly indicated,.Here made Vocabulary " such as " refers to phrase " such as, but not limited to ", and can be used interchangeably with it.
It may also be noted that each component or each step are can to decompose in the device of the disclosure, device and method And/or reconfigure.These decompose and/or reconfigure the equivalent scheme that should be regarded as the disclosure.
Herein, " first ", " second " etc. without the qualifier of quantifier be intended for distinguishing different elements/ Component/circuits/modules/device/step, rather than emphasize order, positional relationship, significance level, priority level etc..Not with this Together, " first ", " second " etc. can be used for emphasizing different elements/components/circuit/moulds with the qualifier of quantifier Block/device/step order, positional relationship, significance level, priority level etc..
The above description of disclosed aspect is provided so that any person skilled in the art can make or use this It is open.Various modifications in terms of these are readily apparent to those skilled in the art, and are defined herein General Principle can be applied to other aspect without departing from the scope of the present disclosure.Therefore, the disclosure is not intended to be limited to Aspect shown in this, but according to principle disclosed herein and the consistent widest range of novel feature.
In order to which purpose of illustration and description has been presented for above description.In addition, this description is not intended to the reality of the disclosure It applies example and is restricted to form disclosed herein.Although already discussed above multiple exemplary aspects and embodiment, this field skill Its certain modifications, modification, change, addition and sub-portfolio will be recognized in art personnel.

Claims (14)

1. a kind of method for adjusting the storage location of multiple semi-cylindrical hills data, comprising:
According to the score of the multiple regions of interest data, the memory block with the multiple regions of interest data of storage is determined The corresponding multiple local address ranges of the address range in domain;
For the first data as the regions of interest data currently to be adjusted, determine in the multiple local address range The first address in first partial address range;
The second data at first address are stored from the storage region into buffer storage;And
By first data storage at the first address in the storage region.
2. according to the method described in claim 1, wherein, each local address range in the multiple local address range Size depends on the region of interest in the multiple regions of interest data with score corresponding with the local address range The quantity of numeric field data.
3. according to the method described in claim 1, wherein, first data have opposite with the first partial address range The score answered, and the second data of first address are not adjusted regions of interest data.
4. according to the method described in claim 3, wherein it is determined that first partial address model in the multiple local address range The first address in enclosing includes:
First address is determined according to the count value of counter corresponding with the first partial address range.
5. according to the method described in claim 4, further include:
The count value for updating counter corresponding with the first partial address range, so that updated count value corresponds to The address of not visited mistake in the first partial address range.
6. according to the method described in claim 1, wherein, the second data at first address are deposited from the storage region It stores up in buffer storage and includes:
By the first data storage in the first buffering area for being buffered in the buffer storage to the second of the buffer storage In buffer area;And
By second data from the first buffering area that the storage region is cached to the buffer storage.
7. according to the method described in claim 6, wherein, the first data in the buffer storage are stored to the storage Include: at the first address in region
The first data in the second buffering area are stored at the first address in the storage region.
8. method according to any one of claims 1 to 7, further includes:
In the case where second data are unadjusted regions of interest data, second in the buffer storage is determined Data are as next regions of interest data to be adjusted.
9. method according to any one of claims 1 to 7, further includes:
It is not that adjusted sense in unadjusted regions of interest data and the storage region is emerging in second data In the case that the quantity of interesting area data is less than the quantity of the multiple regions of interest data, determine in the storage region Data at second address of not visited mistake are as next regions of interest data to be adjusted.
10. according to the method described in claim 9, wherein it is determined that the second address of the not visited mistake in the storage region The data at place include: as next regions of interest data to be adjusted
It determines the second local address range in the multiple local address range, includes extremely in the described second local address range The address of a few not visited mistake;And
Second address is determined according to the count value in counter corresponding with the second part address range.
11. a kind of computer-readable non-transitory storage medium, is stored with program instruction on it, described program instruction exists It is performed and at least executes according to claim 1 to method described in any one of 10.
12. a kind of for adjusting the device of the storage location of multiple semi-cylindrical hills data, comprising:
Buffer storage is configured as the storage regions of interest data currently to be adjusted;And
Processor is configured as at least executing on startup according to claim 1 to method described in any one of 10.
13. according to the method for claim 12, wherein the buffer storage includes two buffer areas, each buffer area Capacity depend on single regions of interest data size.
14. device according to claim 12 or 13, further includes:
Multiple counters, each counter is corresponding with a local address range respectively, and the quantity of the multiple counter takes Certainly in the precision of the score of each regions of interest data.
CN201910005972.2A 2019-01-03 2019-01-03 Method and device for adjusting storage position of multiple region of interest data Active CN109727187B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910005972.2A CN109727187B (en) 2019-01-03 2019-01-03 Method and device for adjusting storage position of multiple region of interest data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910005972.2A CN109727187B (en) 2019-01-03 2019-01-03 Method and device for adjusting storage position of multiple region of interest data

Publications (2)

Publication Number Publication Date
CN109727187A true CN109727187A (en) 2019-05-07
CN109727187B CN109727187B (en) 2023-05-30

Family

ID=66298058

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910005972.2A Active CN109727187B (en) 2019-01-03 2019-01-03 Method and device for adjusting storage position of multiple region of interest data

Country Status (1)

Country Link
CN (1) CN109727187B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110428359A (en) * 2019-08-09 2019-11-08 南京地平线机器人技术有限公司 Device and method for handling regions of interest data
CN112406884A (en) * 2019-08-20 2021-02-26 北京地平线机器人技术研发有限公司 Vehicle driving state recognition method and device, storage medium and electronic equipment
CN112860602A (en) * 2019-11-12 2021-05-28 北京地平线机器人技术研发有限公司 Method and device for controlling storage operation of region-of-interest data

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080133877A1 (en) * 2006-11-30 2008-06-05 Motorola, Inc. Method and apparatus for memory address generation using dynamic stream descriptors
US20110304447A1 (en) * 2010-06-15 2011-12-15 Rohm Co., Ltd. Drive recorder
CN105528179A (en) * 2014-10-17 2016-04-27 卡巴斯基实验室股份制公司 System and method of transfer of control between memory locations
US20170090777A1 (en) * 2015-09-30 2017-03-30 Western Digital Technologies, Inc. Data retention management for data storage device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080133877A1 (en) * 2006-11-30 2008-06-05 Motorola, Inc. Method and apparatus for memory address generation using dynamic stream descriptors
US20110304447A1 (en) * 2010-06-15 2011-12-15 Rohm Co., Ltd. Drive recorder
CN105528179A (en) * 2014-10-17 2016-04-27 卡巴斯基实验室股份制公司 System and method of transfer of control between memory locations
US20170090777A1 (en) * 2015-09-30 2017-03-30 Western Digital Technologies, Inc. Data retention management for data storage device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110428359A (en) * 2019-08-09 2019-11-08 南京地平线机器人技术有限公司 Device and method for handling regions of interest data
CN110428359B (en) * 2019-08-09 2022-12-06 南京地平线机器人技术有限公司 Apparatus and method for processing region of interest data
CN112406884A (en) * 2019-08-20 2021-02-26 北京地平线机器人技术研发有限公司 Vehicle driving state recognition method and device, storage medium and electronic equipment
CN112406884B (en) * 2019-08-20 2022-03-15 北京地平线机器人技术研发有限公司 Vehicle driving state recognition method and device, storage medium and electronic equipment
CN112860602A (en) * 2019-11-12 2021-05-28 北京地平线机器人技术研发有限公司 Method and device for controlling storage operation of region-of-interest data
CN112860602B (en) * 2019-11-12 2024-05-03 北京地平线机器人技术研发有限公司 Method and device for controlling storage operation of region-of-interest data

Also Published As

Publication number Publication date
CN109727187B (en) 2023-05-30

Similar Documents

Publication Publication Date Title
US11803404B2 (en) Deep learning algorithm compiling method, device, and related product
US9934153B2 (en) Patch memory system
US11321092B1 (en) Tensor-based memory access
EP4372620A2 (en) Neural network processor and neural network computation method
KR20190029515A (en) An arithmetic unit that supports arithmetic data with different bit widths, arithmetic method, and arithmetic unit
TWI743627B (en) Method and device for accessing tensor data
CN112070202B (en) Fusion graph generation method and device and computer readable storage medium
CN102890625A (en) Arithmetic and control unit, arithmetic and control method, program and parallel processor
CN109727187A (en) Method and apparatus for adjusting the storage location of multiple semi-cylindrical hills data
CN116167447B (en) Quantum circuit processing method and device and electronic equipment
US7999808B1 (en) Parallel processing system, method, and computer program product for executing node traversal or primitive intersection
CN114692823A (en) Operator fusion method and device, storage medium and electronic equipment
CN113313247A (en) Operation method of sparse neural network based on data flow architecture
CN118114737A (en) Method and equipment for optimizing back propagation of Attention operator
CN116187464A (en) Blind quantum computing processing method, device and electronic equipment
CN112256632B (en) Instruction distribution method and system in reconfigurable processor
CN118264675A (en) A data copying method, device, storage medium and program product
JP7069898B2 (en) Learning identification device and learning identification method
US20190197767A1 (en) Surface extrction method, apparatus, and non-transitory computer readable storage medium thereof
CN105511867A (en) Optimization mode automatic generation method and optimization device
CN118210554B (en) Processor, server, data processing method and device, storage medium and product
CN112463158A (en) Compiling method, compiling device, electronic equipment and storage medium
US12288373B2 (en) Method of processing image, electronic device, storage medium, and program product
CN116225640A (en) Concurrent Construction Method of Welding Digital Twin 3D Scene Model
CN110955386B (en) Method for managing the provision of information, such as instructions, to a microprocessor and corresponding system

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant