CN109727862A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN109727862A CN109727862A CN201811631049.1A CN201811631049A CN109727862A CN 109727862 A CN109727862 A CN 109727862A CN 201811631049 A CN201811631049 A CN 201811631049A CN 109727862 A CN109727862 A CN 109727862A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 132
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000463 material Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- 229910002704 AlGaN Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- -1 nitride compound Chemical class 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 1
- 230000005669 field effect Effects 0.000 description 15
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 10
- 229910002601 GaN Inorganic materials 0.000 description 9
- 229910017083 AlN Inorganic materials 0.000 description 4
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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Abstract
The application proposes a kind of method, semi-conductor device manufacturing method, comprising: provides wafer, the wafer includes N number of semiconductor structure, and the semiconductor structure includes semiconductor layer and the source electrode and drain electrode on the semiconductor layer；First grid is formed between the source electrode and drain electrode on the first semiconductor structure；First medium layer is formed on wafer, and forms second grid on the first medium layer between the source electrode and drain electrode of the second semiconductor structure；Second dielectric layer is formed on wafer, and third grid is formed in the second dielectric layer between the source electrode and drain electrode of third semiconductor structure；The rest may be inferred, N dielectric layer is formed on the wafer, and N+1 grid is formed on the N dielectric layer between the source electrode and drain electrode of N+1 semiconductor structure, wherein the N is the positive integer greater than 1.The semiconductor devices and its manufacturing method that the application is proposed, by forming the dielectric layer of different-thickness in the devices to improve its linearity.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to semiconductor devices and its manufacturing method.
Background technique
There is broad stopband, high electron mobility, high breakdown potential with the third generation semiconductor material that gallium nitride (GaN) is representative
The excellent characteristics such as pressure, therefore the high electron mobility field-effect tube (HEMT) based on gallium nitride material is widely used in radar,
Microwave communication and high voltage power device field.With the fast development of Modern wireless communication, various non-constant enveloped modulation modes
It is applied widely with multi-transceiver technology, these signals have the characteristics that wide bandwidth and high peak-to-average power ratio (PAR), therefore are directed to this
In the RF power amplification circuit of class signal, the linearity of field-effect tube becomes a very important index.If the line of pipe
Property degree it is poor, then will lead to other than spread spectrum to signal bandwidth, interfere adjacency channel, reduce adjacent channel leakage ratio (ACLR) property
Energy.Even if the linearity fluctuation of power amplifier tube also results in distortion and increases, to reduce the mistake of receiver in signal bandwidth
Difference vector amplitude (EVM) performance increases the bit error rate (BER).The HEMT device of gallium nitride base is high-power due to being chiefly used in, high frequency
Rate, the application of big bandwidth, therefore its linearity are most important to the performance of entire radio-frequency front-end.When the dynamic of input signal
When range expands, the quiescent point of gallium nitride HEMT device is affected, so that the amplitude and phase of device transmit spy
Property change, to output signal generate distortion distortion, i.e., generation linearity problems.How the linearity of HEMT device is improved
Can, it is always the technological difficulties of gallium nitride radio-frequency devices.Majority application using back-off, is born instead from the angle of system
Feedback, feedforward, the methods of digital pre-distortion (DPD) cooperate the nonlinearity of pipe, but to tackle the problem at its root, and still need to
From the angle of device, improve the linearity performance of pipe itself.
Summary of the invention
The application proposes a kind of method, semi-conductor device manufacturing method, comprising:
Wafer is provided, the wafer includes N+1 semiconductor structure, each semiconductor structure include semiconductor layer with
Source electrode and drain electrode on the semiconductor layer；
First grid is formed between the source electrode and drain electrode on the first semiconductor structure；
First medium layer, and the first medium layer between the source electrode and drain electrode of the second semiconductor structure are formed on wafer
Upper formation second grid；
Second dielectric layer, and the second dielectric layer between the source electrode and drain electrode of third semiconductor structure are formed on wafer
Upper formation third grid；
The rest may be inferred, forms N dielectric layer on the wafer, and the source electrode and drain electrode of N+1 semiconductor structure it
Between N dielectric layer on form N+1 grid, wherein the N is positive integer greater than 1.
In one embodiment, the N dielectric layer with a thickness of 1nm-10nm.
In one embodiment, the thickness of each dielectric layer is equal.
In one embodiment, the semiconductor layer include substrate, the buffer layer on shown substrate and be located at institute
State the barrier layer on buffer layer.
In one embodiment, the cushioning layer material is GaN, InN, AlN, AlGaN or InGaN.
In one embodiment, the abarrier layer material is ternary or quaternary nitride compound semiconductor alloy.
Correspondingly, the application also proposes a kind of semiconductor devices, comprising:
Wafer and the N number of dielectric layer being sequentially laminated on the wafer, the wafer includes N+1 semiconductor structure, institute
Stating semiconductor structure includes semiconductor layer and the source electrode and drain electrode on the semiconductor layer；
And the first grid between the source electrode and drain electrode on first semiconductor structure；
The second grid between source electrode and drain electrode on the first medium layer and on the second semiconductor structure；
The third grid between source electrode and drain electrode in the second dielectric layer and on third semiconductor structure
The rest may be inferred, on the n-th dielectric layer and the source electrode and drain electrode that is located on the N+1 semiconductor structure it
Between N+1 grid, wherein the N is positive integer greater than 1.
The semiconductor devices and its manufacturing method that the application is proposed, by the dielectric layer for forming different-thickness in the devices
To improve its linearity.
Detailed description of the invention
Fig. 1 is the method, semi-conductor device manufacturing method flow chart that one embodiment proposes；
Fig. 2-Fig. 6 is the schematic diagram for indicating the semiconductor devices of manufacture one embodiment
Fig. 7 is the transconductance curve of the corresponding transconductance curve of three kinds of field-effect tube and the semiconductor devices being composed.
Specific embodiment
Semiconductor devices proposed by the present invention and its manufacturing method are made below in conjunction with the drawings and specific embodiments further
It is described in detail.According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that attached drawing
It is all made of very simplified form and uses non-accurate ratio, only to convenient, lucidly the aid illustration present invention is implemented
The purpose of example.
In the present invention, in " forming layer on another layer ", rectangular stratification on another layer may mean that, but different
Given layer directly physically or electrically contacts (for example, may exist other one or more layers between the two layers) with another layer.However,
In some embodiments, " ... it is upper to be formed " it can be connect with expression layer and the direct physics of at least part of another layer of top surface
Touching.
The application proposes a kind of method, semi-conductor device manufacturing method, as shown in Figure 1, comprising:
S10: providing wafer, and the wafer includes N+1 semiconductor structure, the semiconductor structure include semiconductor layer with
Source electrode and drain electrode on the semiconductor layer；
S20: first grid is formed between the source electrode and drain electrode on the first semiconductor structure；
S30: forming first medium layer on wafer, and first between the source electrode and drain electrode of the second semiconductor structure is situated between
Second grid is formed on matter layer；
S40: forming second dielectric layer on wafer, and second between the source electrode and drain electrode of third semiconductor structure is situated between
Third grid is formed on matter layer；
S50: the rest may be inferred, N dielectric layer is formed on the wafer, and in the source electrode of N+1 semiconductor structure and leakage
N+1 grid is formed on N dielectric layer between pole, wherein the N is the positive integer more than or equal to 1.
In one embodiment, the wafer is as shown in Fig. 2, include 4 semiconductor structures, respectively the first semiconductor junction
Structure 1, the second semiconductor structure 2, third semiconductor structure 3 and the 4th semiconductor structure 4.First semiconductor structure 1 includes
First semiconductor layer 10 and the first source electrode 11 and the first drain electrode 12 on first semiconductor layer 10, described the first half lead
Body layer 10 can be the epitaxial layer including substrate, buffer layer and barrier layer.Second semiconductor structure 2 includes the second semiconductor
Layer 20 and the second source electrode 21 and the second drain electrode 22 on second semiconductor layer 20, second semiconductor layer 20 can be with
It is the epitaxial layer for including substrate, buffer layer and barrier layer.The third semiconductor structure 3 includes third semiconductor layer 30 and is located at
Third source electrode 31 and third drain electrode 32 on the third semiconductor layer 30, the third semiconductor layer 30 can be including lining
Bottom, buffer layer and barrier layer epitaxial layer.4th semiconductor structure 4 is including the 4th semiconductor layer 40 and positioned at the described 4th
The 4th source electrode 41 and the 4th drain electrode 42 on semiconductor layer 40, the 4th semiconductor layer 40 can be including substrate, buffer layer
With the epitaxial layer of barrier layer.
Referring to FIG. 3, can be formed on first semiconductor structure 1 by the method for such as physical vapour deposition (PVD)
One grid 13, the first grid 13 are located between first source electrode 11 and the first drain electrode 12.The first grid 13, first
Semiconductor structure 1 constitutes the first field-effect tube.
Referring to FIG. 4, above-mentioned wafer can be put into atomic layer deposition (ALD), ultra-high vacuum CVD
(UHCVD), in the equipment such as molecular beam epitaxy (MBE), by the method for deposition, one dielectric layer 5 of growth regulation, shape on the wafer
At first medium layer 5 cover whole semiconductor structures.5 material of first medium layer can be silicon nitride (Si2N3), oxidation
Aluminium (Al2O3), zirconium oxide (ZrO2), silica (SiO2) etc..After the first medium layer 5 is formed, it can use and formation
The same method of first grid 13 forms second grid 23 on the first medium layer 5, and the second grid 23 is located at described
Between second source electrode 21 and the second drain electrode 22.The second grid 23, the second semiconductor structure 2 and the second source electrode 21 and second
First medium layer 5 between drain electrode 22 constitutes the second field-effect tube.
Referring to FIG. 5, second dielectric layer can be formed in crystal column surface by method same as first medium layer 5 is formed
6, the second dielectric layer 6 covers the first medium layer 5 and second grid 23.The same preceding layer of 6 material of second dielectric layer
Dielectric layer is identical.It, can be using method same as first grid 13 is formed described second after the second dielectric layer 6 is formed
Third grid 33 is formed on dielectric layer 6, the third grid 33 is located between the third source electrode 31 and third drain electrode 32.It is described
Second dielectric layer 6 and first between third grid 33, the second semiconductor structure 3 and third source electrode 31 and third drain electrode 32 are situated between
Matter layer 5 constitutes third field-effect tube.
Referring to FIG. 6, third dielectric layer can be formed in crystal column surface by method same as first medium layer 5 is formed
7, the third dielectric layer 7 covers the second dielectric layer 6 and third grid 33.The same preceding layer of 7 material of third dielectric layer
Dielectric layer is identical.It, can be using method same as first grid 13 is formed in the third after the third dielectric layer 7 is formed
The 4th grid 43 is formed on dielectric layer 7, the 4th grid 43 is located between the 4th source electrode 41 and the 4th drain electrode 42.It is described
Third dielectric layer 7, second between third grid 43, the 4th semiconductor structure 4 and the 4th source electrode 41 and the 4th drain electrode 42 is situated between
Matter layer 6 and first medium layer 5 constitute the 4th field-effect tube.
In the present embodiment, the first medium layer 5, second dielectric layer 6 and third dielectric layer 7 with a thickness of 1nm-
10nm can be 5nm, be also possible to first medium layer 3nm, second dielectric layer 5nm, third dielectric layer 7nm or first
Dielectric layer 8nm, second dielectric layer 6nm, third dielectric layer 6nm etc..
In the present embodiment, the first grid 13, second grid 23, third grid 22, the 4th grid 43 are along lengthwise side
To length can be each unequal, be also possible to the equal length of wherein certain two or three grid, for example, the first grid
The length of pole 13 is 200um, and the length of second grid 23 is 100um, the length of third grid 33 is 300um, the 4th grid 43
Length 200um.
In order to improve the linearity of semiconductor devices, present inventor has found by long-term experiment, passes through parallel connection
The assembling device that different medium thickness degree MIS field-effect tube is formed can effectively improve the linearity of device.RF front-end module
The important indicator of the measurement linearity is that the interference that the intermodulation distortion (IMD3) of intermodulation distortion (IM), especially 3 ranks generates directly is fallen
Near primary band, it can not filter out, noiseproof feature is caused to be deteriorated.The size of IMD3 distortion power is mainly joined by field-effect tube mutual conductance
Several second dervatives determines that the second dervative numerical value of mutual conductance is bigger, then IMD3 distortion power is higher.
Fig. 7 shows the mutual conductance for the compound tube that one is formed by the silicon nitride medium layer field-effect tube of 0nm, 5nm and 10nm
Data, ordinate indicate the second dervative (S/V of unit mutual conductance2/ mm), abscissa indicates grid voltage (V), three kinds of field-effect tube
Respective mutual conductance data have been also shown in the same figure.In the compound tube, the grid width of three kinds of field-effect tube is according to 0.13:
The ratio of 0.28:0.59 determines.The data that Fig. 7 is shown can see, the respective mutual conductance data of three kinds of field-effect tube (- 1,
2) fluctuated between it is larger, in order to reduce intermodulation distortion, it is necessary to the dynamic range of input signal (grid voltage) is limited, so that herein
In range, the second dervative of mutual conductance is in lesser numerical value；And when three kinds of pipes form combination with grid width ratio above-mentioned
After pipe, hence it is evident that mutual conductance data fluctuations are smaller, and the dynamic range of device expands, and the linearity is improved.
In the present embodiment, method, semi-conductor device manufacturing method the application proposed by taking 4 semiconductor structures as an example into
Row explanation, it will be appreciated by those skilled in the art that, the quantity of the semiconductor structure can be other, in N greater than 1
In the case of, it is applicable in the method proposed with the application.
Correspondingly, the application also proposes a kind of semiconductor devices, as shown in Figure 6, comprising: wafer, the wafer include 4
Semiconductor structure, respectively the first semiconductor structure 1, the second semiconductor structure 2, third semiconductor structure 3 and the 4th semiconductor
Structure 4.First semiconductor structure 1 includes the first semiconductor layer 10 and the first source on first semiconductor layer 10
Pole 11 and the first drain electrode 12.Second semiconductor structure 2 is including the second semiconductor layer 20 and is located at second semiconductor layer
The second source electrode 21 and the second drain electrode 22 on 20.The third semiconductor structure 3 includes third semiconductor layer 30 and is located at described
Third source electrode 31 and third drain electrode 32 on third semiconductor layer 30.4th semiconductor structure 4 includes the 4th semiconductor layer
40 and the 4th source electrode 41 on the 4th semiconductor layer 40 and the 4th drain electrode 42.First semiconductor layer 10, second
Semiconductor layer 20, third semiconductor layer 30 and the 4th semiconductor layer 40 can be including stacking gradually substrate, buffer layer and potential barrier
The epitaxial layer of layer.The substrate material includes but is not limited to the materials such as sapphire, silicon carbide, silicon, diamond, gallium nitride and aluminium nitride
Material.The buffer layer and the barrier layer are stacked to form hetero-junctions, and the buffer layer is close to described barrier layer one end
Surface forms two-dimensional electron gas (2DEG), and the 2DEG has high electron density and high electron mobility.It is typically heterogeneous to become
AlGaN/GaN, i.e., the described buffer layer are GaN, and the barrier layer is AlGaN.The buffer layer may be GaN, AlN,
The nitride such as AlGaN, InGaN, the barrier layer may be the ternarys such as InAlN, AlN, ScAlN or quaternary nitride
One or more of superpositions of semiconductor alloy material.The substrate with a thickness of 50um-1000um, the thickness of the barrier layer
For 3nm-100nm, the buffer layer with a thickness of 50nm-10000nm.
Have on the wafer and stack gradually there are three dielectric layer, respectively first medium layer 5, second dielectric layer 6 and the
Three dielectric layers 7.The first medium layer 5 is located on the wafer, and the second dielectric layer 6 is located on a dielectric layer 5, institute
Third dielectric layer 7 is stated to be located in shown second dielectric layer 6.The first medium layer 5, second dielectric layer 6 and third dielectric layer 7
Material can be silicon nitride or silica.The first medium layer 5, second dielectric layer 6 and third dielectric layer 7 with a thickness of
1nm-10nm can be 5nm, be also possible to first medium layer 3nm, second dielectric layer 5nm, third dielectric layer 7nm, either
First medium layer 8nm, second dielectric layer 6nm, third dielectric layer 6nm etc..
There is first grid 13, the first grid 13 is located at 11 He of the first source electrode on first semiconductor structure
Between first drain electrode 12.There is second grid 23, the second grid 23 is located at second source electrode on the first medium layer 5
21 and second drain electrode 22 between.There is third grid 33, the third grid 33 is located at the third in the second dielectric layer 6
Between source electrode 31 and third drain electrode 32.There is the 4th grid 43, the 4th grid 43 is located at described on the third dielectric layer 7
Between 4th source electrode 41 and the 4th drain electrode 42.First source electrode, the second source electrode, third source electrode and the 4th source electrode can be titanium,
Aluminium, nickel, in gold any a variety of compositions alloy.First drain electrode, the second drain electrode, third drain electrode and the 4th drain electrode can be
Titanium, aluminium, nickel, in gold any a variety of compositions alloy.The first grid, second grid, third grid and the 4th grid can be with
It is constituted for ni au or platinum/gold metal laminated.
The first grid 13, second grid 23, third grid 22, the 4th grid 43 can be each along the length of longitudinally
It is unequal, it is also possible to the equal length of two of them or three grids, for example, the length of the first grid 13 is
200um, the length 200um that the length of second grid 23 is 100um, the length of third grid 33 is 300um, the 4th grid 43.
In the present embodiment, the semiconductor devices proposed by taking 4 semiconductor structures as an example to the application is illustrated, this
Field technical staff is it will be appreciated that the quantity of the semiconductor structure can be other, in the case where N is greater than 1,
It is applicable in the structure proposed with the application.
The semiconductor devices and its manufacturing method that the application is proposed can be at one by controlling the thickness of dielectric layer
A variety of field-effect tube are formed on wafer, different field-effect tube can be effectively improved semiconductor device since the thickness of dielectric layer is different
The linearity of part.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (7)
1. a kind of method, semi-conductor device manufacturing method characterized by comprising
Wafer is provided, the wafer includes N+1 semiconductor structure, and the semiconductor structure includes semiconductor layer and is located at described
Source electrode and drain electrode on semiconductor layer；
First grid is formed between the source electrode and drain electrode on the first semiconductor structure；
First medium layer, and shape on the first medium layer between the source electrode and drain electrode of the second semiconductor structure are formed on wafer
At second grid；
Second dielectric layer, and shape in the second dielectric layer between the source electrode and drain electrode of third semiconductor structure are formed on wafer
At third grid；
The rest may be inferred, N dielectric layer is formed on the wafer, and between the source electrode and drain electrode of N+1 semiconductor structure
N+1 grid is formed on N dielectric layer, wherein the N is the positive integer greater than 1.
2. method, semi-conductor device manufacturing method according to claim 1, which is characterized in that the N dielectric layer with a thickness of
1nm-10nm。
3. method, semi-conductor device manufacturing method according to claim 1, which is characterized in that the thickness phase of each dielectric layer
Deng.
4. method, semi-conductor device manufacturing method according to claim 1, which is characterized in that the semiconductor layer include substrate,
Buffer layer on shown substrate and the barrier layer on the buffer layer.
5. method, semi-conductor device manufacturing method according to claim 4, which is characterized in that the cushioning layer material be GaN,
InN, AlN, AlGaN or InGaN.
6. method, semi-conductor device manufacturing method according to claim 4, which is characterized in that the abarrier layer material be ternary or
Person's quaternary nitride compound semiconductor alloy.
7. a kind of semiconductor devices characterized by comprising
Wafer and the N number of dielectric layer being sequentially laminated on the wafer, the wafer includes N+1 semiconductor structure, and described half
Conductor structure includes semiconductor layer and the source electrode and drain electrode on the semiconductor layer；
And the first grid between the source electrode and drain electrode on first semiconductor structure；
The second grid between source electrode and drain electrode on the first medium layer and on the second semiconductor structure；
The third grid between source electrode and drain electrode in the second dielectric layer and on third semiconductor structure
The rest may be inferred, between the source electrode and drain electrode on the n-th dielectric layer and on the N+1 semiconductor structure
N+1 grid, wherein the N is the positive integer greater than 1.
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| WO2021012340A1 (en) * | 2019-07-19 | 2021-01-28 | 中国电子科技集团公司第五十五研究所 | Gan high-electron-mobility transistor having splicing sub-device and manufacture method therefor |
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| US20090261384A1 (en) * | 2006-09-22 | 2009-10-22 | Korea Advanced Institute Of Science And Technology | Gallium nitride high electron mobility transistor having inner field-plate for high power applications |
| US20150221649A1 (en) * | 2013-03-15 | 2015-08-06 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Complementary Field Effect Transistors Using Gallium Polar and Nitrogen Polar III-Nitride Material |
| CN206412319U (en) * | 2016-05-30 | 2017-08-15 | 意法半导体股份有限公司 | High power and high-frequency HFET |
| CN209298117U (en) * | 2018-12-30 | 2019-08-23 | 苏州汉骅半导体有限公司 | Semiconductor devices |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021012340A1 (en) * | 2019-07-19 | 2021-01-28 | 中国电子科技集团公司第五十五研究所 | Gan high-electron-mobility transistor having splicing sub-device and manufacture method therefor |
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