CN111524924B - Chip packaging method and chip packaging structure - Google Patents
Chip packaging method and chip packaging structure Download PDFInfo
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- CN111524924B CN111524924B CN202010600939.7A CN202010600939A CN111524924B CN 111524924 B CN111524924 B CN 111524924B CN 202010600939 A CN202010600939 A CN 202010600939A CN 111524924 B CN111524924 B CN 111524924B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
- H10F39/024—Manufacture or treatment of image sensors covered by group H10F39/12 of coatings or optical elements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/198—Contact-type image sensors [CIS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/805—Coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/806—Optical elements or arrangements associated with the image sensors
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- Solid State Image Pick-Up Elements (AREA)
Abstract
本申请提供一种芯片封装方法及芯片封装结构，涉及芯片封装技术领域。其中，芯片封装方法包括：提供一晶圆，所述晶圆包括多个晶片区域，每一所述晶片区域包括感光区域以及焊盘区域，所述焊盘区域设置有焊盘；在所述晶圆的上表面设置一透光膜层；将所述透光膜层的位于每一所述焊盘区域上的部分去除以露出每一所述焊盘区域的焊盘，从而得到一晶圆结构；对所述晶圆结构进行切割及封装操作，以得到多个芯片封装结构。本申请提供的芯片封装方法，相对于其他方式的封装方法，加工流程短，工艺控制难度低，得到的封装体厚度更薄，使用材料更少。
The present application provides a chip packaging method and a chip packaging structure, and relates to the technical field of chip packaging. The chip packaging method includes: providing a wafer, the wafer includes a plurality of wafer regions, each of the wafer regions includes a photosensitive region and a pad region, and the pad region is provided with a pad; A light-transmitting film layer is arranged on the upper surface of the circle; the part of the light-transmitting film layer located on each of the pad regions is removed to expose the pads of each of the pad regions, thereby obtaining a wafer structure ; Perform cutting and packaging operations on the wafer structure to obtain a plurality of chip packaging structures. Compared with other packaging methods, the chip packaging method provided by the present application has the advantages of short processing flow, low difficulty in process control, thinner thickness of the obtained package body, and fewer materials used.
Description
Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip packaging method and a chip packaging structure.
Background
Cis (contact Image sensor), also known as a contact Image sensor, is a novel linear Image sensor, which is a photoelectric coupling Device researched and developed in recent years after a Charge-coupled Device (CCD). The electronic signal processing device can sense an optical signal and convert the optical signal into an electronic signal carrying image information, and has wide application in the market at present as a processing electronic device, such as being applied to intelligent terminals, cameras, scanning situation sensing and the like. In order to improve the imaging quality and the practicability of the product, the device is generally required to be packaged and then installed in a terminal device.
At present, the traditional packaging structure is mainly used for carrying out light transmission sealing by using a piece of glass on a photosensitive area of a chip, and a supporting structure is required to be made of glue or other materials around the photosensitive area during manufacturing so as to ensure that a certain height exists between a glass cover plate and the chip. However, the conventional production method has high requirements on packaging and complicated processes, and provides new challenges for quality and efficiency control in mass production.
Disclosure of Invention
An object of the embodiments of the present application is to provide a chip packaging method and a chip packaging structure, when packaging a chip, only one material is used above a photosensitive region, which can reduce the refraction times of light between interfaces, and meanwhile, since only a light-transmitting film layer needs to be arranged above the photosensitive region, the packaging process is simpler.
In a first aspect, an embodiment of the present application provides a chip packaging method, where the method includes: providing a wafer, wherein the wafer comprises a plurality of chip areas, each chip area comprises a photosensitive area and a bonding pad area, and the bonding pad area is provided with a bonding pad; arranging a light-transmitting film layer on the upper surface of the wafer; removing the part of the light-transmitting film layer, which is positioned on each bonding pad area, so as to expose the bonding pad of each bonding pad area, thereby obtaining a wafer structure; and cutting and packaging the wafer structure to obtain a plurality of chip packaging structures.
Compared with the packaging methods of other modes, the chip packaging method provided by the application has the advantages that the processing flow is short, the process control difficulty is low, the used materials are less, and because one material is only used above the photosensitive area, compared with the packaging mode that multiple materials are arranged above the photosensitive area, the refraction times of light rays between interfaces can be effectively reduced, and the photosensitive effect is better.
In a possible implementation manner, the dicing and packaging the wafer structure to obtain a plurality of chip package structures includes: cutting and separating the wafer structure into a plurality of chips corresponding to the chip areas, and connecting the bonding pads on the chips to a carrier plate by using wires; and coating glue between the carrier plate and the lead, and curing the glue to support and fix the arc formed by the lead.
In a possible embodiment, after disposing a light-transmitting film layer on the upper surface of the wafer, the method further includes: and thinning the lower surface of the wafer.
Since the transparent film layer is cured on the upper surface of the wafer before the wafer is thinned, the wafer can be thinned during the thinning operation, so that the thickness of the obtained chip packaging structure is also thinner, and the camera can be made thinner after the chip packaging structure is put into application, such as being used for manufacturing a camera.
In a possible embodiment, the disposing a light-transmitting film layer on the upper surface of the wafer includes: and carrying out film coating treatment on the upper surface of the wafer, and curing the film coated material to enable the film surface to be attached to the upper surface to form a light-transmitting film layer.
In one possible embodiment, the curing of the material of the coating includes: and carrying out ultraviolet curing or baking curing on the material of the coating film to cure the material of the coating film on the upper surface.
In a possible embodiment, the removing the portion of the light-transmitting film layer on each of the pad regions to expose the pad of each of the pad regions includes: determining the distance from the surface of the light-transmitting film layer far away from the upper surface to the bonding pad by using laser ranging, and removing the light-transmitting film layer on the bonding pad region by using a mechanical removal mode according to the distance; or, removing the light-transmitting film layer on the bonding pad area by using a laser mode.
In a second aspect, an embodiment of the present application provides a chip package structure, where the chip package structure includes: a carrier plate; the wafer is arranged on the carrier plate and comprises a photosensitive area and a bonding pad area, and the bonding pad area is provided with a bonding pad; a light-transmitting film layer arranged on the photosensitive region of the wafer; and the wire is used for electrically connecting the carrier plate with the bonding pad.
In one possible implementation, the chip package structure further includes: and the support colloid is positioned between the carrier plate and the lead so as to support and fix a wire arc formed by the lead.
In one possible embodiment, the thickness of the light-transmitting film layer is 65 to 95 micrometers.
In one possible embodiment, the light transmittance of the light-transmitting film layer is greater than 93% for light in a wavelength band of 380 to 780 nanometers.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a flowchart of a chip packaging method according to an embodiment of the present disclosure;
fig. 2 is a schematic view of a wafer according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram illustrating an implementation of steps 10-40 provided by an embodiment of the present application;
fig. 4 is a schematic diagram of a chip package structure according to an embodiment of the present disclosure;
fig. 5 is a schematic view of an application example of the chip package structure according to the embodiment of the present application.
Icon: 100-a wafer; 101-a wafer area; 102-a pad; 110-a light-transmissive film layer; 120-a carrier plate; 130-a wafer; 140-a wire; 150-supporting colloid.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
The embodiment of the application provides a chip packaging method which can be used for a packaging process of a light-transmitting chip (CIS chip), and also provides a chip packaging structure which can be manufactured by adopting the chip packaging method to obtain a light-transmitting chip packaging body. Fig. 1 shows a flowchart of a chip packaging method, which includes, as shown in fig. 1:
step 10: a wafer is provided, the wafer includes a plurality of chip areas, each chip area includes a photosensitive area and a bonding pad area, and the bonding pad area is provided with a bonding pad.
Fig. 2 shows a schematic diagram of a wafer, which includes a plurality of chip regions 101 on a wafer 100, and each chip region 101 has a desired integrated functional circuit fabricated thereon, and the integrated functional circuit converts a sensed optical signal into an electrical signal. Wafer 100 includes a top surface and a bottom surface, and each die area 101 has a light-sensing area and a pad area (not shown) on the top surface, and the integrated functional circuits sense external light through the light-sensing area on die area 101.
Step 20: a transparent film layer is disposed on the upper surface of the wafer.
A schematic diagram of the implementation of steps 10-40 is shown in fig. 3. Fig. 3 (a) provides a wafer, and fig. 3 (a) only shows two chip areas on the wafer, on which the bonding pads 102 are disposed. Specifically, step 20 is to perform film coating treatment on the upper surface of the wafer, and cure the material of the film coating to make the film surface adhere to the upper surface of the wafer, so as to form the light-transmitting film layer. The mode of curing the material of the coating film comprises the following steps: ultraviolet (UV) curing or bake curing.
As shown in fig. 3 (b), a film coating operation is performed on the entire wafer, and a thin film (transparent film layer 110) is formed on the wafer, wherein the thickness of the thin film is 65 to 95 μm, and the thickness is selected as follows: guarantee the luminousness of printing opacity rete and the material strength of rete, and reduce the degree of difficulty of getting rid of the rete material on pad surface on next step, if the rete is too thick, can influence the luminousness parameter of printing opacity rete, lead to the luminousness reduction of printing opacity rete, be unfavorable for the chip sensitization, if the rete is too thin (for example 1 micron), then the material strength that can lead to the rete is low excessively, lead to the rete breakable, be unfavorable for chip package and the operation is got rid of to the material on. The transparent film layer 110 is a high transmittance film, and in one embodiment, the transmittance of the transparent film layer is required to be: the light transmittance of the light ray in a 380-780 nanometer wave band is more than 93 percent. It is understood that for some products with lower requirements, the light transmittance requirement can be reduced appropriately, for example, the light transmittance for the light in the 380-780 nm wave band is greater than 60%.
And after the film covering, Ultraviolet (UV) curing or baking curing is adopted, so that the material of the film covering is cured on the upper surface of the wafer, and the baking curing adopts a high-pressure baking mode to eliminate film covering bubbles, or vacuum film covering is adopted and a common oven is used for baking.
Step 30: and removing the part of the light-transmitting film layer positioned on each bonding pad area to expose the bonding pad of each bonding pad area, thereby obtaining a wafer structure.
After the whole wafer is coated with a film, the bonding pad on the bonding pad region on each chip region is covered with a light-transmitting film layer, and the light-transmitting film layer is removed by a technical means to facilitate subsequent connection of the conductive wires, as shown in fig. 3 (c), it can be seen that the light-transmitting film layer above the bonding pad 102 is removed, so that the bonding pad 102 is exposed.
The material removal method comprises the following steps: and positioning through the surface pattern of the wafer or the position of the conductive bonding pad, and removing the light-transmitting film layer on each bonding pad area by mechanical removal or laser so as to expose the bonding pad of each bonding pad area. The mechanical removal method includes determining a distance from a surface of the transparent film layer, which is far away from the upper surface, to the pad by a distance measuring means (e.g., laser distance measurement), and performing mechanical removal according to the determined distance, for example, cutting the pad by using a wide tool, so as to expose the pad originally covered under the transparent film layer. Laser removal can control the laser energy, does not need distance measurement, has low precision requirement, is stable, has no mechanical cutting stress residue, and has better removal effect.
Optionally, after step 20, that is, after a light-transmitting film layer is disposed on the upper surface of the wafer, the chip packaging method further includes: and thinning the lower surface of the wafer, namely removing the redundant base material on the lower surface of the wafer by a certain thickness. After thinning treatment, the thermal resistance of the device of the integrated functional circuit can be further reduced, the working heat dissipation and cooling capacity of the chip can be improved, and subsequent packaging is facilitated. Wafer thinning belongs to a conventional process flow, and thinning can be performed by a grinding machine. The wafer thinning process may be performed after step 20, before step 30, or after step 30, and the order of the process is not limited in this embodiment.
Step 40: and cutting and packaging the wafer structure to obtain a plurality of chip packaging structures.
As shown in fig. 3 (d), the obtained wafer structure is diced into individual chips, and a plurality of chips are obtained. And mounting the single chip on a carrier plate, and bonding and interconnecting the chip and the carrier plate to complete circuit connection. Specifically, step 140 includes: cutting and separating the wafer structure into a plurality of chips corresponding to the chip areas, mounting the chips on a carrier plate, and connecting bonding pads on the chips to the carrier plate by using wires; and coating glue between the carrier plate and the lead, and curing the glue to support and fix the arc formed by the lead.
After a wafer structure from a previous process is subjected to a cutting process, the wafer structure is cut into a plurality of small chips, each chip corresponds to a chip area on the wafer, each chip includes a photosensitive area and a pad area, the pad area is provided with a corresponding pad, the cut chips are then attached to a corresponding carrier board by using glue or other connection methods, and then the pads of the chips are connected to corresponding pins of the carrier board by using thin metal wires (such as gold wires) or conductive resin to form a required circuit. And next, fixing and protecting the wire arc by using glue, and curing the glue to form a supporting colloid between the carrier plate and the wire after the glue is cured. And respectively carrying out the packaging steps on each wafer obtained by cutting to obtain a plurality of chip packaging structures.
Fig. 4 is a schematic diagram illustrating a chip package structure according to an embodiment of the present disclosure, where the chip package structure can be manufactured by the above chip packaging method, please refer to fig. 4, and the chip package structure includes:
a carrier 120;
a wafer 130 disposed on the carrier 120, the wafer 130 including a photosensitive region and a bonding pad region, the bonding pad region having a bonding pad 102;
a transparent film layer 110 disposed on the photosensitive region of the wafer 130;
and a conductive line 140 for electrically connecting the carrier board 120 with the pad 102.
Optionally, during the chip packaging process, glue is applied between the carrier 120 and the wires 140 and cured, and after curing, a support colloid 150 is formed between the carrier 120 and the wires 140 for supporting and fixing the wire arcs formed by the wires.
Optionally, the thickness of the light-transmitting film layer 110 is 65 to 95 micrometers, and the light transmittance of the light-transmitting film layer and the material strength of the film layer can be ensured within this thickness range. The transparent film layer 110 is a high transmittance film, and in one embodiment, the transmittance of the transparent film layer is required to be: the light transmittance of the light ray in a 380-780 nanometer wave band is more than 93 percent. It is understood that for some products with lower requirements, the light transmittance requirement can be reduced appropriately, for example, the light transmittance for the light in the 380-780 nm wave band is greater than 60%.
The application example of the chip package structure provided in this embodiment is shown in fig. 5, when external light enters the transparent light-transmitting film layer, most of the light enters the chip photosensitive region below the light-transmitting film layer through the light-transmitting film layer due to the high light transmittance of the light-transmitting film layer, and is sensed by the light-transmitting film layer.
It can be understood that the process flow of the chip packaging method provided by the embodiment includes: the method comprises the steps of wafer film covering, curing, wafer thinning, material removing, wafer cutting, wafer mounting (the wafer and the carrier plate are integrated), wire bonding, glue dispensing and glue curing. In addition, since only one material (i.e., the transparent film layer) is used above the photosensitive region, compared with a packaging method in which multiple materials are disposed above the photosensitive region, the number of refraction times of light between interfaces can be effectively reduced, and the photosensitive effect is better. Furthermore, the light-transmitting film layer is a thin film, so that the light-transmitting film layer, the wafer and the carrier plate can be ensured to be horizontal to each other only by simple installation, and the phenomenon that loss of light signals is increased due to refraction after light reaches the wafer and the process control difficulty is low is avoided. Since the transparent film layer is cured on the upper surface of the wafer before the wafer is thinned, the wafer can be thinned during the thinning operation, so that the thickness of the obtained chip packaging structure is also thinner, and the camera can be made thinner after the chip packaging structure is put into application, such as being used for manufacturing a camera.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
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| CN112054063B (en) * | 2020-09-07 | 2022-04-15 | 深圳市灵明光子科技有限公司 | Chip-scale packaging method, chip-scale packaging structure and photoelectric device |
| CN115432661B (en) * | 2021-05-27 | 2025-11-25 | 苏州固锝电子股份有限公司 | Low-stress MEMS packaging structure and packaging method |
| CN114883440A (en) * | 2022-05-19 | 2022-08-09 | 史先德 | Photosensitive chip packaging structure suitable for deep sea high pressure environment |
| CN115312404B (en) * | 2022-07-29 | 2023-05-12 | 深圳米飞泰克科技股份有限公司 | Packaging method and packaging structure of chip |
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| CN109545808A (en) * | 2018-11-12 | 2019-03-29 | 通富微电子股份有限公司 | A kind of semiconductor chip packaging method |
| CN109545806A (en) * | 2018-11-12 | 2019-03-29 | 通富微电子股份有限公司 | A kind of semiconductor chip packaging method |
| CN109545805A (en) * | 2018-11-12 | 2019-03-29 | 通富微电子股份有限公司 | A kind of semiconductor chip packaging method |
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| CN109524311A (en) * | 2018-11-12 | 2019-03-26 | 通富微电子股份有限公司 | A kind of semiconductor chip packaging method |
| CN109545808A (en) * | 2018-11-12 | 2019-03-29 | 通富微电子股份有限公司 | A kind of semiconductor chip packaging method |
| CN109545806A (en) * | 2018-11-12 | 2019-03-29 | 通富微电子股份有限公司 | A kind of semiconductor chip packaging method |
| CN109545805A (en) * | 2018-11-12 | 2019-03-29 | 通富微电子股份有限公司 | A kind of semiconductor chip packaging method |
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